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-rw-r--r--llvm/test/CodeGen/X86/setcc.ll13
-rw-r--r--llvm/test/CodeGen/X86/zext-shl.ll38
2 files changed, 51 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/setcc.ll b/llvm/test/CodeGen/X86/setcc.ll
new file mode 100644
index 00000000000..785a6a900b5
--- /dev/null
+++ b/llvm/test/CodeGen/X86/setcc.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
+
+define zeroext i16 @t1(i16 zeroext %x) nounwind readnone ssp {
+entry:
+; CHECK: t1:
+; CHECK: seta %al
+; CHECK: movzbl %al, %eax
+; CHECK: shll $5, %eax
+ %0 = icmp ugt i16 %x, 26 ; <i1> [#uses=1]
+ %iftmp.1.0 = select i1 %0, i16 32, i16 0 ; <i16> [#uses=1]
+ ret i16 %iftmp.1.0
+}
+
diff --git a/llvm/test/CodeGen/X86/zext-shl.ll b/llvm/test/CodeGen/X86/zext-shl.ll
new file mode 100644
index 00000000000..bc3198a9d17
--- /dev/null
+++ b/llvm/test/CodeGen/X86/zext-shl.ll
@@ -0,0 +1,38 @@
+; RUN: llc < %s -march=x86 | FileCheck %s
+
+define i32 @t1(i8 zeroext %x) nounwind readnone ssp {
+entry:
+; CHECK: t1:
+; CHECK: shll
+; CHECK-NOT: movzwl
+; CHECK: ret
+ %0 = zext i8 %x to i16
+ %1 = shl i16 %0, 5
+ %2 = zext i16 %1 to i32
+ ret i32 %2
+}
+
+define i32 @t2(i8 zeroext %x) nounwind readnone ssp {
+entry:
+; CHECK: t2:
+; CHECK: shrl
+; CHECK-NOT: movzwl
+; CHECK: ret
+ %0 = zext i8 %x to i16
+ %1 = lshr i16 %0, 3
+ %2 = zext i16 %1 to i32
+ ret i32 %2
+}
+
+define i32 @t3(i8 zeroext %x, i8 zeroext %y) nounwind readnone ssp {
+entry:
+; CHECK: t3:
+; CHECK: shll
+; CHECK-NOT: movzwl
+; CHECK: ret
+ %0 = zext i8 %x to i16
+ %1 = zext i8 %y to i16
+ %2 = shl i16 %0, %1
+ %3 = zext i16 %2 to i32
+ ret i32 %3
+}
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