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-rw-r--r--llvm/test/CodeGen/ARM/intrinsics-overflow.ll3
-rw-r--r--llvm/test/CodeGen/Thumb/peephole-cmp.mir226
-rw-r--r--llvm/test/CodeGen/Thumb2/peephole-cmp.mir43
3 files changed, 270 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/ARM/intrinsics-overflow.ll b/llvm/test/CodeGen/ARM/intrinsics-overflow.ll
index d4c20dfacce..c3f64072d7d 100644
--- a/llvm/test/CodeGen/ARM/intrinsics-overflow.ll
+++ b/llvm/test/CodeGen/ARM/intrinsics-overflow.ll
@@ -38,8 +38,7 @@ define i32 @sadd_overflow(i32 %a, i32 %b) #0 {
; ARM: movvc r[[R0]], #0
; ARM: mov pc, lr
- ; THUMBV6: adds r1, r0, r1
- ; THUMBV6: cmp r1, r0
+ ; THUMBV6: adds r0, r0, r1
; THUMBV6: bvc .LBB1_2
; THUMBV7: adds r[[R2:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]
diff --git a/llvm/test/CodeGen/Thumb/peephole-cmp.mir b/llvm/test/CodeGen/Thumb/peephole-cmp.mir
new file mode 100644
index 00000000000..33b1581cdce
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb/peephole-cmp.mir
@@ -0,0 +1,226 @@
+# RUN: llc -mtriple thumbv8m.base-none-eabi -run-pass=peephole-opt -verify-machineinstrs -o - %s | FileCheck %s
+--- |
+ target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+ target triple = "thumbv8m.base-none-none-eabi"
+
+ define i32 @test_subrr(i32 %a, i32 %b) { ret i32 %a }
+ define i32 @test_subrr_c(i32 %a, i32 %b) { ret i32 %a }
+ define i32 @test_subri3(i32 %a) { ret i32 %a }
+ define i32 @test_subri8(i32 %a) { ret i32 %a }
+ define i32 @test_addrr(i32 %a) { ret i32 %a }
+ define i32 @test_addri3(i32 %a) { ret i32 %a }
+ define i32 @test_addri8(i32 %a) { ret i32 %a }
+
+...
+---
+name: test_subrr
+liveins:
+ - { reg: '$r0', virtual-reg: '%1' }
+ - { reg: '$r1', virtual-reg: '%2' }
+body: |
+ bb.0:
+ successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ liveins: $r0, $r1
+
+ %2:tgpr = COPY $r1
+ %1:tgpr = COPY $r0
+ %0:tgpr, $cpsr = tSUBrr %2, %1, 14, $noreg
+ tCMPr %1, %2, 14, $noreg, implicit-def $cpsr
+ tBcc %bb.2, 3, $cpsr
+ tB %bb.1, 14, $noreg
+
+ bb.1:
+ $r0 = COPY %0
+ tBX_RET 14, $noreg, implicit $r0
+
+ bb.2:
+ %3:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
+ $r0 = COPY %3
+ tBX_RET 14, $noreg, implicit $r0
+
+# CHECK-LABEL: name: test_subrr
+# CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r1
+# CHECK-NEXT: [[COPY0:%[0-9]+]]:tgpr = COPY $r0
+# CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tSUBrr [[COPY1]], [[COPY0]], 14, $noreg
+# CHECK-NEXT: tBcc %bb.2, 8, $cpsr
+...
+---
+name: test_subrr_c
+liveins:
+ - { reg: '$r0', virtual-reg: '%1' }
+ - { reg: '$r1', virtual-reg: '%2' }
+body: |
+ bb.0:
+ successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ liveins: $r0, $r1
+
+ %2:tgpr = COPY $r1
+ %1:tgpr = COPY $r0
+ %0:tgpr, $cpsr = tSUBrr %1, %2, 14, $noreg
+ tCMPr %1, %2, 14, $noreg, implicit-def $cpsr
+ tBcc %bb.2, 3, $cpsr
+ tB %bb.1, 14, $noreg
+
+ bb.1:
+ $r0 = COPY %0
+ tBX_RET 14, $noreg, implicit $r0
+
+ bb.2:
+ %3:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
+ $r0 = COPY %3
+ tBX_RET 14, $noreg, implicit $r0
+
+# CHECK-LABEL: name: test_subrr_c
+# CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r1
+# CHECK-NEXT: [[COPY0:%[0-9]+]]:tgpr = COPY $r0
+# CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tSUBrr [[COPY0]], [[COPY1]], 14, $noreg
+# CHECK-NEXT: tBcc %bb.2, 3, $cpsr
+...
+---
+name: test_subri3
+liveins:
+ - { reg: '$r0', virtual-reg: '%1' }
+body: |
+ bb.0:
+ successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ liveins: $r0
+
+ %1:tgpr = COPY $r0
+ %0:tgpr, $cpsr = tSUBi3 %1, 1, 14, $noreg
+ tCMPi8 %1, 1, 14, $noreg, implicit-def $cpsr
+ tBcc %bb.2, 3, $cpsr
+ tB %bb.1, 14, $noreg
+
+ bb.1:
+ $r0 = COPY %0
+ tBX_RET 14, $noreg, implicit $r0
+
+ bb.2:
+ %2:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
+ $r0 = COPY %2
+ tBX_RET 14, $noreg, implicit $r0
+
+# CHECK-LABEL: name: test_subri3
+# CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
+# CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tSUBi3 [[COPY]], 1, 14, $noreg
+# CHECK-NEXT: tBcc %bb.2, 3, $cpsr
+...
+---
+name: test_subri8
+liveins:
+ - { reg: '$r0', virtual-reg: '%1' }
+body: |
+ bb.0:
+ successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ liveins: $r0
+
+ %1:tgpr = COPY $r0
+ %0:tgpr, $cpsr = tSUBi8 %1, 1, 14, $noreg
+ tCMPi8 %1, 1, 14, $noreg, implicit-def $cpsr
+ tBcc %bb.2, 3, $cpsr
+ tB %bb.1, 14, $noreg
+
+ bb.1:
+ $r0 = COPY %0
+ tBX_RET 14, $noreg, implicit $r0
+
+ bb.2:
+ %2:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
+ $r0 = COPY %2
+ tBX_RET 14, $noreg, implicit $r0
+
+# CHECK-LABEL: name: test_subri8
+# CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
+# CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tSUBi8 [[COPY]], 1, 14, $noreg
+# CHECK-NEXT: tBcc %bb.2, 3, $cpsr
+...
+---
+name: test_addrr
+liveins:
+ - { reg: '$r0', virtual-reg: '%1' }
+ - { reg: '$r1', virtual-reg: '%2' }
+body: |
+ bb.0:
+ successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ liveins: $r0, $r1
+
+ %2:tgpr = COPY $r1
+ %1:tgpr = COPY $r0
+ %0:tgpr, $cpsr = tADDrr %2, %1, 14, $noreg
+ tCMPr %0, %2, 14, $noreg, implicit-def $cpsr
+ tBcc %bb.2, 3, $cpsr
+ tB %bb.1, 14, $noreg
+
+ bb.1:
+ $r0 = COPY %0
+ tBX_RET 14, $noreg, implicit $r0
+
+ bb.2:
+ %3:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
+ $r0 = COPY %3
+ tBX_RET 14, $noreg, implicit $r0
+
+# CHECK-LABEL: name: test_addrr
+# CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r1
+# CHECK-NEXT: [[COPY0:%[0-9]+]]:tgpr = COPY $r0
+# CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tADDrr [[COPY1]], [[COPY0]], 14, $noreg
+# CHECK-NEXT: tBcc %bb.2, 2, $cpsr
+...
+---
+name: test_addri3
+liveins:
+ - { reg: '$r0', virtual-reg: '%1' }
+body: |
+ bb.0:
+ successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ liveins: $r0
+
+ %0:tgpr = COPY $r0
+ %1:tgpr, $cpsr = tADDi3 %0, 1, 14, $noreg
+ tCMPr %1, %0, 14, $noreg, implicit-def $cpsr
+ tBcc %bb.2, 3, $cpsr
+ tB %bb.1, 14, $noreg
+
+ bb.1:
+ $r0 = COPY %0
+ tBX_RET 14, $noreg, implicit $r0
+
+ bb.2:
+ %2:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
+ $r0 = COPY %2
+ tBX_RET 14, $noreg, implicit $r0
+
+# CHECK-LABEL: name: test_addri3
+# CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
+# CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tADDi3 [[COPY]], 1, 14, $noreg
+# CHECK-NEXT: tBcc %bb.2, 2, $cpsr
+...
+---
+name: test_addri8
+liveins:
+ - { reg: '$r0', virtual-reg: '%1' }
+body: |
+ bb.0:
+ successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ liveins: $r0
+
+ %0:tgpr = COPY $r0
+ %1:tgpr, $cpsr = tADDi8 %0, 10, 14, $noreg
+ tCMPr %1, %0, 14, $noreg, implicit-def $cpsr
+ tBcc %bb.2, 3, $cpsr
+ tB %bb.1, 14, $noreg
+
+ bb.1:
+ $r0 = COPY %0
+ tBX_RET 14, $noreg, implicit $r0
+
+ bb.2:
+ %2:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
+ $r0 = COPY %2
+ tBX_RET 14, $noreg, implicit $r0
+
+# CHECK-LABEL: name: test_addri8
+# CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
+# CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tADDi8 [[COPY]], 10, 14, $noreg
+# CHECK-NEXT: tBcc %bb.2, 2, $cpsr
+...
diff --git a/llvm/test/CodeGen/Thumb2/peephole-cmp.mir b/llvm/test/CodeGen/Thumb2/peephole-cmp.mir
new file mode 100644
index 00000000000..b033b4a3bfa
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb2/peephole-cmp.mir
@@ -0,0 +1,43 @@
+# RUN: llc -run-pass=peephole-opt -verify-machineinstrs -o - %s | FileCheck %s
+--- |
+ target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+ target triple = "thumbv7m-none-none-eabi"
+
+ define i32 @test_addir_frameindex(i32 %a) {
+ %f = alloca i32
+ ret i32 %a
+ }
+...
+---
+name: test_addir_frameindex
+liveins:
+ - { reg: '$r0', virtual-reg: '%0' }
+stack:
+ - { id: 0, name: f, type: default, offset: 0, size: 1, alignment: 4,
+ stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
+ local-offset: -4, debug-info-variable: '', debug-info-expression: '',
+ debug-info-location: '' }
+body: |
+ bb.0:
+ successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ liveins: $r0
+
+ %0:rgpr = COPY $r0
+ %1:gprnopc = t2ADDri %stack.0.f, 0, 14, $noreg, $noreg
+ t2CMPrr %1, %0, 14, $noreg, implicit-def $cpsr
+ t2Bcc %bb.2, 3, $cpsr
+ t2B %bb.1, 14, $noreg
+
+ bb.1:
+ $r0 = COPY %1
+ tBX_RET 14, $noreg
+
+ bb.2:
+ $r0 = COPY %0
+ tBX_RET 14, $noreg
+
+# CHECK-LABEL: name: test_addir_frameindex
+# CHECK: %1:gprnopc = t2ADDri %stack.0.f, 0, 14, $noreg, $noreg
+# CHECK-NEXT: t2CMPrr %1, %0, 14, $noreg, implicit-def $cpsr
+# CHECK-NEXT: t2Bcc %bb.2, 3, $cpsr
+...
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