diff options
Diffstat (limited to 'llvm/test/CodeGen')
36 files changed, 155 insertions, 150 deletions
diff --git a/llvm/test/CodeGen/PowerPC/2007-01-15-AsmDialect.ll b/llvm/test/CodeGen/PowerPC/2007-01-15-AsmDialect.ll index 57c3531c3da..ca134fa9be4 100644 --- a/llvm/test/CodeGen/PowerPC/2007-01-15-AsmDialect.ll +++ b/llvm/test/CodeGen/PowerPC/2007-01-15-AsmDialect.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ -; RUN: grep cntlzw +; RUN: grep cntlz define i32 @foo() nounwind { entry: diff --git a/llvm/test/CodeGen/PowerPC/2010-02-12-saveCR.ll b/llvm/test/CodeGen/PowerPC/2010-02-12-saveCR.ll index b0c37b80ed2..5932b6d75c0 100644 --- a/llvm/test/CodeGen/PowerPC/2010-02-12-saveCR.ll +++ b/llvm/test/CodeGen/PowerPC/2010-02-12-saveCR.ll @@ -9,13 +9,13 @@ entry: ; CHECK: mfcr [[T1:r[0-9]+]] ; cr2 ; CHECK: lis [[T2:r[0-9]+]], 1 ; CHECK: addi r3, r1, 72 -; CHECK: rlwinm [[T1]], [[T1]], 8, 0, 31 +; CHECK: rotlwi [[T1]], [[T1]], 8 ; CHECK: ori [[T2]], [[T2]], 34540 ; CHECK: stwx [[T1]], r1, [[T2]] ; CHECK: lis [[T3:r[0-9]+]], 1 ; CHECK: mfcr [[T4:r[0-9]+]] ; cr3 ; CHECK: ori [[T3]], [[T3]], 34536 -; CHECK: rlwinm [[T4]], [[T4]], 12, 0, 31 +; CHECK: rotlwi [[T4]], [[T4]], 12 ; CHECK: stwx [[T4]], r1, [[T3]] %x = alloca [100000 x i8] ; <[100000 x i8]*> [#uses=1] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] @@ -28,12 +28,12 @@ return: ; preds = %entry ; CHECK: lis [[T1:r[0-9]+]], 1 ; CHECK: ori [[T1]], [[T1]], 34536 ; CHECK: lwzx [[T1]], r1, [[T1]] -; CHECK: rlwinm [[T1]], [[T1]], 20, 0, 31 +; CHECK: rotlwi [[T1]], [[T1]], 20 ; CHECK: mtcrf 16, [[T1]] ; CHECK: lis [[T1]], 1 ; CHECK: ori [[T1]], [[T1]], 34540 ; CHECK: lwzx [[T1]], r1, [[T1]] -; CHECK: rlwinm [[T1]], [[T1]], 24, 0, 31 +; CHECK: rotlwi [[T1]], [[T1]], 24 ; CHECK: mtcrf 32, [[T1]] ret void } diff --git a/llvm/test/CodeGen/PowerPC/anon_aggr.ll b/llvm/test/CodeGen/PowerPC/anon_aggr.ll index e899cfa4ce0..9f9eed019c1 100644 --- a/llvm/test/CodeGen/PowerPC/anon_aggr.ll +++ b/llvm/test/CodeGen/PowerPC/anon_aggr.ll @@ -21,7 +21,7 @@ unequal: } ; CHECK-LABEL: func1: -; CHECK: cmpld {{[0-9]+}}, 4, 5 +; CHECK: cmpld {{([0-9]+,)?}}4, 5 ; CHECK-DAG: std 4, -[[OFFSET1:[0-9]+]] ; CHECK-DAG: std 5, -[[OFFSET2:[0-9]+]] ; CHECK: ld 3, -[[OFFSET1]](1) @@ -31,7 +31,7 @@ unequal: ; DARWIN32: mr ; DARWIN32: mr r[[REG1:[0-9]+]], r[[REGA:[0-9]+]] ; DARWIN32: mr r[[REG2:[0-9]+]], r[[REGB:[0-9]+]] -; DARWIN32: cmplw cr{{[0-9]+}}, r[[REGA]], r[[REGB]] +; DARWIN32: cmplw {{(cr[0-9]+,)?}}r[[REGA]], r[[REGB]] ; DARWIN32: stw r[[REG1]], -[[OFFSET1:[0-9]+]] ; DARWIN32: stw r[[REG2]], -[[OFFSET2:[0-9]+]] ; DARWIN32: lwz r3, -[[OFFSET1]] @@ -41,7 +41,7 @@ unequal: ; DARWIN64: mr ; DARWIN64: mr r[[REG1:[0-9]+]], r[[REGA:[0-9]+]] ; DARWIN64: mr r[[REG2:[0-9]+]], r[[REGB:[0-9]+]] -; DARWIN64: cmpld cr{{[0-9]+}}, r[[REGA]], r[[REGB]] +; DARWIN64: cmpld {{(cr[0-9]+,)?}}r[[REGA]], r[[REGB]] ; DARWIN64: std r[[REG1]], -[[OFFSET1:[0-9]+]] ; DARWIN64: std r[[REG2]], -[[OFFSET2:[0-9]+]] ; DARWIN64: ld r3, -[[OFFSET1]] @@ -63,7 +63,7 @@ unequal: ; CHECK-LABEL: func2: ; CHECK: ld [[REG2:[0-9]+]], 72(1) -; CHECK: cmpld {{[0-9]+}}, 4, [[REG2]] +; CHECK: cmpld {{([0-9]+,)?}}4, [[REG2]] ; CHECK-DAG: std [[REG2]], -[[OFFSET1:[0-9]+]] ; CHECK-DAG: std 4, -[[OFFSET2:[0-9]+]] ; CHECK: ld 3, -[[OFFSET2]](1) @@ -74,7 +74,7 @@ unequal: ; DARWIN32: lwz r[[REG2:[0-9]+]], 44(r[[REGSP]]) ; DARWIN32: mr ; DARWIN32: mr r[[REG3:[0-9]+]], r[[REGA:[0-9]+]] -; DARWIN32: cmplw cr{{[0-9]+}}, r[[REGA]], r[[REG2]] +; DARWIN32: cmplw {{(cr[0-9]+,)?}}r[[REGA]], r[[REG2]] ; DARWIN32: stw r[[REG3]], -[[OFFSET1:[0-9]+]] ; DARWIN32: stw r[[REG2]], -[[OFFSET2:[0-9]+]] ; DARWIN32: lwz r3, -[[OFFSET1]] @@ -84,7 +84,7 @@ unequal: ; DARWIN64: ld r[[REG2:[0-9]+]], 72(r1) ; DARWIN64: mr ; DARWIN64: mr r[[REG3:[0-9]+]], r[[REGA:[0-9]+]] -; DARWIN64: cmpld cr{{[0-9]+}}, r[[REGA]], r[[REG2]] +; DARWIN64: cmpld {{(cr[0-9]+,)?}}r[[REGA]], r[[REG2]] ; DARWIN64: std r[[REG3]], -[[OFFSET1:[0-9]+]] ; DARWIN64: std r[[REG2]], -[[OFFSET2:[0-9]+]] ; DARWIN64: ld r3, -[[OFFSET1]] @@ -108,7 +108,7 @@ unequal: ; CHECK-LABEL: func3: ; CHECK: ld [[REG3:[0-9]+]], 72(1) ; CHECK: ld [[REG4:[0-9]+]], 56(1) -; CHECK: cmpld {{[0-9]+}}, [[REG4]], [[REG3]] +; CHECK: cmpld {{([0-9]+,)?}}[[REG4]], [[REG3]] ; CHECK: std [[REG3]], -[[OFFSET1:[0-9]+]](1) ; CHECK: std [[REG4]], -[[OFFSET2:[0-9]+]](1) ; CHECK: ld 3, -[[OFFSET2]](1) @@ -119,7 +119,7 @@ unequal: ; DARWIN32: addi r[[REG2:[0-9]+]], r[[REGSP]], 24 ; DARWIN32: lwz r[[REG3:[0-9]+]], 44(r[[REGSP]]) ; DARWIN32: lwz r[[REG4:[0-9]+]], 32(r[[REGSP]]) -; DARWIN32: cmplw cr{{[0-9]+}}, r[[REG4]], r[[REG3]] +; DARWIN32: cmplw {{(cr[0-9]+,)?}}r[[REG4]], r[[REG3]] ; DARWIN32: stw r[[REG3]], -[[OFFSET1:[0-9]+]] ; DARWIN32: stw r[[REG4]], -[[OFFSET2:[0-9]+]] ; DARWIN32: lwz r3, -[[OFFSET2]] @@ -128,7 +128,7 @@ unequal: ; DARWIN64: _func3: ; DARWIN64: ld r[[REG3:[0-9]+]], 72(r1) ; DARWIN64: ld r[[REG4:[0-9]+]], 56(r1) -; DARWIN64: cmpld cr{{[0-9]+}}, r[[REG4]], r[[REG3]] +; DARWIN64: cmpld {{(cr[0-9]+,)?}}r[[REG4]], r[[REG3]] ; DARWIN64: std r[[REG3]], -[[OFFSET1:[0-9]+]] ; DARWIN64: std r[[REG4]], -[[OFFSET2:[0-9]+]] ; DARWIN64: ld r3, -[[OFFSET2]] @@ -153,7 +153,7 @@ unequal: ; CHECK-LABEL: func4: ; CHECK: ld [[REG3:[0-9]+]], 136(1) ; CHECK: ld [[REG2:[0-9]+]], 120(1) -; CHECK: cmpld {{[0-9]+}}, [[REG2]], [[REG3]] +; CHECK: cmpld {{([0-9]+,)?}}[[REG2]], [[REG3]] ; CHECK: std [[REG3]], -[[OFFSET2:[0-9]+]](1) ; CHECK: std [[REG2]], -[[OFFSET1:[0-9]+]](1) ; CHECK: ld 3, -[[OFFSET1]](1) @@ -164,7 +164,7 @@ unequal: ; DARWIN32: addi r[[REG1:[0-9]+]], r1, 100 ; DARWIN32: lwz r[[REG3:[0-9]+]], 108(r1) ; DARWIN32: mr r[[REG2:[0-9]+]], r[[REG4]] -; DARWIN32: cmplw cr{{[0-9]+}}, r[[REG4]], r[[REG3]] +; DARWIN32: cmplw {{(cr[0-9]+,)?}}r[[REG4]], r[[REG3]] ; DARWIN32: stw r[[REG2]], -[[OFFSET1:[0-9]+]] ; DARWIN32: stw r[[REG3]], -[[OFFSET2:[0-9]+]] ; DARWIN32: lwz r[[REG1]], -[[OFFSET1]] @@ -174,7 +174,7 @@ unequal: ; DARWIN64: ld r[[REG2:[0-9]+]], 120(r1) ; DARWIN64: ld r[[REG3:[0-9]+]], 136(r1) ; DARWIN64: mr r[[REG4:[0-9]+]], r[[REG2]] -; DARWIN64: cmpld cr{{[0-9]+}}, r[[REG2]], r[[REG3]] +; DARWIN64: cmpld {{(cr[0-9]+,)?}}r[[REG2]], r[[REG3]] ; DARWIN64: std r[[REG4]], -[[OFFSET1:[0-9]+]] ; DARWIN64: std r[[REG3]], -[[OFFSET2:[0-9]+]] ; DARWIN64: ld r3, -[[OFFSET1]] diff --git a/llvm/test/CodeGen/PowerPC/asm-constraints.ll b/llvm/test/CodeGen/PowerPC/asm-constraints.ll index 1cb00ca30fb..2d9b0eb591d 100644 --- a/llvm/test/CodeGen/PowerPC/asm-constraints.ll +++ b/llvm/test/CodeGen/PowerPC/asm-constraints.ll @@ -31,7 +31,7 @@ entry: ; CHECK-LABEL: @foo ; CHECK: ld [[REG:[0-9]+]], 0(4) -; CHECK: cmpw 0, [[REG]], [[REG]] +; CHECK: cmpw [[REG]], [[REG]] ; CHECK: bne- 0, .Ltmp[[TMP:[0-9]+]] ; CHECK: .Ltmp[[TMP]]: ; CHECK: isync diff --git a/llvm/test/CodeGen/PowerPC/atomic-2.ll b/llvm/test/CodeGen/PowerPC/atomic-2.ll index b4b95a2baab..1857d5d697e 100644 --- a/llvm/test/CodeGen/PowerPC/atomic-2.ll +++ b/llvm/test/CodeGen/PowerPC/atomic-2.ll @@ -84,7 +84,7 @@ define void @atomic_store(i64* %mem, i64 %val) nounwind { entry: ; CHECK: @atomic_store store atomic i64 %val, i64* %mem release, align 64 -; CHECK: sync 1 +; CHECK: lwsync ; CHECK-NOT: stdcx ; CHECK: std ret void @@ -96,7 +96,7 @@ entry: %tmp = load atomic i64, i64* %mem acquire, align 64 ; CHECK-NOT: ldarx ; CHECK: ld -; CHECK: sync 1 +; CHECK: lwsync ret i64 %tmp } diff --git a/llvm/test/CodeGen/PowerPC/atomics-fences.ll b/llvm/test/CodeGen/PowerPC/atomics-fences.ll index 862bd173fda..09dd61f4ac5 100644 --- a/llvm/test/CodeGen/PowerPC/atomics-fences.ll +++ b/llvm/test/CodeGen/PowerPC/atomics-fences.ll @@ -5,16 +5,16 @@ ; Fences define void @fence_acquire() { ; CHECK-LABEL: fence_acquire -; CHECK: sync 1 -; PPC440-NOT: sync 1 +; CHECK: lwsync +; PPC440-NOT: lwsync ; PPC440: msync fence acquire ret void } define void @fence_release() { ; CHECK-LABEL: fence_release -; CHECK: sync 1 -; PPC440-NOT: sync 1 +; CHECK: lwsync +; PPC440-NOT: lwsync ; PPC440: msync fence release ret void diff --git a/llvm/test/CodeGen/PowerPC/atomics-indexed.ll b/llvm/test/CodeGen/PowerPC/atomics-indexed.ll index b9ec3c669ba..2f1a0b9f0b5 100644 --- a/llvm/test/CodeGen/PowerPC/atomics-indexed.ll +++ b/llvm/test/CodeGen/PowerPC/atomics-indexed.ll @@ -11,7 +11,7 @@ define i8 @load_x_i8_seq_cst([100000 x i8]* %mem) { ; CHECK-LABEL: load_x_i8_seq_cst ; CHECK: sync 0 ; CHECK: lbzx -; CHECK: sync 1 +; CHECK: lwsync %ptr = getelementptr inbounds [100000 x i8], [100000 x i8]* %mem, i64 0, i64 90000 %val = load atomic i8, i8* %ptr seq_cst, align 1 ret i8 %val @@ -19,7 +19,7 @@ define i8 @load_x_i8_seq_cst([100000 x i8]* %mem) { define i16 @load_x_i16_acquire([100000 x i16]* %mem) { ; CHECK-LABEL: load_x_i16_acquire ; CHECK: lhzx -; CHECK: sync 1 +; CHECK: lwsync %ptr = getelementptr inbounds [100000 x i16], [100000 x i16]* %mem, i64 0, i64 90000 %val = load atomic i16, i16* %ptr acquire, align 2 ret i16 %val @@ -54,7 +54,7 @@ define void @store_x_i8_seq_cst([100000 x i8]* %mem) { } define void @store_x_i16_release([100000 x i16]* %mem) { ; CHECK-LABEL: store_x_i16_release -; CHECK: sync 1 +; CHECK: lwsync ; CHECK: sthx %ptr = getelementptr inbounds [100000 x i16], [100000 x i16]* %mem, i64 0, i64 90000 store atomic i16 42, i16* %ptr release, align 2 @@ -71,7 +71,7 @@ define void @store_x_i32_monotonic([100000 x i32]* %mem) { define void @store_x_i64_unordered([100000 x i64]* %mem) { ; CHECK-LABEL: store_x_i64_unordered ; CHECK-NOT: sync 0 -; CHECK-NOT: sync 1 +; CHECK-NOT: lwsync ; PPC32: __sync_ ; PPC64-NOT: __sync_ ; PPC64: stdx diff --git a/llvm/test/CodeGen/PowerPC/atomics.ll b/llvm/test/CodeGen/PowerPC/atomics.ll index fe4791ec193..18038d42f33 100644 --- a/llvm/test/CodeGen/PowerPC/atomics.ll +++ b/llvm/test/CodeGen/PowerPC/atomics.ll @@ -27,7 +27,7 @@ define i32 @load_i32_acquire(i32* %mem) { ; CHECK-LABEL: load_i32_acquire ; CHECK: lwz %val = load atomic i32, i32* %mem acquire, align 4 -; CHECK: sync 1 +; CHECK: lwsync ret i32 %val } define i64 @load_i64_seq_cst(i64* %mem) { @@ -37,7 +37,7 @@ define i64 @load_i64_seq_cst(i64* %mem) { ; PPC64-NOT: __sync_ ; PPC64: ld %val = load atomic i64, i64* %mem seq_cst, align 8 -; CHECK: sync 1 +; CHECK: lwsync ret i64 %val } @@ -58,7 +58,7 @@ define void @store_i16_monotonic(i16* %mem) { } define void @store_i32_release(i32* %mem) { ; CHECK-LABEL: store_i32_release -; CHECK: sync 1 +; CHECK: lwsync ; CHECK: stw store atomic i32 42, i32* %mem release, align 4 ret void @@ -78,7 +78,7 @@ define i8 @cas_strong_i8_sc_sc(i8* %mem) { ; CHECK-LABEL: cas_strong_i8_sc_sc ; CHECK: sync 0 %val = cmpxchg i8* %mem, i8 0, i8 1 seq_cst seq_cst -; CHECK: sync 1 +; CHECK: lwsync %loaded = extractvalue { i8, i1} %val, 0 ret i8 %loaded } @@ -86,21 +86,21 @@ define i16 @cas_weak_i16_acquire_acquire(i16* %mem) { ; CHECK-LABEL: cas_weak_i16_acquire_acquire ;CHECK-NOT: sync %val = cmpxchg weak i16* %mem, i16 0, i16 1 acquire acquire -; CHECK: sync 1 +; CHECK: lwsync %loaded = extractvalue { i16, i1} %val, 0 ret i16 %loaded } define i32 @cas_strong_i32_acqrel_acquire(i32* %mem) { ; CHECK-LABEL: cas_strong_i32_acqrel_acquire -; CHECK: sync 1 +; CHECK: lwsync %val = cmpxchg i32* %mem, i32 0, i32 1 acq_rel acquire -; CHECK: sync 1 +; CHECK: lwsync %loaded = extractvalue { i32, i1} %val, 0 ret i32 %loaded } define i64 @cas_weak_i64_release_monotonic(i64* %mem) { ; CHECK-LABEL: cas_weak_i64_release_monotonic -; CHECK: sync 1 +; CHECK: lwsync %val = cmpxchg weak i64* %mem, i64 0, i64 1 release monotonic ; CHECK-NOT: [sync ] %loaded = extractvalue { i64, i1} %val, 0 @@ -118,19 +118,19 @@ define i16 @xor_i16_seq_cst(i16* %mem, i16 %operand) { ; CHECK-LABEL: xor_i16_seq_cst ; CHECK: sync 0 %val = atomicrmw xor i16* %mem, i16 %operand seq_cst -; CHECK: sync 1 +; CHECK: lwsync ret i16 %val } define i32 @xchg_i32_acq_rel(i32* %mem, i32 %operand) { ; CHECK-LABEL: xchg_i32_acq_rel -; CHECK: sync 1 +; CHECK: lwsync %val = atomicrmw xchg i32* %mem, i32 %operand acq_rel -; CHECK: sync 1 +; CHECK: lwsync ret i32 %val } define i64 @and_i64_release(i64* %mem, i64 %operand) { ; CHECK-LABEL: and_i64_release -; CHECK: sync 1 +; CHECK: lwsync %val = atomicrmw and i64* %mem, i64 %operand release ; CHECK-NOT: [sync ] ret i64 %val diff --git a/llvm/test/CodeGen/PowerPC/bperm.ll b/llvm/test/CodeGen/PowerPC/bperm.ll index c489c1f90a8..c5a728859a0 100644 --- a/llvm/test/CodeGen/PowerPC/bperm.ll +++ b/llvm/test/CodeGen/PowerPC/bperm.ll @@ -22,15 +22,15 @@ entry: ret i64 %0 ; CHECK-LABEL: @bs8 -; CHECK-DAG: rldicl [[REG1:[0-9]+]], 3, 16, 0 -; CHECK-DAG: rldicl [[REG2:[0-9]+]], 3, 8, 0 -; CHECK-DAG: rldicl [[REG3:[0-9]+]], 3, 24, 0 +; CHECK-DAG: rotldi [[REG1:[0-9]+]], 3, 16 +; CHECK-DAG: rotldi [[REG2:[0-9]+]], 3, 8 +; CHECK-DAG: rotldi [[REG3:[0-9]+]], 3, 24 ; CHECK-DAG: rldimi [[REG2]], [[REG1]], 8, 48 -; CHECK-DAG: rldicl [[REG4:[0-9]+]], 3, 32, 0 +; CHECK-DAG: rotldi [[REG4:[0-9]+]], 3, 32 ; CHECK-DAG: rldimi [[REG2]], [[REG3]], 16, 40 -; CHECK-DAG: rldicl [[REG5:[0-9]+]], 3, 48, 0 +; CHECK-DAG: rotldi [[REG5:[0-9]+]], 3, 48 ; CHECK-DAG: rldimi [[REG2]], [[REG4]], 24, 32 -; CHECK-DAG: rldicl [[REG6:[0-9]+]], 3, 56, 0 +; CHECK-DAG: rotldi [[REG6:[0-9]+]], 3, 56 ; CHECK-DAG: rldimi [[REG2]], [[REG5]], 40, 16 ; CHECK-DAG: rldimi [[REG2]], [[REG6]], 48, 8 ; CHECK-DAG: rldimi [[REG2]], 3, 56, 0 @@ -46,7 +46,7 @@ entry: ; CHECK-LABEL: @test1 ; CHECK-DAG: li [[REG1:[0-9]+]], 11375 -; CHECK-DAG: rldicl [[REG3:[0-9]+]], 4, 56, 0 +; CHECK-DAG: rotldi [[REG3:[0-9]+]], 4, 56 ; CHECK-DAG: sldi [[REG2:[0-9]+]], [[REG1]], 19 ; CHECK: and 3, [[REG3]], [[REG2]] ; CHECK: blr @@ -60,7 +60,7 @@ entry: ; CHECK-LABEL: @test2 ; CHECK-DAG: lis [[REG1:[0-9]+]], 474 -; CHECK-DAG: rldicl [[REG5:[0-9]+]], 4, 58, 0 +; CHECK-DAG: rotldi [[REG5:[0-9]+]], 4, 58 ; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 3648 ; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 32 ; CHECK-DAG: oris [[REG4:[0-9]+]], [[REG3]], 25464 @@ -76,7 +76,7 @@ entry: ; CHECK-LABEL: @test3 ; CHECK-DAG: lis [[REG1:[0-9]+]], 170 -; CHECK-DAG: rldicl [[REG4:[0-9]+]], 3, 34, 0 +; CHECK-DAG: rotldi [[REG4:[0-9]+]], 3, 34 ; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 22861 ; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 34 ; CHECK: and 3, [[REG4]], [[REG3]] @@ -90,7 +90,7 @@ entry: ret i64 %and ; CHECK-LABEL: @test4 -; CHECK: rldicl [[REG1:[0-9]+]], 4, 49, 0 +; CHECK: rotldi [[REG1:[0-9]+]], 4, 49 ; CHECK: andis. 3, [[REG1]], 888 ; CHECK: blr } @@ -103,7 +103,7 @@ entry: ; CHECK-LABEL: @test5 ; CHECK-DAG: lis [[REG1:[0-9]+]], 3703 -; CHECK-DAG: rldicl [[REG4:[0-9]+]], 4, 12, 0 +; CHECK-DAG: rotldi [[REG4:[0-9]+]], 4, 12 ; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 35951 ; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 19 ; CHECK: and 3, [[REG4]], [[REG3]] @@ -148,7 +148,7 @@ entry: ; CHECK-LABEL: @test8 ; CHECK-DAG: lis [[REG1:[0-9]+]], 4 -; CHECK-DAG: rldicl [[REG4:[0-9]+]], 3, 63, 0 +; CHECK-DAG: rotldi [[REG4:[0-9]+]], 3, 63 ; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 60527 ; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 19 ; CHECK: and 3, [[REG4]], [[REG3]] @@ -166,8 +166,8 @@ entry: ; CHECK-LABEL: @test9 ; CHECK-DAG: lis [[REG1:[0-9]+]], 1440 -; CHECK-DAG: rldicl [[REG5:[0-9]+]], 4, 62, 0 -; CHECK-DAG: rldicl [[REG6:[0-9]+]], 4, 50, 0 +; CHECK-DAG: rotldi [[REG5:[0-9]+]], 4, 62 +; CHECK-DAG: rotldi [[REG6:[0-9]+]], 4, 50 ; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 4 ; CHECK-DAG: rldimi [[REG6]], [[REG5]], 53, 0 ; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 32 @@ -187,8 +187,8 @@ entry: ; CHECK-LABEL: @test10 ; CHECK-DAG: lis [[REG1:[0-9]+]], 1 -; CHECK-DAG: rldicl [[REG6:[0-9]+]], 3, 25, 0 -; CHECK-DAG: rldicl [[REG7:[0-9]+]], 3, 37, 0 +; CHECK-DAG: rotldi [[REG6:[0-9]+]], 3, 25 +; CHECK-DAG: rotldi [[REG7:[0-9]+]], 3, 37 ; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 8183 ; CHECK-DAG: ori [[REG3:[0-9]+]], [[REG1]], 50017 ; CHECK-DAG: sldi [[REG4:[0-9]+]], [[REG2]], 25 diff --git a/llvm/test/CodeGen/PowerPC/cmpb-ppc32.ll b/llvm/test/CodeGen/PowerPC/cmpb-ppc32.ll index 639ed887b97..b5cb0935d88 100644 --- a/llvm/test/CodeGen/PowerPC/cmpb-ppc32.ll +++ b/llvm/test/CodeGen/PowerPC/cmpb-ppc32.ll @@ -17,7 +17,7 @@ entry: ; CHECK-LABEL: @test16 ; CHECK: cmpb [[REG1:[0-9]+]], 4, 3 -; CHECK: rlwinm 3, [[REG1]], 0, 16, 31 +; CHECK: clrlwi 3, [[REG1]], 16 ; CHECK: blr } diff --git a/llvm/test/CodeGen/PowerPC/cmpb.ll b/llvm/test/CodeGen/PowerPC/cmpb.ll index 7d0c0ab3316..d1c951df962 100644 --- a/llvm/test/CodeGen/PowerPC/cmpb.ll +++ b/llvm/test/CodeGen/PowerPC/cmpb.ll @@ -17,7 +17,7 @@ entry: ; CHECK-LABEL: @test16 ; CHECK: cmpb [[REG1:[0-9]+]], 4, 3 -; CHECK: rldicl 3, [[REG1]], 0, 48 +; CHECK: clrldi 3, [[REG1]], 48 ; CHECK: blr } @@ -73,7 +73,7 @@ entry: ; CHECK-LABEL: @test16p3 ; CHECK: cmpb [[REG1:[0-9]+]], 4, 3 -; CHECK: rldicl [[REG2:[0-9]+]], [[REG1]], 0, 55 +; CHECK: clrldi [[REG2:[0-9]+]], [[REG1]], 55 ; CHECK: xori 3, [[REG2]], 1280 ; CHECK: blr } @@ -99,7 +99,7 @@ entry: ; CHECK-LABEL: @test32 ; CHECK: cmpb [[REG1:[0-9]+]], 4, 3 -; CHECK: rldicl 3, [[REG1]], 0, 32 +; CHECK: clrldi 3, [[REG1]], 32 ; CHECK: blr } diff --git a/llvm/test/CodeGen/PowerPC/compare-simm.ll b/llvm/test/CodeGen/PowerPC/compare-simm.ll index 94c5c0290f5..12eff7bb181 100644 --- a/llvm/test/CodeGen/PowerPC/compare-simm.ll +++ b/llvm/test/CodeGen/PowerPC/compare-simm.ll @@ -1,7 +1,9 @@ -; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ -; RUN: grep "cmpwi cr0, r3, -1" +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | FileCheck %s define i32 @test(i32 %x) nounwind { +; CHECK-LABEL: @test +; CHECK: cmpwi r3, -1 + %c = icmp eq i32 %x, -1 br i1 %c, label %T, label %F T: diff --git a/llvm/test/CodeGen/PowerPC/crbit-asm.ll b/llvm/test/CodeGen/PowerPC/crbit-asm.ll index 373e334f02b..36de3435a08 100644 --- a/llvm/test/CodeGen/PowerPC/crbit-asm.ll +++ b/llvm/test/CodeGen/PowerPC/crbit-asm.ll @@ -12,7 +12,7 @@ entry: ; CHECK-LABEL: @testi1 ; CHECK-DAG: andi. {{[0-9]+}}, 3, 1 ; CHECK-DAG: li [[REG1:[0-9]+]], 0 -; CHECK-DAG: cror [[REG2:[0-9]+]], 1, 1 +; CHECK-DAG: crmove [[REG2:[0-9]+]], 1 ; CHECK-DAG: andi. {{[0-9]+}}, 4, 1 ; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1 ; CHECK-DAG: li [[REG4:[0-9]+]], 1 @@ -31,7 +31,7 @@ entry: ; CHECK-LABEL: @testi32 ; CHECK-DAG: andi. {{[0-9]+}}, 3, 1 ; CHECK-DAG: li [[REG1:[0-9]+]], 0 -; CHECK-DAG: cror [[REG2:[0-9]+]], 1, 1 +; CHECK-DAG: crmove [[REG2:[0-9]+]], 1 ; CHECK-DAG: andi. {{[0-9]+}}, 4, 1 ; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1 ; CHECK-DAG: li [[REG4:[0-9]+]], -1 @@ -47,7 +47,7 @@ entry: ; CHECK-LABEL: @testi8 ; CHECK-DAG: andi. {{[0-9]+}}, 3, 1 ; CHECK-DAG: li [[REG1:[0-9]+]], 0 -; CHECK-DAG: cror [[REG2:[0-9]+]], 1, 1 +; CHECK-DAG: crmove [[REG2:[0-9]+]], 1 ; CHECK-DAG: andi. {{[0-9]+}}, 4, 1 ; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1 ; CHECK-DAG: li [[REG4:[0-9]+]], 1 diff --git a/llvm/test/CodeGen/PowerPC/crbits.ll b/llvm/test/CodeGen/PowerPC/crbits.ll index 8873c1bd28c..ab8655c5c8c 100644 --- a/llvm/test/CodeGen/PowerPC/crbits.ll +++ b/llvm/test/CodeGen/PowerPC/crbits.ll @@ -107,7 +107,7 @@ entry: ; CHECK-LABEL: @test6 ; CHECK-DAG: andi. {{[0-9]+}}, 3, 1 ; CHECK-DAG: cmpwi {{[0-9]+}}, 5, -2 -; CHECK-DAG: cror [[REG1:[0-9]+]], 1, 1 +; CHECK-DAG: crmove [[REG1:[0-9]+]], 1 ; CHECK-DAG: andi. {{[0-9]+}}, 4, 1 ; CHECK-DAG: li [[REG2:[0-9]+]], 1 ; CHECK-DAG: crorc [[REG4:[0-9]+]], 1, diff --git a/llvm/test/CodeGen/PowerPC/cttz.ll b/llvm/test/CodeGen/PowerPC/cttz.ll index 3757fa3e2f2..60de982d91a 100644 --- a/llvm/test/CodeGen/PowerPC/cttz.ll +++ b/llvm/test/CodeGen/PowerPC/cttz.ll @@ -6,7 +6,7 @@ declare i32 @llvm.cttz.i32(i32, i1) define i32 @bar(i32 %x) { entry: ; CHECK: @bar -; CHECK: cntlzw +; CHECK: cntlz %tmp.1 = call i32 @llvm.cttz.i32( i32 %x, i1 true ) ; <i32> [#uses=1] ret i32 %tmp.1 } diff --git a/llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll b/llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll index 24bd11bda40..5a9d15868b6 100644 --- a/llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll +++ b/llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll @@ -201,7 +201,7 @@ define void @t12(i8 %a) uwtable ssp { entry: ; ELF64: t12 %cmp = icmp ugt i8 %a, -113 -; ELF64: rlwinm +; ELF64: clrlwi ; ELF64: cmplwi br i1 %cmp, label %if.then, label %if.end diff --git a/llvm/test/CodeGen/PowerPC/fast-isel-conversion.ll b/llvm/test/CodeGen/PowerPC/fast-isel-conversion.ll index fe4580441eb..f7557d45685 100644 --- a/llvm/test/CodeGen/PowerPC/fast-isel-conversion.ll +++ b/llvm/test/CodeGen/PowerPC/fast-isel-conversion.ll @@ -253,7 +253,7 @@ entry: ; ELF64LE: std ; ELF64LE: lfd ; ELF64LE: fcfidus -; PPC970: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 16, 31 +; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16 ; PPC970: std ; PPC970: lfd ; PPC970: fcfid @@ -277,7 +277,7 @@ entry: ; ELF64LE: std ; ELF64LE: lfd ; ELF64LE: fcfidus -; PPC970: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 24, 31 +; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24 ; PPC970: std ; PPC970: lfd ; PPC970: fcfid @@ -342,7 +342,7 @@ entry: ; ELF64LE: std ; ELF64LE: lfd ; ELF64LE: fcfidu -; PPC970: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 16, 31 +; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16 ; PPC970: std ; PPC970: lfd ; PPC970: fcfid @@ -365,7 +365,7 @@ entry: ; ELF64LE: std ; ELF64LE: lfd ; ELF64LE: fcfidu -; PPC970: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 24, 31 +; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24 ; PPC970: std ; PPC970: lfd ; PPC970: fcfid diff --git a/llvm/test/CodeGen/PowerPC/fast-isel-ext.ll b/llvm/test/CodeGen/PowerPC/fast-isel-ext.ll index 69fa9945ded..6fd3b403512 100644 --- a/llvm/test/CodeGen/PowerPC/fast-isel-ext.ll +++ b/llvm/test/CodeGen/PowerPC/fast-isel-ext.ll @@ -5,14 +5,14 @@ define i32 @zext_8_32(i8 %a) nounwind ssp { ; ELF64: zext_8_32 %r = zext i8 %a to i32 -; ELF64: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 24, 31 +; ELF64: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24 ret i32 %r } define i32 @zext_16_32(i16 %a) nounwind ssp { ; ELF64: zext_16_32 %r = zext i16 %a to i32 -; ELF64: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 16, 31 +; ELF64: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16 ret i32 %r } diff --git a/llvm/test/CodeGen/PowerPC/i64_fp_round.ll b/llvm/test/CodeGen/PowerPC/i64_fp_round.ll index 5770d788caf..2530b8a9282 100644 --- a/llvm/test/CodeGen/PowerPC/i64_fp_round.ll +++ b/llvm/test/CodeGen/PowerPC/i64_fp_round.ll @@ -14,7 +14,7 @@ entry: ; CHECK: sradi [[REG1:[0-9]+]], 3, 53 ; CHECK: addi [[REG2:[0-9]+]], [[REG1]], 1 -; CHECK: cmpldi 0, [[REG2]], 1 +; CHECK: cmpldi [[REG2]], 1 ; CHECK: isel [[REG3:[0-9]+]], {{[0-9]+}}, 3, 1 ; CHECK: std [[REG3]], -{{[0-9]+}}(1) diff --git a/llvm/test/CodeGen/PowerPC/long-compare.ll b/llvm/test/CodeGen/PowerPC/long-compare.ll index 915595f6dba..e53356a5ddf 100644 --- a/llvm/test/CodeGen/PowerPC/long-compare.ll +++ b/llvm/test/CodeGen/PowerPC/long-compare.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ppc32 | grep cntlzw +; RUN: llc < %s -march=ppc32 | grep cntlz ; RUN: llc < %s -march=ppc32 | not grep xori ; RUN: llc < %s -march=ppc32 | not grep "li " ; RUN: llc < %s -march=ppc32 | not grep "mr " diff --git a/llvm/test/CodeGen/PowerPC/ppc32-cyclecounter.ll b/llvm/test/CodeGen/PowerPC/ppc32-cyclecounter.ll index 9e2cd0b1288..ea50a1bdbdc 100644 --- a/llvm/test/CodeGen/PowerPC/ppc32-cyclecounter.ll +++ b/llvm/test/CodeGen/PowerPC/ppc32-cyclecounter.ll @@ -13,8 +13,8 @@ entry: ; CHECK: mfspr 3, 269 ; CHECK: mfspr 4, 268 ; CHECK: mfspr [[REG:[0-9]+]], 269 -; CHECK: cmpw [[CR:[0-9]+]], 3, [[REG]] -; CHECK: bne [[CR]], .LBB +; CHECK: cmpw 3, [[REG]] +; CHECK: bne 0, .LBB declare i64 @llvm.readcyclecounter() diff --git a/llvm/test/CodeGen/PowerPC/ppc64-zext.ll b/llvm/test/CodeGen/PowerPC/ppc64-zext.ll index eb55445cc6c..bbd4856babd 100644 --- a/llvm/test/CodeGen/PowerPC/ppc64-zext.ll +++ b/llvm/test/CodeGen/PowerPC/ppc64-zext.ll @@ -4,7 +4,7 @@ target triple = "powerpc64-unknown-linux" define i64 @fun(i32 %arg32) nounwind { entry: -; CHECK: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 32 +; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 32 %o = zext i32 %arg32 to i64 ret i64 %o } diff --git a/llvm/test/CodeGen/PowerPC/rlwimi-and.ll b/llvm/test/CodeGen/PowerPC/rlwimi-and.ll index b9b0c915a1d..59f704ee16b 100644 --- a/llvm/test/CodeGen/PowerPC/rlwimi-and.ll +++ b/llvm/test/CodeGen/PowerPC/rlwimi-and.ll @@ -29,7 +29,7 @@ codeRepl17: ; preds = %codeRepl4 unreachable ; CHECK: @test -; CHECK: rlwinm [[R1:[0-9]+]], {{[0-9]+}}, 0, 31, 31 +; CHECK: clrlwi [[R1:[0-9]+]], {{[0-9]+}}, 31 ; CHECK: rlwimi [[R1]], {{[0-9]+}}, 8, 23, 23 codeRepl29: ; preds = %codeRepl1 diff --git a/llvm/test/CodeGen/PowerPC/rotl-2.ll b/llvm/test/CodeGen/PowerPC/rotl-2.ll index d32ef59be6c..86539b6c119 100644 --- a/llvm/test/CodeGen/PowerPC/rotl-2.ll +++ b/llvm/test/CodeGen/PowerPC/rotl-2.ll @@ -1,5 +1,6 @@ -; RUN: llc < %s -march=ppc32 | grep rlwinm | count 4 -; RUN: llc < %s -march=ppc32 | grep rlwnm | count 2 +; RUN: llc < %s -march=ppc32 | grep rotlwi | count 2 +; RUN: llc < %s -march=ppc32 | grep clrlwi | count 2 +; RUN: llc < %s -march=ppc32 | grep rotlw | count 4 ; RUN: llc < %s -march=ppc32 | not grep or define i32 @rotl32(i32 %A, i8 %Amt) nounwind { diff --git a/llvm/test/CodeGen/PowerPC/rotl-64.ll b/llvm/test/CodeGen/PowerPC/rotl-64.ll index 674c9e4cc95..2ccdc29f2cd 100644 --- a/llvm/test/CodeGen/PowerPC/rotl-64.ll +++ b/llvm/test/CodeGen/PowerPC/rotl-64.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=ppc64 | grep rldicl -; RUN: llc < %s -march=ppc64 | grep rldcl +; RUN: llc < %s -march=ppc64 | grep rotld +; RUN: llc < %s -march=ppc64 | grep rotldi ; PR1613 define i64 @t1(i64 %A) { diff --git a/llvm/test/CodeGen/PowerPC/rotl.ll b/llvm/test/CodeGen/PowerPC/rotl.ll index 56fc4a8c911..671f524645a 100644 --- a/llvm/test/CodeGen/PowerPC/rotl.ll +++ b/llvm/test/CodeGen/PowerPC/rotl.ll @@ -1,5 +1,7 @@ -; RUN: llc < %s -march=ppc32 | grep rlwnm | count 2 -; RUN: llc < %s -march=ppc32 | grep rlwinm | count 2 +; RUN: llc < %s -march=ppc32 | grep rotrw: | count 1 +; RUN: llc < %s -march=ppc32 | grep rotlw: | count 1 +; RUN: llc < %s -march=ppc32 | grep rotlwi: | count 1 +; RUN: llc < %s -march=ppc32 | grep rotrwi: | count 1 define i32 @rotlw(i32 %x, i32 %sh) { entry: diff --git a/llvm/test/CodeGen/PowerPC/sdag-ppcf128.ll b/llvm/test/CodeGen/PowerPC/sdag-ppcf128.ll index c46bc6b22dd..6d2a04c7293 100644 --- a/llvm/test/CodeGen/PowerPC/sdag-ppcf128.ll +++ b/llvm/test/CodeGen/PowerPC/sdag-ppcf128.ll @@ -5,7 +5,7 @@ define fastcc void @_D3std4math4sqrtFNaNbNfcZc() { entry: br i1 undef, label %if, label %else -; CHECK: cmplwi 0, 3, 0 +; CHECK: cmplwi 3, 0 if: ; preds = %entry store { ppc_fp128, ppc_fp128 } zeroinitializer, { ppc_fp128, ppc_fp128 }* undef ret void diff --git a/llvm/test/CodeGen/PowerPC/seteq-0.ll b/llvm/test/CodeGen/PowerPC/seteq-0.ll index b7dd78085eb..4afb8fee177 100644 --- a/llvm/test/CodeGen/PowerPC/seteq-0.ll +++ b/llvm/test/CodeGen/PowerPC/seteq-0.ll @@ -5,7 +5,7 @@ define i32 @eq0(i32 %a) { %tmp.2 = zext i1 %tmp.1 to i32 ; <i32> [#uses=1] ret i32 %tmp.2 -; CHECK: cntlzw [[REG:r[0-9]+]], r3 +; CHECK: cntlz [[REG:r[0-9]+]], r3 ; CHECK: rlwinm r3, [[REG]], 27, 31, 31 ; CHECK: blr } diff --git a/llvm/test/CodeGen/PowerPC/stack-realign.ll b/llvm/test/CodeGen/PowerPC/stack-realign.ll index 00aee56199b..e91b563af72 100644 --- a/llvm/test/CodeGen/PowerPC/stack-realign.ll +++ b/llvm/test/CodeGen/PowerPC/stack-realign.ll @@ -30,7 +30,7 @@ entry: ; CHECK-LABEL: @goo ; CHECK-DAG: mflr 0 -; CHECK-DAG: rldicl [[REG:[0-9]+]], 1, 0, 59 +; CHECK-DAG: clrldi [[REG:[0-9]+]], 1, 59 ; CHECK-DAG: std 30, -16(1) ; CHECK-DAG: mr 30, 1 ; CHECK-DAG: std 0, 16(1) @@ -52,7 +52,7 @@ entry: ; CHECK-FP-LABEL: @goo ; CHECK-FP-DAG: mflr 0 -; CHECK-FP-DAG: rldicl [[REG:[0-9]+]], 1, 0, 59 +; CHECK-FP-DAG: clrldi [[REG:[0-9]+]], 1, 59 ; CHECK-FP-DAG: std 31, -8(1) ; CHECK-FP-DAG: std 30, -16(1) ; CHECK-FP-DAG: mr 30, 1 @@ -78,7 +78,7 @@ entry: ; CHECK-32-LABEL: @goo ; CHECK-32-DAG: mflr 0 -; CHECK-32-DAG: rlwinm [[REG:[0-9]+]], 1, 0, 27, 31 +; CHECK-32-DAG: clrlwi [[REG:[0-9]+]], 1, 27 ; CHECK-32-DAG: stw 30, -8(1) ; CHECK-32-DAG: mr 30, 1 ; CHECK-32-DAG: stw 0, 4(1) @@ -87,7 +87,7 @@ entry: ; CHECK-32-PIC-LABEL: @goo ; CHECK-32-PIC-DAG: mflr 0 -; CHECK-32-PIC-DAG: rlwinm [[REG:[0-9]+]], 1, 0, 27, 31 +; CHECK-32-PIC-DAG: clrlwi [[REG:[0-9]+]], 1, 27 ; CHECK-32-PIC-DAG: stw 29, -12(1) ; CHECK-32-PIC-DAG: mr 29, 1 ; CHECK-32-PIC-DAG: stw 0, 4(1) @@ -113,7 +113,7 @@ entry: ; CHECK-LABEL: @hoo ; CHECK-DAG: lis [[REG1:[0-9]+]], -13 -; CHECK-DAG: rldicl [[REG3:[0-9]+]], 1, 0, 59 +; CHECK-DAG: clrldi [[REG3:[0-9]+]], 1, 59 ; CHECK-DAG: mflr 0 ; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51808 ; CHECK-DAG: std 30, -16(1) @@ -129,7 +129,7 @@ entry: ; CHECK-32-LABEL: @hoo ; CHECK-32-DAG: lis [[REG1:[0-9]+]], -13 -; CHECK-32-DAG: rlwinm [[REG3:[0-9]+]], 1, 0, 27, 31 +; CHECK-32-DAG: clrlwi [[REG3:[0-9]+]], 1, 27 ; CHECK-32-DAG: mflr 0 ; CHECK-32-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51904 ; CHECK-32-DAG: stw 30, -8(1) @@ -143,7 +143,7 @@ entry: ; CHECK-32-PIC-LABEL: @hoo ; CHECK-32-PIC-DAG: lis [[REG1:[0-9]+]], -13 -; CHECK-32-PIC-DAG: rlwinm [[REG3:[0-9]+]], 1, 0, 27, 31 +; CHECK-32-PIC-DAG: clrlwi [[REG3:[0-9]+]], 1, 27 ; CHECK-32-PIC-DAG: mflr 0 ; CHECK-32-PIC-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51904 ; CHECK-32-PIC-DAG: stw 29, -12(1) @@ -175,7 +175,7 @@ entry: ; CHECK-LABEL: @loo ; CHECK-DAG: mflr 0 -; CHECK-DAG: rldicl [[REG:[0-9]+]], 1, 0, 59 +; CHECK-DAG: clrldi [[REG:[0-9]+]], 1, 59 ; CHECK-DAG: std 30, -32(1) ; CHECK-DAG: mr 30, 1 ; CHECK-DAG: std 0, 16(1) @@ -191,7 +191,7 @@ entry: ; CHECK-FP-LABEL: @loo ; CHECK-FP-DAG: mflr 0 -; CHECK-FP-DAG: rldicl [[REG:[0-9]+]], 1, 0, 59 +; CHECK-FP-DAG: clrldi [[REG:[0-9]+]], 1, 59 ; CHECK-FP-DAG: std 31, -24(1) ; CHECK-FP-DAG: std 30, -32(1) ; CHECK-FP-DAG: mr 30, 1 diff --git a/llvm/test/CodeGen/PowerPC/subreg-postra-2.ll b/llvm/test/CodeGen/PowerPC/subreg-postra-2.ll index 893e4b9e8ae..05153644341 100644 --- a/llvm/test/CodeGen/PowerPC/subreg-postra-2.ll +++ b/llvm/test/CodeGen/PowerPC/subreg-postra-2.ll @@ -160,7 +160,7 @@ while.end418: ; preds = %wait_on_buffer.exit ; CHECK-LABEL: @jbd2_journal_commit_transaction ; CHECK: andi. -; CHECK: cror [[REG:[0-9]+]], 1, 1 +; CHECK: crmove [[REG:[0-9]+]], 1 ; CHECK: stdcx. ; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, [[REG]] diff --git a/llvm/test/CodeGen/PowerPC/subreg-postra.ll b/llvm/test/CodeGen/PowerPC/subreg-postra.ll index fa5fd7e1c76..ba1b967cf20 100644 --- a/llvm/test/CodeGen/PowerPC/subreg-postra.ll +++ b/llvm/test/CodeGen/PowerPC/subreg-postra.ll @@ -143,7 +143,7 @@ wait_on_buffer.exit1319: ; preds = %while.body392 ; CHECK-LABEL: @jbd2_journal_commit_transaction ; CHECK: andi. -; CHECK: cror [[REG:[0-9]+]], 1, 1 +; CHECK: crmove [[REG:[0-9]+]], 1 ; CHECK: stdcx. ; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, [[REG]] diff --git a/llvm/test/CodeGen/PowerPC/vsx-ldst-builtin-le.ll b/llvm/test/CodeGen/PowerPC/vsx-ldst-builtin-le.ll index e6ddf647616..b0648003094 100644 --- a/llvm/test/CodeGen/PowerPC/vsx-ldst-builtin-le.ll +++ b/llvm/test/CodeGen/PowerPC/vsx-ldst-builtin-le.ll @@ -1,7 +1,7 @@ ; RUN: llc -mcpu=pwr8 -mattr=+vsx -O2 -mtriple=powerpc64le-unknown-linux-gnu < %s > %t ; RUN: grep lxvd2x < %t | count 18 ; RUN: grep stxvd2x < %t | count 18 -; RUN: grep xxpermdi < %t | count 36 +; RUN: grep xxswapd < %t | count 36 @vf = global <4 x float> <float -1.500000e+00, float 2.500000e+00, float -3.500000e+00, float 4.500000e+00>, align 16 @vd = global <2 x double> <double 3.500000e+00, double -7.500000e+00>, align 16 diff --git a/llvm/test/CodeGen/PowerPC/vsx-ldst.ll b/llvm/test/CodeGen/PowerPC/vsx-ldst.ll index 4ed91bca420..d198f0b8636 100644 --- a/llvm/test/CodeGen/PowerPC/vsx-ldst.ll +++ b/llvm/test/CodeGen/PowerPC/vsx-ldst.ll @@ -12,7 +12,7 @@ ; RUN: llc -mcpu=pwr8 -mattr=+vsx -O2 -mtriple=powerpc64le-unknown-linux-gnu < %s > %t ; RUN: grep lxvd2x < %t | count 6 ; RUN: grep stxvd2x < %t | count 6 -; RUN: grep xxpermdi < %t | count 12 +; RUN: grep xxswapd < %t | count 12 @vsi = global <4 x i32> <i32 -1, i32 2, i32 -3, i32 4>, align 16 @vui = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 diff --git a/llvm/test/CodeGen/PowerPC/vsx.ll b/llvm/test/CodeGen/PowerPC/vsx.ll index 25cf3d4750a..b185fed4cd5 100644 --- a/llvm/test/CodeGen/PowerPC/vsx.ll +++ b/llvm/test/CodeGen/PowerPC/vsx.ll @@ -733,7 +733,7 @@ define <2 x double> @test51(<2 x double> %a, <2 x double> %b) { ret <2 x double> %v ; CHECK-LABEL: @test51 -; CHECK: xxpermdi 34, 34, 34, 0 +; CHECK: xxspltd 34, 34, 0 ; CHECK: blr } @@ -742,7 +742,7 @@ define <2 x double> @test52(<2 x double> %a, <2 x double> %b) { ret <2 x double> %v ; CHECK-LABEL: @test52 -; CHECK: xxpermdi 34, 34, 35, 0 +; CHECK: xxmrghd 34, 34, 35 ; CHECK: blr } @@ -751,7 +751,7 @@ define <2 x double> @test53(<2 x double> %a, <2 x double> %b) { ret <2 x double> %v ; CHECK-LABEL: @test53 -; CHECK: xxpermdi 34, 35, 34, 0 +; CHECK: xxmrghd 34, 35, 34 ; CHECK: blr } @@ -769,7 +769,7 @@ define <2 x double> @test55(<2 x double> %a, <2 x double> %b) { ret <2 x double> %v ; CHECK-LABEL: @test55 -; CHECK: xxpermdi 34, 34, 35, 3 +; CHECK: xxmrgld 34, 34, 35 ; CHECK: blr } @@ -778,7 +778,7 @@ define <2 x i64> @test56(<2 x i64> %a, <2 x i64> %b) { ret <2 x i64> %v ; CHECK-LABEL: @test56 -; CHECK: xxpermdi 34, 34, 35, 3 +; CHECK: xxmrgld 34, 34, 35 ; CHECK: blr } @@ -843,11 +843,11 @@ define double @test64(<2 x double> %a) { ret double %v ; CHECK-REG-LABEL: @test64 -; CHECK-REG: xxpermdi 1, 34, 34, 2 +; CHECK-REG: xxswapd 1, 34 ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test64 -; CHECK-FISL: xxpermdi 34, 34, 34, 2 +; CHECK-FISL: xxswapd 34, 34 ; CHECK-FISL: xxlor 0, 34, 34 ; CHECK-FISL: fmr 1, 0 ; CHECK-FISL: blr diff --git a/llvm/test/CodeGen/PowerPC/vsx_insert_extract_le.ll b/llvm/test/CodeGen/PowerPC/vsx_insert_extract_le.ll index e00cc4bf9fc..84bbdd75b0f 100644 --- a/llvm/test/CodeGen/PowerPC/vsx_insert_extract_le.ll +++ b/llvm/test/CodeGen/PowerPC/vsx_insert_extract_le.ll @@ -9,8 +9,8 @@ define <2 x double> @testi0(<2 x double>* %p1, double* %p2) { ; CHECK-LABEL: testi0 ; CHECK: lxvd2x 0, 0, 3 ; CHECK: lxsdx 34, 0, 4 -; CHECK: xxpermdi 0, 0, 0, 2 -; CHECK: xxpermdi 1, 34, 34, 0 +; CHECK: xxswapd 0, 0 +; CHECK: xxspltd 1, 34, 0 ; CHECK: xxpermdi 34, 0, 1, 1 } @@ -23,9 +23,9 @@ define <2 x double> @testi1(<2 x double>* %p1, double* %p2) { ; CHECK-LABEL: testi1 ; CHECK: lxvd2x 0, 0, 3 ; CHECK: lxsdx 34, 0, 4 -; CHECK: xxpermdi 0, 0, 0, 2 -; CHECK: xxpermdi 1, 34, 34, 0 -; CHECK: xxpermdi 34, 1, 0, 3 +; CHECK: xxswapd 0, 0 +; CHECK: xxspltd 1, 34, 0 +; CHECK: xxmrgld 34, 1, 0 } define double @teste0(<2 x double>* %p1) { @@ -37,8 +37,8 @@ define double @teste0(<2 x double>* %p1) { ; CHECK-LABEL: teste0 ; CHECK: lxvd2x 0, 0, 3 -; CHECK: xxpermdi 0, 0, 0, 2 -; CHECK: xxpermdi 1, 0, 0, 2 +; CHECK: xxswapd 0, 0 +; CHECK: xxswapd 1, 0 } define double @teste1(<2 x double>* %p1) { @@ -48,5 +48,5 @@ define double @teste1(<2 x double>* %p1) { ; CHECK-LABEL: teste1 ; CHECK: lxvd2x 0, 0, 3 -; CHECK: xxpermdi 1, 0, 0, 2 +; CHECK: xxswapd 1, 0 } diff --git a/llvm/test/CodeGen/PowerPC/vsx_shuffle_le.ll b/llvm/test/CodeGen/PowerPC/vsx_shuffle_le.ll index 6bfde935f1d..dcfa0e78886 100644 --- a/llvm/test/CodeGen/PowerPC/vsx_shuffle_le.ll +++ b/llvm/test/CodeGen/PowerPC/vsx_shuffle_le.ll @@ -8,8 +8,8 @@ define <2 x double> @test00(<2 x double>* %p1, <2 x double>* %p2) { ; CHECK-LABEL: test00 ; CHECK: lxvd2x 0, 0, 3 -; CHECK: xxpermdi 0, 0, 0, 2 -; CHECK: xxpermdi 34, 0, 0, 3 +; CHECK: xxswapd 0, 0 +; CHECK: xxspltd 34, 0, 1 } define <2 x double> @test01(<2 x double>* %p1, <2 x double>* %p2) { @@ -20,7 +20,7 @@ define <2 x double> @test01(<2 x double>* %p1, <2 x double>* %p2) { ; CHECK-LABEL: test01 ; CHECK: lxvd2x 0, 0, 3 -; CHECK: xxpermdi 34, 0, 0, 2 +; CHECK: xxswapd 34, 0 } define <2 x double> @test02(<2 x double>* %p1, <2 x double>* %p2) { @@ -32,9 +32,9 @@ define <2 x double> @test02(<2 x double>* %p1, <2 x double>* %p2) { ; CHECK-LABEL: @test02 ; CHECK: lxvd2x 0, 0, 3 ; CHECK: lxvd2x 1, 0, 4 -; CHECK: xxpermdi 0, 0, 0, 2 -; CHECK: xxpermdi 1, 1, 1, 2 -; CHECK: xxpermdi 34, 1, 0, 3 +; CHECK: xxswapd 0, 0 +; CHECK: xxswapd 1, 1 +; CHECK: xxmrgld 34, 1, 0 } define <2 x double> @test03(<2 x double>* %p1, <2 x double>* %p2) { @@ -46,8 +46,8 @@ define <2 x double> @test03(<2 x double>* %p1, <2 x double>* %p2) { ; CHECK-LABEL: @test03 ; CHECK: lxvd2x 0, 0, 3 ; CHECK: lxvd2x 1, 0, 4 -; CHECK: xxpermdi 0, 0, 0, 2 -; CHECK: xxpermdi 1, 1, 1, 2 +; CHECK: xxswapd 0, 0 +; CHECK: xxswapd 1, 1 ; CHECK: xxpermdi 34, 1, 0, 1 } @@ -59,8 +59,8 @@ define <2 x double> @test10(<2 x double>* %p1, <2 x double>* %p2) { ; CHECK-LABEL: @test10 ; CHECK: lxvd2x 0, 0, 3 -; CHECK: xxpermdi 0, 0, 0, 2 -; CHECK: xxpermdi 34, 0, 0, 2 +; CHECK: xxswapd 0, 0 +; CHECK: xxswapd 34, 0 } define <2 x double> @test11(<2 x double>* %p1, <2 x double>* %p2) { @@ -71,8 +71,8 @@ define <2 x double> @test11(<2 x double>* %p1, <2 x double>* %p2) { ; CHECK-LABEL: @test11 ; CHECK: lxvd2x 0, 0, 3 -; CHECK: xxpermdi 0, 0, 0, 2 -; CHECK: xxpermdi 34, 0, 0, 0 +; CHECK: xxswapd 0, 0 +; CHECK: xxspltd 34, 0, 0 } define <2 x double> @test12(<2 x double>* %p1, <2 x double>* %p2) { @@ -84,8 +84,8 @@ define <2 x double> @test12(<2 x double>* %p1, <2 x double>* %p2) { ; CHECK-LABEL: @test12 ; CHECK: lxvd2x 0, 0, 3 ; CHECK: lxvd2x 1, 0, 4 -; CHECK: xxpermdi 0, 0, 0, 2 -; CHECK: xxpermdi 1, 1, 1, 2 +; CHECK: xxswapd 0, 0 +; CHECK: xxswapd 1, 1 ; CHECK: xxpermdi 34, 1, 0, 2 } @@ -98,9 +98,9 @@ define <2 x double> @test13(<2 x double>* %p1, <2 x double>* %p2) { ; CHECK-LABEL: @test13 ; CHECK: lxvd2x 0, 0, 3 ; CHECK: lxvd2x 1, 0, 4 -; CHECK: xxpermdi 0, 0, 0, 2 -; CHECK: xxpermdi 1, 1, 1, 2 -; CHECK: xxpermdi 34, 1, 0, 0 +; CHECK: xxswapd 0, 0 +; CHECK: xxswapd 1, 1 +; CHECK: xxmrghd 34, 1, 0 } define <2 x double> @test20(<2 x double>* %p1, <2 x double>* %p2) { @@ -112,9 +112,9 @@ define <2 x double> @test20(<2 x double>* %p1, <2 x double>* %p2) { ; CHECK-LABEL: @test20 ; CHECK: lxvd2x 0, 0, 3 ; CHECK: lxvd2x 1, 0, 4 -; CHECK: xxpermdi 0, 0, 0, 2 -; CHECK: xxpermdi 1, 1, 1, 2 -; CHECK: xxpermdi 34, 0, 1, 3 +; CHECK: xxswapd 0, 0 +; CHECK: xxswapd 1, 1 +; CHECK: xxmrgld 34, 0, 1 } define <2 x double> @test21(<2 x double>* %p1, <2 x double>* %p2) { @@ -126,8 +126,8 @@ define <2 x double> @test21(<2 x double>* %p1, <2 x double>* %p2) { ; CHECK-LABEL: @test21 ; CHECK: lxvd2x 0, 0, 3 ; CHECK: lxvd2x 1, 0, 4 -; CHECK: xxpermdi 0, 0, 0, 2 -; CHECK: xxpermdi 1, 1, 1, 2 +; CHECK: xxswapd 0, 0 +; CHECK: xxswapd 1, 1 ; CHECK: xxpermdi 34, 0, 1, 1 } @@ -139,8 +139,8 @@ define <2 x double> @test22(<2 x double>* %p1, <2 x double>* %p2) { ; CHECK-LABEL: @test22 ; CHECK: lxvd2x 0, 0, 4 -; CHECK: xxpermdi 0, 0, 0, 2 -; CHECK: xxpermdi 34, 0, 0, 3 +; CHECK: xxswapd 0, 0 +; CHECK: xxspltd 34, 0, 1 } define <2 x double> @test23(<2 x double>* %p1, <2 x double>* %p2) { @@ -151,7 +151,7 @@ define <2 x double> @test23(<2 x double>* %p1, <2 x double>* %p2) { ; CHECK-LABEL: @test23 ; CHECK: lxvd2x 0, 0, 4 -; CHECK: xxpermdi 34, 0, 0, 2 +; CHECK: xxswapd 34, 0 } define <2 x double> @test30(<2 x double>* %p1, <2 x double>* %p2) { @@ -163,8 +163,8 @@ define <2 x double> @test30(<2 x double>* %p1, <2 x double>* %p2) { ; CHECK-LABEL: @test30 ; CHECK: lxvd2x 0, 0, 3 ; CHECK: lxvd2x 1, 0, 4 -; CHECK: xxpermdi 0, 0, 0, 2 -; CHECK: xxpermdi 1, 1, 1, 2 +; CHECK: xxswapd 0, 0 +; CHECK: xxswapd 1, 1 ; CHECK: xxpermdi 34, 0, 1, 2 } @@ -177,9 +177,9 @@ define <2 x double> @test31(<2 x double>* %p1, <2 x double>* %p2) { ; CHECK-LABEL: @test31 ; CHECK: lxvd2x 0, 0, 3 ; CHECK: lxvd2x 1, 0, 4 -; CHECK: xxpermdi 0, 0, 0, 2 -; CHECK: xxpermdi 1, 1, 1, 2 -; CHECK: xxpermdi 34, 0, 1, 0 +; CHECK: xxswapd 0, 0 +; CHECK: xxswapd 1, 1 +; CHECK: xxmrghd 34, 0, 1 } define <2 x double> @test32(<2 x double>* %p1, <2 x double>* %p2) { @@ -190,8 +190,8 @@ define <2 x double> @test32(<2 x double>* %p1, <2 x double>* %p2) { ; CHECK-LABEL: @test32 ; CHECK: lxvd2x 0, 0, 4 -; CHECK: xxpermdi 0, 0, 0, 2 -; CHECK: xxpermdi 34, 0, 0, 2 +; CHECK: xxswapd 0, 0 +; CHECK: xxswapd 34, 0 } define <2 x double> @test33(<2 x double>* %p1, <2 x double>* %p2) { @@ -202,6 +202,6 @@ define <2 x double> @test33(<2 x double>* %p1, <2 x double>* %p2) { ; CHECK-LABEL: @test33 ; CHECK: lxvd2x 0, 0, 4 -; CHECK: xxpermdi 0, 0, 0, 2 -; CHECK: xxpermdi 34, 0, 0, 0 +; CHECK: xxswapd 0, 0 +; CHECK: xxspltd 34, 0, 0 } |
