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-rw-r--r--llvm/test/CodeGen/AArch64/arm64-named-reg-alloc.ll2
-rw-r--r--llvm/test/CodeGen/AArch64/arm64-named-reg-notareg.ll2
-rw-r--r--llvm/test/CodeGen/AArch64/special-reg.ll48
-rw-r--r--llvm/test/CodeGen/ARM/named-reg-alloc.ll2
-rw-r--r--llvm/test/CodeGen/ARM/named-reg-notareg.ll2
-rw-r--r--llvm/test/CodeGen/ARM/special-reg-acore.ll78
-rw-r--r--llvm/test/CodeGen/ARM/special-reg-mcore.ll143
-rw-r--r--llvm/test/CodeGen/ARM/special-reg.ll78
8 files changed, 4 insertions, 351 deletions
diff --git a/llvm/test/CodeGen/AArch64/arm64-named-reg-alloc.ll b/llvm/test/CodeGen/AArch64/arm64-named-reg-alloc.ll
index 5d48c17e128..0c564544a53 100644
--- a/llvm/test/CodeGen/AArch64/arm64-named-reg-alloc.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-named-reg-alloc.ll
@@ -4,7 +4,7 @@
define i32 @get_stack() nounwind {
entry:
; FIXME: Include an allocatable-specific error message
-; CHECK: Invalid register name "x5".
+; CHECK: Invalid register name global variable
%sp = call i32 @llvm.read_register.i32(metadata !0)
ret i32 %sp
}
diff --git a/llvm/test/CodeGen/AArch64/arm64-named-reg-notareg.ll b/llvm/test/CodeGen/AArch64/arm64-named-reg-notareg.ll
index 8a5fd6f1ac8..759bc15807b 100644
--- a/llvm/test/CodeGen/AArch64/arm64-named-reg-notareg.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-named-reg-notareg.ll
@@ -3,7 +3,7 @@
define i32 @get_stack() nounwind {
entry:
-; CHECK: Invalid register name "notareg".
+; CHECK: Invalid register name global variable
%sp = call i32 @llvm.read_register.i32(metadata !0)
ret i32 %sp
}
diff --git a/llvm/test/CodeGen/AArch64/special-reg.ll b/llvm/test/CodeGen/AArch64/special-reg.ll
deleted file mode 100644
index 91c32158d42..00000000000
--- a/llvm/test/CodeGen/AArch64/special-reg.ll
+++ /dev/null
@@ -1,48 +0,0 @@
-; RUN: llc < %s -mtriple=aarch64-none-eabi -mcpu=cortex-a57 2>&1 | FileCheck %s
-
-define i64 @read_encoded_register() nounwind {
-entry:
-; CHECK-LABEL: read_encoded_register:
-; CHECK: mrs x0, S1_2_C3_C4_5
- %reg = call i64 @llvm.read_register.i64(metadata !0)
- ret i64 %reg
-}
-
-define i64 @read_daif() nounwind {
-entry:
-; CHECK-LABEL: read_daif:
-; CHECK: mrs x0, DAIF
- %reg = call i64 @llvm.read_register.i64(metadata !1)
- ret i64 %reg
-}
-
-define void @write_encoded_register(i64 %x) nounwind {
-entry:
-; CHECK-LABEL: write_encoded_register:
-; CHECK: msr S1_2_C3_C4_5, x0
- call void @llvm.write_register.i64(metadata !0, i64 %x)
- ret void
-}
-
-define void @write_daif(i64 %x) nounwind {
-entry:
-; CHECK-LABEL: write_daif:
-; CHECK: msr DAIF, x0
- call void @llvm.write_register.i64(metadata !1, i64 %x)
- ret void
-}
-
-define void @write_daifset() nounwind {
-entry:
-; CHECK-LABEL: write_daifset:
-; CHECK: msr DAIFSET, #2
- call void @llvm.write_register.i64(metadata !2, i64 2)
- ret void
-}
-
-declare i64 @llvm.read_register.i64(metadata) nounwind
-declare void @llvm.write_register.i64(metadata, i64) nounwind
-
-!0 = !{!"1:2:3:4:5"}
-!1 = !{!"daif"}
-!2 = !{!"daifset"}
diff --git a/llvm/test/CodeGen/ARM/named-reg-alloc.ll b/llvm/test/CodeGen/ARM/named-reg-alloc.ll
index d41fa64882c..380cf39734f 100644
--- a/llvm/test/CodeGen/ARM/named-reg-alloc.ll
+++ b/llvm/test/CodeGen/ARM/named-reg-alloc.ll
@@ -4,7 +4,7 @@
define i32 @get_stack() nounwind {
entry:
; FIXME: Include an allocatable-specific error message
-; CHECK: Invalid register name "r5".
+; CHECK: Invalid register name global variable
%sp = call i32 @llvm.read_register.i32(metadata !0)
ret i32 %sp
}
diff --git a/llvm/test/CodeGen/ARM/named-reg-notareg.ll b/llvm/test/CodeGen/ARM/named-reg-notareg.ll
index 45cb38f30f3..3ac03f4fdaa 100644
--- a/llvm/test/CodeGen/ARM/named-reg-notareg.ll
+++ b/llvm/test/CodeGen/ARM/named-reg-notareg.ll
@@ -3,7 +3,7 @@
define i32 @get_stack() nounwind {
entry:
-; CHECK: Invalid register name "notareg".
+; CHECK: Invalid register name global variable
%sp = call i32 @llvm.read_register.i32(metadata !0)
ret i32 %sp
}
diff --git a/llvm/test/CodeGen/ARM/special-reg-acore.ll b/llvm/test/CodeGen/ARM/special-reg-acore.ll
deleted file mode 100644
index f63d5ddecfc..00000000000
--- a/llvm/test/CodeGen/ARM/special-reg-acore.ll
+++ /dev/null
@@ -1,78 +0,0 @@
-; RUN: llc < %s -mtriple=arm-none-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s --check-prefix=ACORE
-; RUN: not llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4 2>&1 | FileCheck %s --check-prefix=MCORE
-
-; MCORE: LLVM ERROR: Invalid register name "cpsr".
-
-define i32 @read_cpsr() nounwind {
- ; ACORE-LABEL: read_cpsr:
- ; ACORE: mrs r0, apsr
- %reg = call i32 @llvm.read_register.i32(metadata !1)
- ret i32 %reg
-}
-
-define i32 @read_aclass_registers() nounwind {
-entry:
- ; ACORE-LABEL: read_aclass_registers:
- ; ACORE: mrs r0, apsr
- ; ACORE: mrs r1, spsr
-
- %0 = call i32 @llvm.read_register.i32(metadata !0)
- %1 = call i32 @llvm.read_register.i32(metadata !1)
- %add1 = add i32 %1, %0
- %2 = call i32 @llvm.read_register.i32(metadata !2)
- %add2 = add i32 %add1, %2
- ret i32 %add2
-}
-
-define void @write_aclass_registers(i32 %x) nounwind {
-entry:
- ; ACORE-LABEL: write_aclass_registers:
- ; ACORE: msr APSR_nzcvq, r0
- ; ACORE: msr APSR_g, r0
- ; ACORE: msr APSR_nzcvqg, r0
- ; ACORE: msr CPSR_c, r0
- ; ACORE: msr CPSR_x, r0
- ; ACORE: msr APSR_g, r0
- ; ACORE: msr APSR_nzcvq, r0
- ; ACORE: msr CPSR_fsxc, r0
- ; ACORE: msr SPSR_c, r0
- ; ACORE: msr SPSR_x, r0
- ; ACORE: msr SPSR_s, r0
- ; ACORE: msr SPSR_f, r0
- ; ACORE: msr SPSR_fsxc, r0
-
- call void @llvm.write_register.i32(metadata !3, i32 %x)
- call void @llvm.write_register.i32(metadata !4, i32 %x)
- call void @llvm.write_register.i32(metadata !5, i32 %x)
- call void @llvm.write_register.i32(metadata !6, i32 %x)
- call void @llvm.write_register.i32(metadata !7, i32 %x)
- call void @llvm.write_register.i32(metadata !8, i32 %x)
- call void @llvm.write_register.i32(metadata !9, i32 %x)
- call void @llvm.write_register.i32(metadata !10, i32 %x)
- call void @llvm.write_register.i32(metadata !11, i32 %x)
- call void @llvm.write_register.i32(metadata !12, i32 %x)
- call void @llvm.write_register.i32(metadata !13, i32 %x)
- call void @llvm.write_register.i32(metadata !14, i32 %x)
- call void @llvm.write_register.i32(metadata !15, i32 %x)
- ret void
-}
-
-declare i32 @llvm.read_register.i32(metadata) nounwind
-declare void @llvm.write_register.i32(metadata, i32) nounwind
-
-!0 = !{!"apsr"}
-!1 = !{!"cpsr"}
-!2 = !{!"spsr"}
-!3 = !{!"apsr_nzcvq"}
-!4 = !{!"apsr_g"}
-!5 = !{!"apsr_nzcvqg"}
-!6 = !{!"cpsr_c"}
-!7 = !{!"cpsr_x"}
-!8 = !{!"cpsr_s"}
-!9 = !{!"cpsr_f"}
-!10 = !{!"cpsr_cxsf"}
-!11 = !{!"spsr_c"}
-!12 = !{!"spsr_x"}
-!13 = !{!"spsr_s"}
-!14 = !{!"spsr_f"}
-!15 = !{!"spsr_cxsf"}
diff --git a/llvm/test/CodeGen/ARM/special-reg-mcore.ll b/llvm/test/CodeGen/ARM/special-reg-mcore.ll
deleted file mode 100644
index 686da0f6b83..00000000000
--- a/llvm/test/CodeGen/ARM/special-reg-mcore.ll
+++ /dev/null
@@ -1,143 +0,0 @@
-; RUN: llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4 2>&1 | FileCheck %s --check-prefix=MCORE
-; RUN: not llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m3 2>&1 | FileCheck %s --check-prefix=M3CORE
-; RUN: not llc < %s -mtriple=arm-none-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s --check-prefix=ACORE
-
-; ACORE: LLVM ERROR: Invalid register name "control".
-; M3CORE: LLVM ERROR: Invalid register name "control".
-
-define i32 @read_mclass_registers() nounwind {
-entry:
- ; MCORE-LABEL: read_mclass_registers:
- ; MCORE: mrs r0, apsr
- ; MCORE: mrs r1, iapsr
- ; MCORE: mrs r1, eapsr
- ; MCORE: mrs r1, xpsr
- ; MCORE: mrs r1, ipsr
- ; MCORE: mrs r1, epsr
- ; MCORE: mrs r1, iepsr
- ; MCORE: mrs r1, msp
- ; MCORE: mrs r1, psp
- ; MCORE: mrs r1, primask
- ; MCORE: mrs r1, basepri
- ; MCORE: mrs r1, basepri_max
- ; MCORE: mrs r1, faultmask
- ; MCORE: mrs r1, control
-
- %0 = call i32 @llvm.read_register.i32(metadata !0)
- %1 = call i32 @llvm.read_register.i32(metadata !4)
- %add1 = add i32 %1, %0
- %2 = call i32 @llvm.read_register.i32(metadata !8)
- %add2 = add i32 %add1, %2
- %3 = call i32 @llvm.read_register.i32(metadata !12)
- %add3 = add i32 %add2, %3
- %4 = call i32 @llvm.read_register.i32(metadata !16)
- %add4 = add i32 %add3, %4
- %5 = call i32 @llvm.read_register.i32(metadata !17)
- %add5 = add i32 %add4, %5
- %6 = call i32 @llvm.read_register.i32(metadata !18)
- %add6 = add i32 %add5, %6
- %7 = call i32 @llvm.read_register.i32(metadata !19)
- %add7 = add i32 %add6, %7
- %8 = call i32 @llvm.read_register.i32(metadata !20)
- %add8 = add i32 %add7, %8
- %9 = call i32 @llvm.read_register.i32(metadata !21)
- %add9 = add i32 %add8, %9
- %10 = call i32 @llvm.read_register.i32(metadata !22)
- %add10 = add i32 %add9, %10
- %11 = call i32 @llvm.read_register.i32(metadata !23)
- %add11 = add i32 %add10, %11
- %12 = call i32 @llvm.read_register.i32(metadata !24)
- %add12 = add i32 %add11, %12
- %13 = call i32 @llvm.read_register.i32(metadata !25)
- %add13 = add i32 %add12, %13
- ret i32 %add13
-}
-
-define void @write_mclass_registers(i32 %x) nounwind {
-entry:
- ; MCORE-LABEL: write_mclass_registers:
- ; MCORE: msr apsr_nzcvqg, r0
- ; MCORE: msr apsr_nzcvq, r0
- ; MCORE: msr apsr_g, r0
- ; MCORE: msr apsr_nzcvqg, r0
- ; MCORE: msr iapsr_nzcvqg, r0
- ; MCORE: msr iapsr_nzcvq, r0
- ; MCORE: msr iapsr_g, r0
- ; MCORE: msr iapsr_nzcvqg, r0
- ; MCORE: msr eapsr_nzcvqg, r0
- ; MCORE: msr eapsr_nzcvq, r0
- ; MCORE: msr eapsr_g, r0
- ; MCORE: msr eapsr_nzcvqg, r0
- ; MCORE: msr xpsr_nzcvqg, r0
- ; MCORE: msr xpsr_nzcvq, r0
- ; MCORE: msr xpsr_g, r0
- ; MCORE: msr xpsr_nzcvqg, r0
- ; MCORE: msr ipsr, r0
- ; MCORE: msr epsr, r0
- ; MCORE: msr iepsr, r0
- ; MCORE: msr msp, r0
- ; MCORE: msr psp, r0
- ; MCORE: msr primask, r0
- ; MCORE: msr basepri, r0
- ; MCORE: msr basepri_max, r0
- ; MCORE: msr faultmask, r0
- ; MCORE: msr control, r0
-
- call void @llvm.write_register.i32(metadata !0, i32 %x)
- call void @llvm.write_register.i32(metadata !1, i32 %x)
- call void @llvm.write_register.i32(metadata !2, i32 %x)
- call void @llvm.write_register.i32(metadata !3, i32 %x)
- call void @llvm.write_register.i32(metadata !4, i32 %x)
- call void @llvm.write_register.i32(metadata !5, i32 %x)
- call void @llvm.write_register.i32(metadata !6, i32 %x)
- call void @llvm.write_register.i32(metadata !7, i32 %x)
- call void @llvm.write_register.i32(metadata !8, i32 %x)
- call void @llvm.write_register.i32(metadata !9, i32 %x)
- call void @llvm.write_register.i32(metadata !10, i32 %x)
- call void @llvm.write_register.i32(metadata !11, i32 %x)
- call void @llvm.write_register.i32(metadata !12, i32 %x)
- call void @llvm.write_register.i32(metadata !13, i32 %x)
- call void @llvm.write_register.i32(metadata !14, i32 %x)
- call void @llvm.write_register.i32(metadata !15, i32 %x)
- call void @llvm.write_register.i32(metadata !16, i32 %x)
- call void @llvm.write_register.i32(metadata !17, i32 %x)
- call void @llvm.write_register.i32(metadata !18, i32 %x)
- call void @llvm.write_register.i32(metadata !19, i32 %x)
- call void @llvm.write_register.i32(metadata !20, i32 %x)
- call void @llvm.write_register.i32(metadata !21, i32 %x)
- call void @llvm.write_register.i32(metadata !22, i32 %x)
- call void @llvm.write_register.i32(metadata !23, i32 %x)
- call void @llvm.write_register.i32(metadata !24, i32 %x)
- call void @llvm.write_register.i32(metadata !25, i32 %x)
- ret void
-}
-
-declare i32 @llvm.read_register.i32(metadata) nounwind
-declare void @llvm.write_register.i32(metadata, i32) nounwind
-
-!0 = !{!"apsr"}
-!1 = !{!"apsr_nzcvq"}
-!2 = !{!"apsr_g"}
-!3 = !{!"apsr_nzcvqg"}
-!4 = !{!"iapsr"}
-!5 = !{!"iapsr_nzcvq"}
-!6 = !{!"iapsr_g"}
-!7 = !{!"iapsr_nzcvqg"}
-!8 = !{!"eapsr"}
-!9 = !{!"eapsr_nzcvq"}
-!10 = !{!"eapsr_g"}
-!11 = !{!"eapsr_nzcvqg"}
-!12 = !{!"xpsr"}
-!13 = !{!"xpsr_nzcvq"}
-!14 = !{!"xpsr_g"}
-!15 = !{!"xpsr_nzcvqg"}
-!16 = !{!"ipsr"}
-!17 = !{!"epsr"}
-!18 = !{!"iepsr"}
-!19 = !{!"msp"}
-!20 = !{!"psp"}
-!21 = !{!"primask"}
-!22 = !{!"basepri"}
-!23 = !{!"basepri_max"}
-!24 = !{!"faultmask"}
-!25 = !{!"control"}
diff --git a/llvm/test/CodeGen/ARM/special-reg.ll b/llvm/test/CodeGen/ARM/special-reg.ll
deleted file mode 100644
index 8b8243ec712..00000000000
--- a/llvm/test/CodeGen/ARM/special-reg.ll
+++ /dev/null
@@ -1,78 +0,0 @@
-; RUN: llc < %s -mtriple=arm-none-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s --check-prefix=ARM --check-prefix=ACORE
-; RUN: llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4 2>&1 | FileCheck %s --check-prefix=ARM --check-prefix=MCORE
-
-define i32 @read_i32_encoded_register() nounwind {
-entry:
-; ARM-LABEL: read_i32_encoded_register:
-; ARM: mrc p1, #2, r0, c3, c4, #5
- %reg = call i32 @llvm.read_register.i32(metadata !0)
- ret i32 %reg
-}
-
-define i64 @read_i64_encoded_register() nounwind {
-entry:
-; ARM-LABEL: read_i64_encoded_register:
-; ARM: mrrc p1, #2, r0, r1, c3
- %reg = call i64 @llvm.read_register.i64(metadata !1)
- ret i64 %reg
-}
-
-define i32 @read_apsr() nounwind {
-entry:
-; ARM-LABEL: read_apsr:
-; ARM: mrs r0, apsr
- %reg = call i32 @llvm.read_register.i32(metadata !2)
- ret i32 %reg
-}
-
-define i32 @read_fpscr() nounwind {
-entry:
-; ARM-LABEL: read_fpscr:
-; ARM: vmrs r0, fpscr
- %reg = call i32 @llvm.read_register.i32(metadata !3)
- ret i32 %reg
-}
-
-define void @write_i32_encoded_register(i32 %x) nounwind {
-entry:
-; ARM-LABEL: write_i32_encoded_register:
-; ARM: mcr p1, #2, r0, c3, c4, #5
- call void @llvm.write_register.i32(metadata !0, i32 %x)
- ret void
-}
-
-define void @write_i64_encoded_register(i64 %x) nounwind {
-entry:
-; ARM-LABEL: write_i64_encoded_register:
-; ARM: mcrr p1, #2, r0, r1, c3
- call void @llvm.write_register.i64(metadata !1, i64 %x)
- ret void
-}
-
-define void @write_apsr(i32 %x) nounwind {
-entry:
-; ARM-LABEL: write_apsr:
-; ACORE: msr APSR_nzcvq, r0
-; MCORE: msr apsr_nzcvq, r0
- call void @llvm.write_register.i32(metadata !4, i32 %x)
- ret void
-}
-
-define void @write_fpscr(i32 %x) nounwind {
-entry:
-; ARM-LABEL: write_fpscr:
-; ARM: vmsr fpscr, r0
- call void @llvm.write_register.i32(metadata !3, i32 %x)
- ret void
-}
-
-declare i32 @llvm.read_register.i32(metadata) nounwind
-declare i64 @llvm.read_register.i64(metadata) nounwind
-declare void @llvm.write_register.i32(metadata, i32) nounwind
-declare void @llvm.write_register.i64(metadata, i64) nounwind
-
-!0 = !{!"cp1:2:c3:c4:5"}
-!1 = !{!"cp1:2:c3"}
-!2 = !{!"apsr"}
-!3 = !{!"fpscr"}
-!4 = !{!"apsr_nzcvq"}
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