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-rw-r--r--llvm/test/CodeGen/Hexagon/adde.ll4
-rw-r--r--llvm/test/CodeGen/Hexagon/alu64.ll2
-rw-r--r--llvm/test/CodeGen/Hexagon/bit-eval.ll2
-rw-r--r--llvm/test/CodeGen/Hexagon/sube.ll4
4 files changed, 6 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/Hexagon/adde.ll b/llvm/test/CodeGen/Hexagon/adde.ll
index 25160a8d338..4a88914dc6c 100644
--- a/llvm/test/CodeGen/Hexagon/adde.ll
+++ b/llvm/test/CodeGen/Hexagon/adde.ll
@@ -1,7 +1,7 @@
; RUN: llc -march=hexagon -disable-hsdr -hexagon-expand-condsets=0 -hexagon-bit=0 < %s | FileCheck %s
-; CHECK: r{{[0-9]+:[0-9]+}} = #1
-; CHECK: r{{[0-9]+:[0-9]+}} = #0
+; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0, #1)
+; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0, #0)
; CHECK: r{{[0-9]+:[0-9]+}} = add(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
diff --git a/llvm/test/CodeGen/Hexagon/alu64.ll b/llvm/test/CodeGen/Hexagon/alu64.ll
index 4334c7b36a0..f986f135937 100644
--- a/llvm/test/CodeGen/Hexagon/alu64.ll
+++ b/llvm/test/CodeGen/Hexagon/alu64.ll
@@ -193,7 +193,7 @@ entry:
}
; CHECK-LABEL: @test53
-; CHECK: = add(r0, r3:2)
+; CHECK: = add(r1:0, r3:2):raw:
define i64 @test53(i32 %Rs, i64 %Rt) #0 {
entry:
%0 = tail call i64 @llvm.hexagon.A2.addsp(i32 %Rs, i64 %Rt)
diff --git a/llvm/test/CodeGen/Hexagon/bit-eval.ll b/llvm/test/CodeGen/Hexagon/bit-eval.ll
index be886aa7459..1d2be5bfc19 100644
--- a/llvm/test/CodeGen/Hexagon/bit-eval.ll
+++ b/llvm/test/CodeGen/Hexagon/bit-eval.ll
@@ -20,7 +20,7 @@ entry:
}
; CHECK-LABEL: test3:
-; CHECK: r1:0 = #1
+; CHECK: r1:0 = combine(#0, #1)
define i64 @test3() #0 {
entry:
%0 = tail call i64 @llvm.hexagon.S4.extractp(i64 -1, i32 63, i32 63)
diff --git a/llvm/test/CodeGen/Hexagon/sube.ll b/llvm/test/CodeGen/Hexagon/sube.ll
index be299b0e1be..fab3dcaefa8 100644
--- a/llvm/test/CodeGen/Hexagon/sube.ll
+++ b/llvm/test/CodeGen/Hexagon/sube.ll
@@ -1,7 +1,7 @@
; RUN: llc -march=hexagon -disable-hsdr -hexagon-expand-condsets=0 -hexagon-bit=0 < %s | FileCheck %s
-; CHECK: r{{[0-9]+:[0-9]+}} = #1
-; CHECK: r{{[0-9]+:[0-9]+}} = #0
+; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0, #1)
+; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0, #0)
; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
; CHECK: r{{[0-9]+:[0-9]+}} = sub(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
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