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-rw-r--r--llvm/test/CodeGen/ARM/setcc-sentinals.ll14
-rw-r--r--llvm/test/CodeGen/X86/setcc-sentinals.ll13
2 files changed, 27 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/setcc-sentinals.ll b/llvm/test/CodeGen/ARM/setcc-sentinals.ll
new file mode 100644
index 00000000000..4033a810985
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/setcc-sentinals.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -mcpu=cortex-a8 -march=arm -asm-verbose=false | FileCheck %s
+
+define zeroext i1 @test0(i32 %x) nounwind {
+; CHECK-LABEL: test0:
+; CHECK-NEXT: add [[REG:(r[0-9]+)|(lr)]], r0, #1
+; CHECK-NEXT: mov r0, #0
+; CHECK-NEXT: cmp [[REG]], #1
+; CHECK-NEXT: movhi r0, #1
+; CHECK-NEXT: bx lr
+ %cmp1 = icmp ne i32 %x, -1
+ %not.cmp = icmp ne i32 %x, 0
+ %.cmp1 = and i1 %cmp1, %not.cmp
+ ret i1 %.cmp1
+}
diff --git a/llvm/test/CodeGen/X86/setcc-sentinals.ll b/llvm/test/CodeGen/X86/setcc-sentinals.ll
new file mode 100644
index 00000000000..cae5f58d17f
--- /dev/null
+++ b/llvm/test/CodeGen/X86/setcc-sentinals.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -mcpu=generic -march=x86-64 -asm-verbose=false | FileCheck %s
+
+define zeroext i1 @test0(i64 %x) nounwind {
+; CHECK-LABEL: test0:
+; CHECK-NEXT: incq %rdi
+; CHECK-NEXT: cmpq $1, %rdi
+; CHECK-NEXT: seta %al
+; CHECK-NEXT: ret
+ %cmp1 = icmp ne i64 %x, -1
+ %not.cmp = icmp ne i64 %x, 0
+ %.cmp1 = and i1 %cmp1, %not.cmp
+ ret i1 %.cmp1
+}
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