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-rw-r--r--llvm/test/CodeGen/X86/avx-isa-check.ll5
-rwxr-xr-xllvm/test/CodeGen/X86/avx512vl-arith.ll2
2 files changed, 6 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/X86/avx-isa-check.ll b/llvm/test/CodeGen/X86/avx-isa-check.ll
index dffc8078e44..5d66dfde0bc 100644
--- a/llvm/test/CodeGen/X86/avx-isa-check.ll
+++ b/llvm/test/CodeGen/X86/avx-isa-check.ll
@@ -680,3 +680,8 @@ define <4 x double> @_inreg4xdouble(double %a) {
%c = shufflevector <4 x double> %b, <4 x double> undef, <4 x i32> zeroinitializer
ret <4 x double> %c
}
+
+define <8 x i32> @test_mul_v8i32(<8 x i32> %arg1, <8 x i32> %arg2) #0 {
+ %ret = mul <8 x i32> %arg1, %arg2
+ ret <8 x i32> %ret
+}
diff --git a/llvm/test/CodeGen/X86/avx512vl-arith.ll b/llvm/test/CodeGen/X86/avx512vl-arith.ll
index b7a7bebe1df..9c056cdee19 100755
--- a/llvm/test/CodeGen/X86/avx512vl-arith.ll
+++ b/llvm/test/CodeGen/X86/avx512vl-arith.ll
@@ -176,7 +176,7 @@ define <8 x i32> @vpsubd256_test(<8 x i32> %i, <8 x i32> %j) nounwind readnone {
define <8 x i32> @vpmulld256_test(<8 x i32> %i, <8 x i32> %j) {
; CHECK-LABEL: vpmulld256_test:
; CHECK: ## BB#0:
-; CHECK-NEXT: vpmulld %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x40,0xc1]
+; CHECK-NEXT: vpmulld %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x40,0xc1]
; CHECK-NEXT: retq ## encoding: [0xc3]
%x = mul <8 x i32> %i, %j
ret <8 x i32> %x
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