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-rw-r--r--llvm/test/CodeGen/X86/widen_shuffle-1.ll115
1 files changed, 75 insertions, 40 deletions
diff --git a/llvm/test/CodeGen/X86/widen_shuffle-1.ll b/llvm/test/CodeGen/X86/widen_shuffle-1.ll
index 66ba6350c8a..781cad5493e 100644
--- a/llvm/test/CodeGen/X86/widen_shuffle-1.ll
+++ b/llvm/test/CodeGen/X86/widen_shuffle-1.ll
@@ -1,18 +1,24 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=x86 -mattr=+sse4.2 | FileCheck %s
-
-target triple = "x86_64-unknown-unknown"
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=X64
; widening shuffle v3float and then a add
define void @shuf(<3 x float>* %dst.addr, <3 x float> %src1,<3 x float> %src2) nounwind {
-; CHECK-LABEL: shuf:
-; CHECK: # BB#0: # %entry
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT: addps %xmm1, %xmm0
-; CHECK-NEXT: extractps $2, %xmm0, 8(%eax)
-; CHECK-NEXT: extractps $1, %xmm0, 4(%eax)
-; CHECK-NEXT: movss %xmm0, (%eax)
-; CHECK-NEXT: retl
+; X86-LABEL: shuf:
+; X86: # BB#0: # %entry
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: addps %xmm1, %xmm0
+; X86-NEXT: extractps $2, %xmm0, 8(%eax)
+; X86-NEXT: extractps $1, %xmm0, 4(%eax)
+; X86-NEXT: movss %xmm0, (%eax)
+; X86-NEXT: retl
+;
+; X64-LABEL: shuf:
+; X64: # BB#0: # %entry
+; X64-NEXT: addps %xmm1, %xmm0
+; X64-NEXT: extractps $2, %xmm0, 8(%rdi)
+; X64-NEXT: movlps %xmm0, (%rdi)
+; X64-NEXT: retq
entry:
%x = shufflevector <3 x float> %src1, <3 x float> %src2, <3 x i32> < i32 0, i32 1, i32 2>
%val = fadd <3 x float> %x, %src2
@@ -23,15 +29,23 @@ entry:
; widening shuffle v3float with a different mask and then a add
define void @shuf2(<3 x float>* %dst.addr, <3 x float> %src1,<3 x float> %src2) nounwind {
-; CHECK-LABEL: shuf2:
-; CHECK: # BB#0: # %entry
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
-; CHECK-NEXT: addps %xmm1, %xmm0
-; CHECK-NEXT: extractps $2, %xmm0, 8(%eax)
-; CHECK-NEXT: extractps $1, %xmm0, 4(%eax)
-; CHECK-NEXT: movss %xmm0, (%eax)
-; CHECK-NEXT: retl
+; X86-LABEL: shuf2:
+; X86: # BB#0: # %entry
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
+; X86-NEXT: addps %xmm1, %xmm0
+; X86-NEXT: extractps $2, %xmm0, 8(%eax)
+; X86-NEXT: extractps $1, %xmm0, 4(%eax)
+; X86-NEXT: movss %xmm0, (%eax)
+; X86-NEXT: retl
+;
+; X64-LABEL: shuf2:
+; X64: # BB#0: # %entry
+; X64-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
+; X64-NEXT: addps %xmm1, %xmm0
+; X64-NEXT: extractps $2, %xmm0, 8(%rdi)
+; X64-NEXT: movlps %xmm0, (%rdi)
+; X64-NEXT: retq
entry:
%x = shufflevector <3 x float> %src1, <3 x float> %src2, <3 x i32> < i32 0, i32 4, i32 2>
%val = fadd <3 x float> %x, %src2
@@ -43,12 +57,18 @@ entry:
; with the operation that we are currently widening, i.e. when replacing
; opA with opB, the DAG will produce new operations with opA.
define void @shuf3(<4 x float> %tmp10, <4 x float> %vecinit15, <4 x float>* %dst) nounwind {
-; CHECK-LABEL: shuf3:
-; CHECK: # BB#0: # %entry
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0,0,0]
-; CHECK-NEXT: movaps %xmm1, (%eax)
-; CHECK-NEXT: retl
+; X86-LABEL: shuf3:
+; X86: # BB#0: # %entry
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0,0,0]
+; X86-NEXT: movaps %xmm1, (%eax)
+; X86-NEXT: retl
+;
+; X64-LABEL: shuf3:
+; X64: # BB#0: # %entry
+; X64-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0,0,0]
+; X64-NEXT: movaps %xmm1, (%rdi)
+; X64-NEXT: retq
entry:
%shuffle.i.i.i12 = shufflevector <4 x float> %tmp10, <4 x float> %vecinit15, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
%tmp25.i.i = shufflevector <4 x float> %shuffle.i.i.i12, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
@@ -67,26 +87,41 @@ entry:
; PR10421: make sure we correctly handle extreme widening with CONCAT_VECTORS
define <8 x i8> @shuf4(<4 x i8> %a, <4 x i8> %b) nounwind readnone {
-; CHECK-LABEL: shuf4:
-; CHECK: # BB#0:
-; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
-; CHECK-NEXT: pshufb %xmm2, %xmm1
-; CHECK-NEXT: pshufb %xmm2, %xmm0
-; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
-; CHECK-NEXT: retl
+; X86-LABEL: shuf4:
+; X86: # BB#0:
+; X86-NEXT: movdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
+; X86-NEXT: pshufb %xmm2, %xmm1
+; X86-NEXT: pshufb %xmm2, %xmm0
+; X86-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; X86-NEXT: retl
+;
+; X64-LABEL: shuf4:
+; X64: # BB#0:
+; X64-NEXT: movdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
+; X64-NEXT: pshufb %xmm2, %xmm1
+; X64-NEXT: pshufb %xmm2, %xmm0
+; X64-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; X64-NEXT: retq
%vshuf = shufflevector <4 x i8> %a, <4 x i8> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x i8> %vshuf
}
; PR11389: another CONCAT_VECTORS case
define void @shuf5(<8 x i8>* %p) nounwind {
-; CHECK-LABEL: shuf5:
-; CHECK: # BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT: movdqa {{.*#+}} xmm0 = [33,33,33,33,33,33,33,33]
-; CHECK-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
-; CHECK-NEXT: movq %xmm0, (%eax)
-; CHECK-NEXT: retl
+; X86-LABEL: shuf5:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movdqa {{.*#+}} xmm0 = [33,33,33,33,33,33,33,33]
+; X86-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
+; X86-NEXT: movq %xmm0, (%eax)
+; X86-NEXT: retl
+;
+; X64-LABEL: shuf5:
+; X64: # BB#0:
+; X64-NEXT: movdqa {{.*#+}} xmm0 = [33,33,33,33,33,33,33,33]
+; X64-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
+; X64-NEXT: movq %xmm0, (%rdi)
+; X64-NEXT: retq
%v = shufflevector <2 x i8> <i8 4, i8 33>, <2 x i8> undef, <8 x i32> <i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
store <8 x i8> %v, <8 x i8>* %p, align 8
ret void
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