diff options
Diffstat (limited to 'llvm/test/CodeGen/X86/vector-trunc-math.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/vector-trunc-math.ll | 664 |
1 files changed, 332 insertions, 332 deletions
diff --git a/llvm/test/CodeGen/X86/vector-trunc-math.ll b/llvm/test/CodeGen/X86/vector-trunc-math.ll index c399ea077cc..45479941143 100644 --- a/llvm/test/CodeGen/X86/vector-trunc-math.ll +++ b/llvm/test/CodeGen/X86/vector-trunc-math.ll @@ -12,14 +12,14 @@ define <4 x i32> @trunc_add_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; SSE-LABEL: trunc_add_v4i64_v4i32: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: paddq %xmm3, %xmm1 ; SSE-NEXT: paddq %xmm2, %xmm0 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_add_v4i64_v4i32: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 ; AVX1-NEXT: vpaddq %xmm2, %xmm3, %xmm2 @@ -29,7 +29,7 @@ define <4 x i32> @trunc_add_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_add_v4i64_v4i32: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpaddq %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] @@ -38,7 +38,7 @@ define <4 x i32> @trunc_add_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_add_v4i64_v4i32: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpaddq %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0 ; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> @@ -51,7 +51,7 @@ define <4 x i32> @trunc_add_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { define <8 x i16> @trunc_add_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; SSE-LABEL: trunc_add_v8i64_v8i16: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: paddq %xmm6, %xmm2 ; SSE-NEXT: paddq %xmm7, %xmm3 ; SSE-NEXT: paddq %xmm4, %xmm0 @@ -70,7 +70,7 @@ define <8 x i16> @trunc_add_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_add_v8i64_v8i16: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vpaddq %xmm2, %xmm0, %xmm4 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 @@ -91,7 +91,7 @@ define <8 x i16> @trunc_add_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_add_v8i64_v8i16: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpaddq %ymm3, %ymm1, %ymm1 ; AVX2-NEXT: vpaddq %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7] @@ -106,7 +106,7 @@ define <8 x i16> @trunc_add_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_add_v8i64_v8i16: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpaddq %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpmovqw %zmm0, %xmm0 ; AVX512-NEXT: vzeroupper @@ -118,7 +118,7 @@ define <8 x i16> @trunc_add_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { define <8 x i16> @trunc_add_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; SSE-LABEL: trunc_add_v8i32_v8i16: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: paddd %xmm2, %xmm0 ; SSE-NEXT: paddd %xmm3, %xmm1 ; SSE-NEXT: pslld $16, %xmm1 @@ -129,7 +129,7 @@ define <8 x i16> @trunc_add_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_add_v8i32_v8i16: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 @@ -142,7 +142,7 @@ define <8 x i16> @trunc_add_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_add_v8i32_v8i16: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpaddd %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] @@ -151,7 +151,7 @@ define <8 x i16> @trunc_add_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_add_v8i32_v8i16: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpaddd %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vpmovdw %zmm0, %ymm0 ; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> @@ -164,7 +164,7 @@ define <8 x i16> @trunc_add_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { define <16 x i8> @trunc_add_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwind { ; SSE-LABEL: trunc_add_v16i64_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: paddq {{[0-9]+}}(%rsp), %xmm0 ; SSE-NEXT: paddq {{[0-9]+}}(%rsp), %xmm1 ; SSE-NEXT: paddq {{[0-9]+}}(%rsp), %xmm2 @@ -192,7 +192,7 @@ define <16 x i8> @trunc_add_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwin ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_add_v16i64_v16i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vpaddq %xmm4, %xmm0, %xmm8 ; AVX1-NEXT: vextractf128 $1, %ymm4, %xmm4 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 @@ -229,7 +229,7 @@ define <16 x i8> @trunc_add_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwin ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_add_v16i64_v16i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpaddq %ymm5, %ymm1, %ymm1 ; AVX2-NEXT: vpaddq %ymm4, %ymm0, %ymm0 ; AVX2-NEXT: vpaddq %ymm7, %ymm3, %ymm3 @@ -257,7 +257,7 @@ define <16 x i8> @trunc_add_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwin ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_add_v16i64_v16i8: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpaddq %zmm3, %zmm1, %zmm1 ; AVX512-NEXT: vpaddq %zmm2, %zmm0, %zmm0 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0 @@ -273,7 +273,7 @@ define <16 x i8> @trunc_add_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwin define <16 x i8> @trunc_add_v16i32_v16i8(<16 x i32> %a0, <16 x i32> %a1) nounwind { ; SSE-LABEL: trunc_add_v16i32_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: paddd %xmm4, %xmm0 ; SSE-NEXT: paddd %xmm5, %xmm1 ; SSE-NEXT: paddd %xmm6, %xmm2 @@ -289,7 +289,7 @@ define <16 x i8> @trunc_add_v16i32_v16i8(<16 x i32> %a0, <16 x i32> %a1) nounwin ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_add_v16i32_v16i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vpaddd %xmm2, %xmm0, %xmm4 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 @@ -310,7 +310,7 @@ define <16 x i8> @trunc_add_v16i32_v16i8(<16 x i32> %a0, <16 x i32> %a1) nounwin ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_add_v16i32_v16i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpaddd %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpaddd %ymm3, %ymm1, %ymm1 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] @@ -326,7 +326,7 @@ define <16 x i8> @trunc_add_v16i32_v16i8(<16 x i32> %a0, <16 x i32> %a1) nounwin ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_add_v16i32_v16i8: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpaddd %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpmovdb %zmm0, %xmm0 ; AVX512-NEXT: vzeroupper @@ -338,7 +338,7 @@ define <16 x i8> @trunc_add_v16i32_v16i8(<16 x i32> %a0, <16 x i32> %a1) nounwin define <16 x i8> @trunc_add_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwind { ; SSE-LABEL: trunc_add_v16i16_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: paddw %xmm2, %xmm0 ; SSE-NEXT: paddw %xmm3, %xmm1 ; SSE-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255] @@ -348,7 +348,7 @@ define <16 x i8> @trunc_add_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwin ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_add_v16i16_v16i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vpaddw %xmm1, %xmm0, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 @@ -361,7 +361,7 @@ define <16 x i8> @trunc_add_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwin ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_add_v16i16_v16i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpaddw %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u> @@ -372,7 +372,7 @@ define <16 x i8> @trunc_add_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwin ; AVX2-NEXT: retq ; ; AVX512F-LABEL: trunc_add_v16i16_v16i8: -; AVX512F: # BB#0: +; AVX512F: # %bb.0: ; AVX512F-NEXT: vpaddw %ymm1, %ymm0, %ymm0 ; AVX512F-NEXT: vpmovsxwd %ymm0, %zmm0 ; AVX512F-NEXT: vpmovdb %zmm0, %xmm0 @@ -380,7 +380,7 @@ define <16 x i8> @trunc_add_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwin ; AVX512F-NEXT: retq ; ; AVX512BW-LABEL: trunc_add_v16i16_v16i8: -; AVX512BW: # BB#0: +; AVX512BW: # %bb.0: ; AVX512BW-NEXT: vpaddw %ymm1, %ymm0, %ymm0 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0 ; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> @@ -388,7 +388,7 @@ define <16 x i8> @trunc_add_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwin ; AVX512BW-NEXT: retq ; ; AVX512DQ-LABEL: trunc_add_v16i16_v16i8: -; AVX512DQ: # BB#0: +; AVX512DQ: # %bb.0: ; AVX512DQ-NEXT: vpaddw %ymm1, %ymm0, %ymm0 ; AVX512DQ-NEXT: vpmovsxwd %ymm0, %zmm0 ; AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0 @@ -401,7 +401,7 @@ define <16 x i8> @trunc_add_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwin define <8 x i16> @trunc_add_v8i32_v8i16_sext_8i8(<16 x i8> %a0, <8 x i32> %a1) { ; SSE-LABEL: trunc_add_v8i32_v8i16_sext_8i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: pslld $16, %xmm2 ; SSE-NEXT: psrad $16, %xmm2 ; SSE-NEXT: pslld $16, %xmm1 @@ -413,7 +413,7 @@ define <8 x i16> @trunc_add_v8i32_v8i16_sext_8i8(<16 x i8> %a0, <8 x i32> %a1) { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_add_v8i32_v8i16_sext_8i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; AVX1-NEXT: vpshufb %xmm3, %xmm2, %xmm2 @@ -425,7 +425,7 @@ define <8 x i16> @trunc_add_v8i32_v8i16_sext_8i8(<16 x i8> %a0, <8 x i32> %a1) { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_add_v8i32_v8i16_sext_8i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpmovsxbw %xmm0, %xmm0 ; AVX2-NEXT: vpshufb {{.*#+}} ymm1 = ymm1[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3] @@ -434,7 +434,7 @@ define <8 x i16> @trunc_add_v8i32_v8i16_sext_8i8(<16 x i8> %a0, <8 x i32> %a1) { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_add_v8i32_v8i16_sext_8i8: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> ; AVX512-NEXT: vpmovdw %zmm1, %ymm1 ; AVX512-NEXT: vpmovsxbw %xmm0, %xmm0 @@ -454,13 +454,13 @@ define <8 x i16> @trunc_add_v8i32_v8i16_sext_8i8(<16 x i8> %a0, <8 x i32> %a1) { define <4 x i32> @trunc_add_const_v4i64_v4i32(<4 x i64> %a0) nounwind { ; SSE-LABEL: trunc_add_const_v4i64_v4i32: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; SSE-NEXT: paddd {{.*}}(%rip), %xmm0 ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_add_const_v4i64_v4i32: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0 @@ -468,7 +468,7 @@ define <4 x i32> @trunc_add_const_v4i64_v4i32(<4 x i64> %a0) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_add_const_v4i64_v4i32: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] ; AVX2-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0 @@ -476,7 +476,7 @@ define <4 x i32> @trunc_add_const_v4i64_v4i32(<4 x i64> %a0) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_add_const_v4i64_v4i32: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512-NEXT: vpmovqd %zmm0, %ymm0 ; AVX512-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0 @@ -489,7 +489,7 @@ define <4 x i32> @trunc_add_const_v4i64_v4i32(<4 x i64> %a0) nounwind { define <8 x i16> @trunc_add_const_v8i64_v8i16(<8 x i64> %a0) nounwind { ; SSE-LABEL: trunc_add_const_v8i64_v8i16: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7] ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] @@ -505,7 +505,7 @@ define <8 x i16> @trunc_add_const_v8i64_v8i16(<8 x i64> %a0) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_add_const_v8i64_v8i16: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3 ; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0],xmm3[1,2,3],xmm2[4],xmm3[5,6,7] @@ -521,7 +521,7 @@ define <8 x i16> @trunc_add_const_v8i64_v8i16(<8 x i64> %a0) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_add_const_v8i64_v8i16: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] ; AVX2-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7] @@ -534,7 +534,7 @@ define <8 x i16> @trunc_add_const_v8i64_v8i16(<8 x i64> %a0) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_add_const_v8i64_v8i16: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpmovqw %zmm0, %xmm0 ; AVX512-NEXT: vpaddw {{.*}}(%rip), %xmm0, %xmm0 ; AVX512-NEXT: vzeroupper @@ -546,7 +546,7 @@ define <8 x i16> @trunc_add_const_v8i64_v8i16(<8 x i64> %a0) nounwind { define <8 x i16> @trunc_add_const_v8i32_v8i16(<8 x i32> %a0) nounwind { ; SSE-LABEL: trunc_add_const_v8i32_v8i16: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: pslld $16, %xmm1 ; SSE-NEXT: psrad $16, %xmm1 ; SSE-NEXT: pslld $16, %xmm0 @@ -556,7 +556,7 @@ define <8 x i16> @trunc_add_const_v8i32_v8i16(<8 x i32> %a0) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_add_const_v8i32_v8i16: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 @@ -567,7 +567,7 @@ define <8 x i16> @trunc_add_const_v8i32_v8i16(<8 x i32> %a0) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_add_const_v8i32_v8i16: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] ; AVX2-NEXT: vpaddw {{.*}}(%rip), %xmm0, %xmm0 @@ -575,7 +575,7 @@ define <8 x i16> @trunc_add_const_v8i32_v8i16(<8 x i32> %a0) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_add_const_v8i32_v8i16: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512-NEXT: vpmovdw %zmm0, %ymm0 ; AVX512-NEXT: vpaddw {{.*}}(%rip), %xmm0, %xmm0 @@ -588,7 +588,7 @@ define <8 x i16> @trunc_add_const_v8i32_v8i16(<8 x i32> %a0) nounwind { define <16 x i8> @trunc_add_const_v16i64_v16i8(<16 x i64> %a0) nounwind { ; SSE-LABEL: trunc_add_const_v16i64_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movdqa {{.*#+}} xmm8 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0] ; SSE-NEXT: pand %xmm8, %xmm7 ; SSE-NEXT: pand %xmm8, %xmm6 @@ -609,7 +609,7 @@ define <16 x i8> @trunc_add_const_v16i64_v16i8(<16 x i64> %a0) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_add_const_v16i64_v16i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm4 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm5 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0] ; AVX1-NEXT: vpand %xmm5, %xmm4, %xmm4 @@ -635,7 +635,7 @@ define <16 x i8> @trunc_add_const_v16i64_v16i8(<16 x i64> %a0) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_add_const_v16i64_v16i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[0,2,2,3,4,6,6,7] ; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,2,2,3] ; AVX2-NEXT: vpshufd {{.*#+}} ymm3 = ymm3[0,2,2,3,4,6,6,7] @@ -660,7 +660,7 @@ define <16 x i8> @trunc_add_const_v16i64_v16i8(<16 x i64> %a0) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_add_const_v16i64_v16i8: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpmovqd %zmm0, %ymm0 ; AVX512-NEXT: vpmovqd %zmm1, %ymm1 ; AVX512-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0 @@ -675,7 +675,7 @@ define <16 x i8> @trunc_add_const_v16i64_v16i8(<16 x i64> %a0) nounwind { define <16 x i8> @trunc_add_const_v16i32_v16i8(<16 x i32> %a0) nounwind { ; SSE-LABEL: trunc_add_const_v16i32_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movdqa {{.*#+}} xmm4 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0] ; SSE-NEXT: pand %xmm4, %xmm3 ; SSE-NEXT: pand %xmm4, %xmm2 @@ -688,7 +688,7 @@ define <16 x i8> @trunc_add_const_v16i32_v16i8(<16 x i32> %a0) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_add_const_v16i32_v16i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0] ; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2 @@ -704,7 +704,7 @@ define <16 x i8> @trunc_add_const_v16i32_v16i8(<16 x i32> %a0) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_add_const_v16i32_v16i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpshufb %ymm2, %ymm1, %ymm1 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3] @@ -719,7 +719,7 @@ define <16 x i8> @trunc_add_const_v16i32_v16i8(<16 x i32> %a0) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_add_const_v16i32_v16i8: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpmovdb %zmm0, %xmm0 ; AVX512-NEXT: vpaddb {{.*}}(%rip), %xmm0, %xmm0 ; AVX512-NEXT: vzeroupper @@ -731,7 +731,7 @@ define <16 x i8> @trunc_add_const_v16i32_v16i8(<16 x i32> %a0) nounwind { define <16 x i8> @trunc_add_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; SSE-LABEL: trunc_add_const_v16i16_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255] ; SSE-NEXT: pand %xmm2, %xmm1 ; SSE-NEXT: pand %xmm2, %xmm0 @@ -740,7 +740,7 @@ define <16 x i8> @trunc_add_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_add_const_v16i16_v16i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u> ; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 @@ -751,7 +751,7 @@ define <16 x i8> @trunc_add_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_add_const_v16i16_v16i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u> ; AVX2-NEXT: vpshufb %xmm2, %xmm1, %xmm1 @@ -762,7 +762,7 @@ define <16 x i8> @trunc_add_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; AVX2-NEXT: retq ; ; AVX512F-LABEL: trunc_add_const_v16i16_v16i8: -; AVX512F: # BB#0: +; AVX512F: # %bb.0: ; AVX512F-NEXT: vpmovsxwd %ymm0, %zmm0 ; AVX512F-NEXT: vpmovdb %zmm0, %xmm0 ; AVX512F-NEXT: vpaddb {{.*}}(%rip), %xmm0, %xmm0 @@ -770,7 +770,7 @@ define <16 x i8> @trunc_add_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; AVX512F-NEXT: retq ; ; AVX512BW-LABEL: trunc_add_const_v16i16_v16i8: -; AVX512BW: # BB#0: +; AVX512BW: # %bb.0: ; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0 ; AVX512BW-NEXT: vpaddb {{.*}}(%rip), %xmm0, %xmm0 @@ -778,7 +778,7 @@ define <16 x i8> @trunc_add_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; AVX512BW-NEXT: retq ; ; AVX512DQ-LABEL: trunc_add_const_v16i16_v16i8: -; AVX512DQ: # BB#0: +; AVX512DQ: # %bb.0: ; AVX512DQ-NEXT: vpmovsxwd %ymm0, %zmm0 ; AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0 ; AVX512DQ-NEXT: vpaddb {{.*}}(%rip), %xmm0, %xmm0 @@ -795,14 +795,14 @@ define <16 x i8> @trunc_add_const_v16i16_v16i8(<16 x i16> %a0) nounwind { define <4 x i32> @trunc_sub_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; SSE-LABEL: trunc_sub_v4i64_v4i32: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: psubq %xmm3, %xmm1 ; SSE-NEXT: psubq %xmm2, %xmm0 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_sub_v4i64_v4i32: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 ; AVX1-NEXT: vpsubq %xmm2, %xmm3, %xmm2 @@ -812,7 +812,7 @@ define <4 x i32> @trunc_sub_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_sub_v4i64_v4i32: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpsubq %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] @@ -821,7 +821,7 @@ define <4 x i32> @trunc_sub_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_sub_v4i64_v4i32: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpsubq %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0 ; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> @@ -834,7 +834,7 @@ define <4 x i32> @trunc_sub_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { define <8 x i16> @trunc_sub_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; SSE-LABEL: trunc_sub_v8i64_v8i16: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: psubq %xmm6, %xmm2 ; SSE-NEXT: psubq %xmm7, %xmm3 ; SSE-NEXT: psubq %xmm4, %xmm0 @@ -853,7 +853,7 @@ define <8 x i16> @trunc_sub_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_sub_v8i64_v8i16: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vpsubq %xmm2, %xmm0, %xmm4 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 @@ -874,7 +874,7 @@ define <8 x i16> @trunc_sub_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_sub_v8i64_v8i16: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpsubq %ymm3, %ymm1, %ymm1 ; AVX2-NEXT: vpsubq %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7] @@ -889,7 +889,7 @@ define <8 x i16> @trunc_sub_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_sub_v8i64_v8i16: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpsubq %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpmovqw %zmm0, %xmm0 ; AVX512-NEXT: vzeroupper @@ -901,7 +901,7 @@ define <8 x i16> @trunc_sub_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { define <8 x i16> @trunc_sub_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; SSE-LABEL: trunc_sub_v8i32_v8i16: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: psubd %xmm2, %xmm0 ; SSE-NEXT: psubd %xmm3, %xmm1 ; SSE-NEXT: pslld $16, %xmm1 @@ -912,7 +912,7 @@ define <8 x i16> @trunc_sub_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_sub_v8i32_v8i16: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 @@ -925,7 +925,7 @@ define <8 x i16> @trunc_sub_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_sub_v8i32_v8i16: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpsubd %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] @@ -934,7 +934,7 @@ define <8 x i16> @trunc_sub_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_sub_v8i32_v8i16: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpsubd %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vpmovdw %zmm0, %ymm0 ; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> @@ -947,7 +947,7 @@ define <8 x i16> @trunc_sub_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { define <16 x i8> @trunc_sub_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwind { ; SSE-LABEL: trunc_sub_v16i64_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: psubq {{[0-9]+}}(%rsp), %xmm0 ; SSE-NEXT: psubq {{[0-9]+}}(%rsp), %xmm1 ; SSE-NEXT: psubq {{[0-9]+}}(%rsp), %xmm2 @@ -975,7 +975,7 @@ define <16 x i8> @trunc_sub_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwin ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_sub_v16i64_v16i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vpsubq %xmm4, %xmm0, %xmm8 ; AVX1-NEXT: vextractf128 $1, %ymm4, %xmm4 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 @@ -1012,7 +1012,7 @@ define <16 x i8> @trunc_sub_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwin ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_sub_v16i64_v16i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpsubq %ymm5, %ymm1, %ymm1 ; AVX2-NEXT: vpsubq %ymm4, %ymm0, %ymm0 ; AVX2-NEXT: vpsubq %ymm7, %ymm3, %ymm3 @@ -1040,7 +1040,7 @@ define <16 x i8> @trunc_sub_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwin ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_sub_v16i64_v16i8: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpsubq %zmm3, %zmm1, %zmm1 ; AVX512-NEXT: vpsubq %zmm2, %zmm0, %zmm0 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0 @@ -1056,7 +1056,7 @@ define <16 x i8> @trunc_sub_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwin define <16 x i8> @trunc_sub_v16i32_v16i8(<16 x i32> %a0, <16 x i32> %a1) nounwind { ; SSE-LABEL: trunc_sub_v16i32_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: psubd %xmm4, %xmm0 ; SSE-NEXT: psubd %xmm5, %xmm1 ; SSE-NEXT: psubd %xmm6, %xmm2 @@ -1072,7 +1072,7 @@ define <16 x i8> @trunc_sub_v16i32_v16i8(<16 x i32> %a0, <16 x i32> %a1) nounwin ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_sub_v16i32_v16i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vpsubd %xmm2, %xmm0, %xmm4 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 @@ -1093,7 +1093,7 @@ define <16 x i8> @trunc_sub_v16i32_v16i8(<16 x i32> %a0, <16 x i32> %a1) nounwin ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_sub_v16i32_v16i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpsubd %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpsubd %ymm3, %ymm1, %ymm1 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] @@ -1109,7 +1109,7 @@ define <16 x i8> @trunc_sub_v16i32_v16i8(<16 x i32> %a0, <16 x i32> %a1) nounwin ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_sub_v16i32_v16i8: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpsubd %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpmovdb %zmm0, %xmm0 ; AVX512-NEXT: vzeroupper @@ -1121,7 +1121,7 @@ define <16 x i8> @trunc_sub_v16i32_v16i8(<16 x i32> %a0, <16 x i32> %a1) nounwin define <16 x i8> @trunc_sub_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwind { ; SSE-LABEL: trunc_sub_v16i16_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: psubw %xmm2, %xmm0 ; SSE-NEXT: psubw %xmm3, %xmm1 ; SSE-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255] @@ -1131,7 +1131,7 @@ define <16 x i8> @trunc_sub_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwin ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_sub_v16i16_v16i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vpsubw %xmm1, %xmm0, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 @@ -1144,7 +1144,7 @@ define <16 x i8> @trunc_sub_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwin ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_sub_v16i16_v16i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpsubw %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u> @@ -1155,7 +1155,7 @@ define <16 x i8> @trunc_sub_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwin ; AVX2-NEXT: retq ; ; AVX512F-LABEL: trunc_sub_v16i16_v16i8: -; AVX512F: # BB#0: +; AVX512F: # %bb.0: ; AVX512F-NEXT: vpsubw %ymm1, %ymm0, %ymm0 ; AVX512F-NEXT: vpmovsxwd %ymm0, %zmm0 ; AVX512F-NEXT: vpmovdb %zmm0, %xmm0 @@ -1163,7 +1163,7 @@ define <16 x i8> @trunc_sub_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwin ; AVX512F-NEXT: retq ; ; AVX512BW-LABEL: trunc_sub_v16i16_v16i8: -; AVX512BW: # BB#0: +; AVX512BW: # %bb.0: ; AVX512BW-NEXT: vpsubw %ymm1, %ymm0, %ymm0 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0 ; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> @@ -1171,7 +1171,7 @@ define <16 x i8> @trunc_sub_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwin ; AVX512BW-NEXT: retq ; ; AVX512DQ-LABEL: trunc_sub_v16i16_v16i8: -; AVX512DQ: # BB#0: +; AVX512DQ: # %bb.0: ; AVX512DQ-NEXT: vpsubw %ymm1, %ymm0, %ymm0 ; AVX512DQ-NEXT: vpmovsxwd %ymm0, %zmm0 ; AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0 @@ -1188,7 +1188,7 @@ define <16 x i8> @trunc_sub_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwin define <4 x i32> @trunc_sub_const_v4i64_v4i32(<4 x i64> %a0) nounwind { ; SSE-LABEL: trunc_sub_const_v4i64_v4i32: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movl $1, %eax ; SSE-NEXT: movq %rax, %xmm2 ; SSE-NEXT: pslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0,1,2,3,4,5,6,7] @@ -1198,7 +1198,7 @@ define <4 x i32> @trunc_sub_const_v4i64_v4i32(<4 x i64> %a0) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_sub_const_v4i64_v4i32: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: movl $1, %eax ; AVX1-NEXT: vmovq %rax, %xmm1 ; AVX1-NEXT: vpslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1,2,3,4,5,6,7] @@ -1210,7 +1210,7 @@ define <4 x i32> @trunc_sub_const_v4i64_v4i32(<4 x i64> %a0) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_sub_const_v4i64_v4i32: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpsubq {{.*}}(%rip), %ymm0, %ymm0 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] @@ -1219,7 +1219,7 @@ define <4 x i32> @trunc_sub_const_v4i64_v4i32(<4 x i64> %a0) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_sub_const_v4i64_v4i32: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpsubq {{.*}}(%rip), %ymm0, %ymm0 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0 ; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> @@ -1232,7 +1232,7 @@ define <4 x i32> @trunc_sub_const_v4i64_v4i32(<4 x i64> %a0) nounwind { define <8 x i16> @trunc_sub_const_v8i64_v8i16(<8 x i64> %a0) nounwind { ; SSE-LABEL: trunc_sub_const_v8i64_v8i16: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movl $1, %eax ; SSE-NEXT: movq %rax, %xmm4 ; SSE-NEXT: pslldq {{.*#+}} xmm4 = zero,zero,zero,zero,zero,zero,zero,zero,xmm4[0,1,2,3,4,5,6,7] @@ -1255,7 +1255,7 @@ define <8 x i16> @trunc_sub_const_v8i64_v8i16(<8 x i64> %a0) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_sub_const_v8i64_v8i16: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: movl $1, %eax ; AVX1-NEXT: vmovq %rax, %xmm2 ; AVX1-NEXT: vpslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0,1,2,3,4,5,6,7] @@ -1277,7 +1277,7 @@ define <8 x i16> @trunc_sub_const_v8i64_v8i16(<8 x i64> %a0) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_sub_const_v8i64_v8i16: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpsubq {{.*}}(%rip), %ymm1, %ymm1 ; AVX2-NEXT: vpsubq {{.*}}(%rip), %ymm0, %ymm0 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7] @@ -1292,7 +1292,7 @@ define <8 x i16> @trunc_sub_const_v8i64_v8i16(<8 x i64> %a0) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_sub_const_v8i64_v8i16: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpsubq {{.*}}(%rip), %zmm0, %zmm0 ; AVX512-NEXT: vpmovqw %zmm0, %xmm0 ; AVX512-NEXT: vzeroupper @@ -1304,7 +1304,7 @@ define <8 x i16> @trunc_sub_const_v8i64_v8i16(<8 x i64> %a0) nounwind { define <8 x i16> @trunc_sub_const_v8i32_v8i16(<8 x i32> %a0) nounwind { ; SSE-LABEL: trunc_sub_const_v8i32_v8i16: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: psubd {{.*}}(%rip), %xmm0 ; SSE-NEXT: psubd {{.*}}(%rip), %xmm1 ; SSE-NEXT: pslld $16, %xmm1 @@ -1315,7 +1315,7 @@ define <8 x i16> @trunc_sub_const_v8i32_v8i16(<8 x i32> %a0) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_sub_const_v8i32_v8i16: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vpsubd {{.*}}(%rip), %xmm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vpsubd {{.*}}(%rip), %xmm0, %xmm0 @@ -1327,7 +1327,7 @@ define <8 x i16> @trunc_sub_const_v8i32_v8i16(<8 x i32> %a0) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_sub_const_v8i32_v8i16: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpsubd {{.*}}(%rip), %ymm0, %ymm0 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] @@ -1336,7 +1336,7 @@ define <8 x i16> @trunc_sub_const_v8i32_v8i16(<8 x i32> %a0) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_sub_const_v8i32_v8i16: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpsubd {{.*}}(%rip), %ymm0, %ymm0 ; AVX512-NEXT: vpmovdw %zmm0, %ymm0 ; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> @@ -1349,7 +1349,7 @@ define <8 x i16> @trunc_sub_const_v8i32_v8i16(<8 x i32> %a0) nounwind { define <16 x i8> @trunc_sub_const_v16i64_v16i8(<16 x i64> %a0) nounwind { ; SSE-LABEL: trunc_sub_const_v16i64_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movl $1, %eax ; SSE-NEXT: movq %rax, %xmm8 ; SSE-NEXT: pslldq {{.*#+}} xmm8 = zero,zero,zero,zero,zero,zero,zero,zero,xmm8[0,1,2,3,4,5,6,7] @@ -1380,7 +1380,7 @@ define <16 x i8> @trunc_sub_const_v16i64_v16i8(<16 x i64> %a0) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_sub_const_v16i64_v16i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: movl $1, %eax ; AVX1-NEXT: vmovq %rax, %xmm4 ; AVX1-NEXT: vpslldq {{.*#+}} xmm4 = zero,zero,zero,zero,zero,zero,zero,zero,xmm4[0,1,2,3,4,5,6,7] @@ -1416,7 +1416,7 @@ define <16 x i8> @trunc_sub_const_v16i64_v16i8(<16 x i64> %a0) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_sub_const_v16i64_v16i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpsubq {{.*}}(%rip), %ymm1, %ymm1 ; AVX2-NEXT: vpsubq {{.*}}(%rip), %ymm0, %ymm0 ; AVX2-NEXT: vpsubq {{.*}}(%rip), %ymm3, %ymm3 @@ -1444,7 +1444,7 @@ define <16 x i8> @trunc_sub_const_v16i64_v16i8(<16 x i64> %a0) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_sub_const_v16i64_v16i8: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpsubq {{.*}}(%rip), %zmm1, %zmm1 ; AVX512-NEXT: vpsubq {{.*}}(%rip), %zmm0, %zmm0 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0 @@ -1460,7 +1460,7 @@ define <16 x i8> @trunc_sub_const_v16i64_v16i8(<16 x i64> %a0) nounwind { define <16 x i8> @trunc_sub_const_v16i32_v16i8(<16 x i32> %a0) nounwind { ; SSE-LABEL: trunc_sub_const_v16i32_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: psubd {{.*}}(%rip), %xmm0 ; SSE-NEXT: psubd {{.*}}(%rip), %xmm1 ; SSE-NEXT: psubd {{.*}}(%rip), %xmm2 @@ -1476,7 +1476,7 @@ define <16 x i8> @trunc_sub_const_v16i32_v16i8(<16 x i32> %a0) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_sub_const_v16i32_v16i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vpsubd {{.*}}(%rip), %xmm0, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vpsubd {{.*}}(%rip), %xmm0, %xmm0 @@ -1495,7 +1495,7 @@ define <16 x i8> @trunc_sub_const_v16i32_v16i8(<16 x i32> %a0) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_sub_const_v16i32_v16i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpsubd {{.*}}(%rip), %ymm0, %ymm0 ; AVX2-NEXT: vpsubd {{.*}}(%rip), %ymm1, %ymm1 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] @@ -1511,7 +1511,7 @@ define <16 x i8> @trunc_sub_const_v16i32_v16i8(<16 x i32> %a0) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_sub_const_v16i32_v16i8: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpsubd {{.*}}(%rip), %zmm0, %zmm0 ; AVX512-NEXT: vpmovdb %zmm0, %xmm0 ; AVX512-NEXT: vzeroupper @@ -1523,7 +1523,7 @@ define <16 x i8> @trunc_sub_const_v16i32_v16i8(<16 x i32> %a0) nounwind { define <16 x i8> @trunc_sub_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; SSE-LABEL: trunc_sub_const_v16i16_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: psubw {{.*}}(%rip), %xmm0 ; SSE-NEXT: psubw {{.*}}(%rip), %xmm1 ; SSE-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255] @@ -1533,7 +1533,7 @@ define <16 x i8> @trunc_sub_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_sub_const_v16i16_v16i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vpsubw {{.*}}(%rip), %xmm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vpsubw {{.*}}(%rip), %xmm0, %xmm0 @@ -1545,7 +1545,7 @@ define <16 x i8> @trunc_sub_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_sub_const_v16i16_v16i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpsubw {{.*}}(%rip), %ymm0, %ymm0 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u> @@ -1556,7 +1556,7 @@ define <16 x i8> @trunc_sub_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; AVX2-NEXT: retq ; ; AVX512F-LABEL: trunc_sub_const_v16i16_v16i8: -; AVX512F: # BB#0: +; AVX512F: # %bb.0: ; AVX512F-NEXT: vpsubw {{.*}}(%rip), %ymm0, %ymm0 ; AVX512F-NEXT: vpmovsxwd %ymm0, %zmm0 ; AVX512F-NEXT: vpmovdb %zmm0, %xmm0 @@ -1564,7 +1564,7 @@ define <16 x i8> @trunc_sub_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; AVX512F-NEXT: retq ; ; AVX512BW-LABEL: trunc_sub_const_v16i16_v16i8: -; AVX512BW: # BB#0: +; AVX512BW: # %bb.0: ; AVX512BW-NEXT: vpsubw {{.*}}(%rip), %ymm0, %ymm0 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0 ; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> @@ -1572,7 +1572,7 @@ define <16 x i8> @trunc_sub_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; AVX512BW-NEXT: retq ; ; AVX512DQ-LABEL: trunc_sub_const_v16i16_v16i8: -; AVX512DQ: # BB#0: +; AVX512DQ: # %bb.0: ; AVX512DQ-NEXT: vpsubw {{.*}}(%rip), %ymm0, %ymm0 ; AVX512DQ-NEXT: vpmovsxwd %ymm0, %zmm0 ; AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0 @@ -1589,7 +1589,7 @@ define <16 x i8> @trunc_sub_const_v16i16_v16i8(<16 x i16> %a0) nounwind { define <4 x i32> @trunc_mul_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; SSE-LABEL: trunc_mul_v4i64_v4i32: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm1, %xmm4 ; SSE-NEXT: psrlq $32, %xmm4 ; SSE-NEXT: pmuludq %xmm3, %xmm4 @@ -1614,7 +1614,7 @@ define <4 x i32> @trunc_mul_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_mul_v4i64_v4i32: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,2],xmm2[0,2] ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 @@ -1624,7 +1624,7 @@ define <4 x i32> @trunc_mul_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_mul_v4i64_v4i32: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7] ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3] ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7] @@ -1634,7 +1634,7 @@ define <4 x i32> @trunc_mul_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; AVX2-NEXT: retq ; ; AVX512F-LABEL: trunc_mul_v4i64_v4i32: -; AVX512F: # BB#0: +; AVX512F: # %bb.0: ; AVX512F-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> ; AVX512F-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512F-NEXT: vpmovqd %zmm1, %ymm1 @@ -1644,7 +1644,7 @@ define <4 x i32> @trunc_mul_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; AVX512F-NEXT: retq ; ; AVX512BW-LABEL: trunc_mul_v4i64_v4i32: -; AVX512BW: # BB#0: +; AVX512BW: # %bb.0: ; AVX512BW-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> ; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512BW-NEXT: vpmovqd %zmm1, %ymm1 @@ -1654,7 +1654,7 @@ define <4 x i32> @trunc_mul_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; AVX512BW-NEXT: retq ; ; AVX512DQ-LABEL: trunc_mul_v4i64_v4i32: -; AVX512DQ: # BB#0: +; AVX512DQ: # %bb.0: ; AVX512DQ-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> ; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512DQ-NEXT: vpmullq %zmm1, %zmm0, %zmm0 @@ -1669,7 +1669,7 @@ define <4 x i32> @trunc_mul_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { define <8 x i16> @trunc_mul_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; SSE-LABEL: trunc_mul_v8i64_v8i16: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm5[0,2,2,3] ; SSE-NEXT: pshuflw {{.*#+}} xmm5 = xmm5[0,2,2,3,4,5,6,7] ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,2,2,3] @@ -1696,7 +1696,7 @@ define <8 x i16> @trunc_mul_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_mul_v8i64_v8i16: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm4 ; AVX1-NEXT: vpxor %xmm5, %xmm5, %xmm5 ; AVX1-NEXT: vpblendw {{.*#+}} xmm4 = xmm4[0],xmm5[1,2,3],xmm4[4],xmm5[5,6,7] @@ -1721,7 +1721,7 @@ define <8 x i16> @trunc_mul_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_mul_v8i64_v8i16: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[0,2,2,3,4,6,6,7] ; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,2,2,3] ; AVX2-NEXT: vpshufd {{.*#+}} ymm3 = ymm3[0,2,2,3,4,6,6,7] @@ -1742,7 +1742,7 @@ define <8 x i16> @trunc_mul_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; AVX2-NEXT: retq ; ; AVX512F-LABEL: trunc_mul_v8i64_v8i16: -; AVX512F: # BB#0: +; AVX512F: # %bb.0: ; AVX512F-NEXT: vpmovqw %zmm1, %xmm1 ; AVX512F-NEXT: vpmovqw %zmm0, %xmm0 ; AVX512F-NEXT: vpmullw %xmm1, %xmm0, %xmm0 @@ -1750,7 +1750,7 @@ define <8 x i16> @trunc_mul_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; AVX512F-NEXT: retq ; ; AVX512BW-LABEL: trunc_mul_v8i64_v8i16: -; AVX512BW: # BB#0: +; AVX512BW: # %bb.0: ; AVX512BW-NEXT: vpmovqw %zmm1, %xmm1 ; AVX512BW-NEXT: vpmovqw %zmm0, %xmm0 ; AVX512BW-NEXT: vpmullw %xmm1, %xmm0, %xmm0 @@ -1758,7 +1758,7 @@ define <8 x i16> @trunc_mul_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; AVX512BW-NEXT: retq ; ; AVX512DQ-LABEL: trunc_mul_v8i64_v8i16: -; AVX512DQ: # BB#0: +; AVX512DQ: # %bb.0: ; AVX512DQ-NEXT: vpmullq %zmm1, %zmm0, %zmm0 ; AVX512DQ-NEXT: vpmovqw %zmm0, %xmm0 ; AVX512DQ-NEXT: vzeroupper @@ -1770,7 +1770,7 @@ define <8 x i16> @trunc_mul_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { define <8 x i16> @trunc_mul_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; SSE-LABEL: trunc_mul_v8i32_v8i16: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm0[1,1,3,3] ; SSE-NEXT: pmuludq %xmm2, %xmm0 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] @@ -1793,7 +1793,7 @@ define <8 x i16> @trunc_mul_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_mul_v8i32_v8i16: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vpmulld %xmm1, %xmm0, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 @@ -1806,7 +1806,7 @@ define <8 x i16> @trunc_mul_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_mul_v8i32_v8i16: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpmulld %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] @@ -1815,7 +1815,7 @@ define <8 x i16> @trunc_mul_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_mul_v8i32_v8i16: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpmulld %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vpmovdw %zmm0, %ymm0 ; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> @@ -1828,7 +1828,7 @@ define <8 x i16> @trunc_mul_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { define <16 x i8> @trunc_mul_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwind { ; SSE-LABEL: trunc_mul_v16i64_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8 ; SSE-NEXT: movdqa %xmm0, %xmm9 ; SSE-NEXT: psrlq $32, %xmm9 @@ -1936,7 +1936,7 @@ define <16 x i8> @trunc_mul_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwin ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_mul_v16i64_v16i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vpsrlq $32, %xmm0, %xmm8 ; AVX1-NEXT: vpmuludq %xmm4, %xmm8, %xmm8 ; AVX1-NEXT: vpsrlq $32, %xmm4, %xmm9 @@ -2029,7 +2029,7 @@ define <16 x i8> @trunc_mul_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwin ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_mul_v16i64_v16i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpshufd {{.*#+}} ymm7 = ymm7[0,2,2,3,4,6,6,7] ; AVX2-NEXT: vpermq {{.*#+}} ymm7 = ymm7[0,2,2,3] ; AVX2-NEXT: vpshufd {{.*#+}} ymm3 = ymm3[0,2,2,3,4,6,6,7] @@ -2065,7 +2065,7 @@ define <16 x i8> @trunc_mul_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwin ; AVX2-NEXT: retq ; ; AVX512F-LABEL: trunc_mul_v16i64_v16i8: -; AVX512F: # BB#0: +; AVX512F: # %bb.0: ; AVX512F-NEXT: vpmovqd %zmm3, %ymm3 ; AVX512F-NEXT: vpmovqd %zmm1, %ymm1 ; AVX512F-NEXT: vpmulld %ymm3, %ymm1, %ymm1 @@ -2078,7 +2078,7 @@ define <16 x i8> @trunc_mul_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwin ; AVX512F-NEXT: retq ; ; AVX512BW-LABEL: trunc_mul_v16i64_v16i8: -; AVX512BW: # BB#0: +; AVX512BW: # %bb.0: ; AVX512BW-NEXT: vpmovqd %zmm3, %ymm3 ; AVX512BW-NEXT: vpmovqd %zmm1, %ymm1 ; AVX512BW-NEXT: vpmulld %ymm3, %ymm1, %ymm1 @@ -2091,7 +2091,7 @@ define <16 x i8> @trunc_mul_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwin ; AVX512BW-NEXT: retq ; ; AVX512DQ-LABEL: trunc_mul_v16i64_v16i8: -; AVX512DQ: # BB#0: +; AVX512DQ: # %bb.0: ; AVX512DQ-NEXT: vpmullq %zmm3, %zmm1, %zmm1 ; AVX512DQ-NEXT: vpmullq %zmm2, %zmm0, %zmm0 ; AVX512DQ-NEXT: vpmovqd %zmm0, %ymm0 @@ -2107,7 +2107,7 @@ define <16 x i8> @trunc_mul_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwin define <16 x i8> @trunc_mul_v16i32_v16i8(<16 x i32> %a0, <16 x i32> %a1) nounwind { ; SSE-LABEL: trunc_mul_v16i32_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: pshufd {{.*#+}} xmm8 = xmm0[1,1,3,3] ; SSE-NEXT: pmuludq %xmm4, %xmm0 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] @@ -2147,7 +2147,7 @@ define <16 x i8> @trunc_mul_v16i32_v16i8(<16 x i32> %a0, <16 x i32> %a1) nounwin ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_mul_v16i32_v16i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vpmulld %xmm2, %xmm0, %xmm4 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 @@ -2168,7 +2168,7 @@ define <16 x i8> @trunc_mul_v16i32_v16i8(<16 x i32> %a0, <16 x i32> %a1) nounwin ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_mul_v16i32_v16i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpmulld %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpmulld %ymm3, %ymm1, %ymm1 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] @@ -2184,7 +2184,7 @@ define <16 x i8> @trunc_mul_v16i32_v16i8(<16 x i32> %a0, <16 x i32> %a1) nounwin ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_mul_v16i32_v16i8: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpmulld %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpmovdb %zmm0, %xmm0 ; AVX512-NEXT: vzeroupper @@ -2196,7 +2196,7 @@ define <16 x i8> @trunc_mul_v16i32_v16i8(<16 x i32> %a0, <16 x i32> %a1) nounwin define <16 x i8> @trunc_mul_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwind { ; SSE-LABEL: trunc_mul_v16i16_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: pmullw %xmm2, %xmm0 ; SSE-NEXT: pmullw %xmm3, %xmm1 ; SSE-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255] @@ -2206,7 +2206,7 @@ define <16 x i8> @trunc_mul_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwin ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_mul_v16i16_v16i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vpmullw %xmm1, %xmm0, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 @@ -2219,7 +2219,7 @@ define <16 x i8> @trunc_mul_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwin ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_mul_v16i16_v16i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpmullw %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u> @@ -2230,7 +2230,7 @@ define <16 x i8> @trunc_mul_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwin ; AVX2-NEXT: retq ; ; AVX512F-LABEL: trunc_mul_v16i16_v16i8: -; AVX512F: # BB#0: +; AVX512F: # %bb.0: ; AVX512F-NEXT: vpmullw %ymm1, %ymm0, %ymm0 ; AVX512F-NEXT: vpmovsxwd %ymm0, %zmm0 ; AVX512F-NEXT: vpmovdb %zmm0, %xmm0 @@ -2238,7 +2238,7 @@ define <16 x i8> @trunc_mul_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwin ; AVX512F-NEXT: retq ; ; AVX512BW-LABEL: trunc_mul_v16i16_v16i8: -; AVX512BW: # BB#0: +; AVX512BW: # %bb.0: ; AVX512BW-NEXT: vpmullw %ymm1, %ymm0, %ymm0 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0 ; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> @@ -2246,7 +2246,7 @@ define <16 x i8> @trunc_mul_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwin ; AVX512BW-NEXT: retq ; ; AVX512DQ-LABEL: trunc_mul_v16i16_v16i8: -; AVX512DQ: # BB#0: +; AVX512DQ: # %bb.0: ; AVX512DQ-NEXT: vpmullw %ymm1, %ymm0, %ymm0 ; AVX512DQ-NEXT: vpmovsxwd %ymm0, %zmm0 ; AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0 @@ -2259,7 +2259,7 @@ define <16 x i8> @trunc_mul_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwin define <8 x i16> @trunc_mul_v8i32_v8i16_zext_8i8(<16 x i8> %a0, <8 x i32> %a1) { ; SSE-LABEL: trunc_mul_v8i32_v8i16_zext_8i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: pxor %xmm3, %xmm3 ; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3],xmm0[4],xmm3[4],xmm0[5],xmm3[5],xmm0[6],xmm3[6],xmm0[7],xmm3[7] ; SSE-NEXT: pslld $16, %xmm2 @@ -2271,7 +2271,7 @@ define <8 x i16> @trunc_mul_v8i32_v8i16_zext_8i8(<16 x i8> %a0, <8 x i32> %a1) { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_mul_v8i32_v8i16_zext_8i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; AVX1-NEXT: vpshufb %xmm3, %xmm2, %xmm2 @@ -2283,7 +2283,7 @@ define <8 x i16> @trunc_mul_v8i32_v8i16_zext_8i8(<16 x i8> %a0, <8 x i32> %a1) { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_mul_v8i32_v8i16_zext_8i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; AVX2-NEXT: vpshufb {{.*#+}} ymm1 = ymm1[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3] @@ -2292,7 +2292,7 @@ define <8 x i16> @trunc_mul_v8i32_v8i16_zext_8i8(<16 x i8> %a0, <8 x i32> %a1) { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_mul_v8i32_v8i16_zext_8i8: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> ; AVX512-NEXT: vpmovdw %zmm1, %ymm1 ; AVX512-NEXT: vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero @@ -2312,7 +2312,7 @@ define <8 x i16> @trunc_mul_v8i32_v8i16_zext_8i8(<16 x i8> %a0, <8 x i32> %a1) { define <4 x i32> @trunc_mul_const_v4i64_v4i32(<4 x i64> %a0) nounwind { ; SSE-LABEL: trunc_mul_const_v4i64_v4i32: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movdqa {{.*#+}} xmm2 = [2,3] ; SSE-NEXT: movdqa %xmm1, %xmm3 ; SSE-NEXT: pmuludq %xmm2, %xmm3 @@ -2333,7 +2333,7 @@ define <4 x i32> @trunc_mul_const_v4i64_v4i32(<4 x i64> %a0) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_mul_const_v4i64_v4i32: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0 @@ -2341,7 +2341,7 @@ define <4 x i32> @trunc_mul_const_v4i64_v4i32(<4 x i64> %a0) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_mul_const_v4i64_v4i32: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] ; AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0 @@ -2349,7 +2349,7 @@ define <4 x i32> @trunc_mul_const_v4i64_v4i32(<4 x i64> %a0) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_mul_const_v4i64_v4i32: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512-NEXT: vpmovqd %zmm0, %ymm0 ; AVX512-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0 @@ -2362,7 +2362,7 @@ define <4 x i32> @trunc_mul_const_v4i64_v4i32(<4 x i64> %a0) nounwind { define <8 x i16> @trunc_mul_const_v8i64_v8i16(<8 x i64> %a0) nounwind { ; SSE-LABEL: trunc_mul_const_v8i64_v8i16: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7] ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] @@ -2378,7 +2378,7 @@ define <8 x i16> @trunc_mul_const_v8i64_v8i16(<8 x i64> %a0) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_mul_const_v8i64_v8i16: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3 ; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0],xmm3[1,2,3],xmm2[4],xmm3[5,6,7] @@ -2394,7 +2394,7 @@ define <8 x i16> @trunc_mul_const_v8i64_v8i16(<8 x i64> %a0) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_mul_const_v8i64_v8i16: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] ; AVX2-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7] @@ -2407,7 +2407,7 @@ define <8 x i16> @trunc_mul_const_v8i64_v8i16(<8 x i64> %a0) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_mul_const_v8i64_v8i16: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpmovqw %zmm0, %xmm0 ; AVX512-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0 ; AVX512-NEXT: vzeroupper @@ -2419,7 +2419,7 @@ define <8 x i16> @trunc_mul_const_v8i64_v8i16(<8 x i64> %a0) nounwind { define <8 x i16> @trunc_mul_const_v8i32_v8i16(<8 x i32> %a0) nounwind { ; SSE-LABEL: trunc_mul_const_v8i32_v8i16: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: pslld $16, %xmm1 ; SSE-NEXT: psrad $16, %xmm1 ; SSE-NEXT: pslld $16, %xmm0 @@ -2429,7 +2429,7 @@ define <8 x i16> @trunc_mul_const_v8i32_v8i16(<8 x i32> %a0) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_mul_const_v8i32_v8i16: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 @@ -2440,7 +2440,7 @@ define <8 x i16> @trunc_mul_const_v8i32_v8i16(<8 x i32> %a0) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_mul_const_v8i32_v8i16: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] ; AVX2-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0 @@ -2448,7 +2448,7 @@ define <8 x i16> @trunc_mul_const_v8i32_v8i16(<8 x i32> %a0) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_mul_const_v8i32_v8i16: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512-NEXT: vpmovdw %zmm0, %ymm0 ; AVX512-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0 @@ -2461,7 +2461,7 @@ define <8 x i16> @trunc_mul_const_v8i32_v8i16(<8 x i32> %a0) nounwind { define <16 x i8> @trunc_mul_const_v16i64_v16i8(<16 x i64> %a0) nounwind { ; SSE-LABEL: trunc_mul_const_v16i64_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movl $1, %eax ; SSE-NEXT: movq %rax, %xmm8 ; SSE-NEXT: pslldq {{.*#+}} xmm8 = zero,zero,zero,zero,zero,zero,zero,zero,xmm8[0,1,2,3,4,5,6,7] @@ -2539,7 +2539,7 @@ define <16 x i8> @trunc_mul_const_v16i64_v16i8(<16 x i64> %a0) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_mul_const_v16i64_v16i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: movl $1, %eax ; AVX1-NEXT: vmovq %rax, %xmm4 ; AVX1-NEXT: vpslldq {{.*#+}} xmm4 = zero,zero,zero,zero,zero,zero,zero,zero,xmm4[0,1,2,3,4,5,6,7] @@ -2614,7 +2614,7 @@ define <16 x i8> @trunc_mul_const_v16i64_v16i8(<16 x i64> %a0) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_mul_const_v16i64_v16i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[0,2,2,3,4,6,6,7] ; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,2,2,3] ; AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm2, %xmm2 @@ -2642,7 +2642,7 @@ define <16 x i8> @trunc_mul_const_v16i64_v16i8(<16 x i64> %a0) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_mul_const_v16i64_v16i8: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpmovqd %zmm0, %ymm0 ; AVX512-NEXT: vpmulld {{.*}}(%rip), %ymm0, %ymm0 ; AVX512-NEXT: vpmovqd %zmm1, %ymm1 @@ -2658,7 +2658,7 @@ define <16 x i8> @trunc_mul_const_v16i64_v16i8(<16 x i64> %a0) nounwind { define <16 x i8> @trunc_mul_const_v16i32_v16i8(<16 x i32> %a0) nounwind { ; SSE-LABEL: trunc_mul_const_v16i32_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movdqa {{.*#+}} xmm4 = [0,1,2,3] ; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm0[1,1,3,3] ; SSE-NEXT: pmuludq %xmm4, %xmm0 @@ -2702,7 +2702,7 @@ define <16 x i8> @trunc_mul_const_v16i32_v16i8(<16 x i32> %a0) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_mul_const_v16i32_v16i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0 @@ -2721,7 +2721,7 @@ define <16 x i8> @trunc_mul_const_v16i32_v16i8(<16 x i32> %a0) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_mul_const_v16i32_v16i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpshufb %ymm2, %ymm1, %ymm1 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3] @@ -2737,7 +2737,7 @@ define <16 x i8> @trunc_mul_const_v16i32_v16i8(<16 x i32> %a0) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_mul_const_v16i32_v16i8: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpmulld {{.*}}(%rip), %zmm0, %zmm0 ; AVX512-NEXT: vpmovdb %zmm0, %xmm0 ; AVX512-NEXT: vzeroupper @@ -2749,7 +2749,7 @@ define <16 x i8> @trunc_mul_const_v16i32_v16i8(<16 x i32> %a0) nounwind { define <16 x i8> @trunc_mul_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; SSE-LABEL: trunc_mul_const_v16i16_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: pmullw {{.*}}(%rip), %xmm0 ; SSE-NEXT: pmullw {{.*}}(%rip), %xmm1 ; SSE-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255] @@ -2759,7 +2759,7 @@ define <16 x i8> @trunc_mul_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_mul_const_v16i16_v16i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0 @@ -2771,7 +2771,7 @@ define <16 x i8> @trunc_mul_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_mul_const_v16i16_v16i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u> @@ -2782,7 +2782,7 @@ define <16 x i8> @trunc_mul_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; AVX2-NEXT: retq ; ; AVX512F-LABEL: trunc_mul_const_v16i16_v16i8: -; AVX512F: # BB#0: +; AVX512F: # %bb.0: ; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0 ; AVX512F-NEXT: vpmovsxwd %ymm0, %zmm0 ; AVX512F-NEXT: vpmovdb %zmm0, %xmm0 @@ -2790,7 +2790,7 @@ define <16 x i8> @trunc_mul_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; AVX512F-NEXT: retq ; ; AVX512BW-LABEL: trunc_mul_const_v16i16_v16i8: -; AVX512BW: # BB#0: +; AVX512BW: # %bb.0: ; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0 ; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> @@ -2798,7 +2798,7 @@ define <16 x i8> @trunc_mul_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; AVX512BW-NEXT: retq ; ; AVX512DQ-LABEL: trunc_mul_const_v16i16_v16i8: -; AVX512DQ: # BB#0: +; AVX512DQ: # %bb.0: ; AVX512DQ-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0 ; AVX512DQ-NEXT: vpmovsxwd %ymm0, %zmm0 ; AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0 @@ -2815,14 +2815,14 @@ define <16 x i8> @trunc_mul_const_v16i16_v16i8(<16 x i16> %a0) nounwind { define <4 x i32> @trunc_and_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; SSE-LABEL: trunc_and_v4i64_v4i32: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: andps %xmm3, %xmm1 ; SSE-NEXT: andps %xmm2, %xmm0 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_and_v4i64_v4i32: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] @@ -2830,7 +2830,7 @@ define <4 x i32> @trunc_and_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_and_v4i64_v4i32: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vandps %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7] ; AVX2-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,2,3] @@ -2839,7 +2839,7 @@ define <4 x i32> @trunc_and_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_and_v4i64_v4i32: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0 ; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> @@ -2852,7 +2852,7 @@ define <4 x i32> @trunc_and_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { define <8 x i16> @trunc_and_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; SSE-LABEL: trunc_and_v8i64_v8i16: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: pand %xmm6, %xmm2 ; SSE-NEXT: pand %xmm7, %xmm3 ; SSE-NEXT: pand %xmm4, %xmm0 @@ -2871,7 +2871,7 @@ define <8 x i16> @trunc_and_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_and_v8i64_v8i16: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vandps %ymm2, %ymm0, %ymm0 ; AVX1-NEXT: vandps %ymm3, %ymm1, %ymm1 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 @@ -2888,7 +2888,7 @@ define <8 x i16> @trunc_and_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_and_v8i64_v8i16: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpand %ymm3, %ymm1, %ymm1 ; AVX2-NEXT: vpand %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7] @@ -2903,7 +2903,7 @@ define <8 x i16> @trunc_and_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_and_v8i64_v8i16: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpandq %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpmovqw %zmm0, %xmm0 ; AVX512-NEXT: vzeroupper @@ -2915,7 +2915,7 @@ define <8 x i16> @trunc_and_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { define <8 x i16> @trunc_and_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; SSE-LABEL: trunc_and_v8i32_v8i16: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: pand %xmm3, %xmm1 ; SSE-NEXT: pslld $16, %xmm1 ; SSE-NEXT: psrad $16, %xmm1 @@ -2926,7 +2926,7 @@ define <8 x i16> @trunc_and_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_and_v8i32_v8i16: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] @@ -2937,7 +2937,7 @@ define <8 x i16> @trunc_and_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_and_v8i32_v8i16: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] @@ -2946,7 +2946,7 @@ define <8 x i16> @trunc_and_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_and_v8i32_v8i16: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vpmovdw %zmm0, %ymm0 ; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> @@ -2959,7 +2959,7 @@ define <8 x i16> @trunc_and_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { define <16 x i8> @trunc_and_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwind { ; SSE-LABEL: trunc_and_v16i64_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: pand {{[0-9]+}}(%rsp), %xmm0 ; SSE-NEXT: pand {{[0-9]+}}(%rsp), %xmm1 ; SSE-NEXT: pand {{[0-9]+}}(%rsp), %xmm2 @@ -2987,7 +2987,7 @@ define <16 x i8> @trunc_and_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwin ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_and_v16i64_v16i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vandps %ymm4, %ymm0, %ymm0 ; AVX1-NEXT: vandps %ymm5, %ymm1, %ymm1 ; AVX1-NEXT: vandps %ymm6, %ymm2, %ymm2 @@ -3016,7 +3016,7 @@ define <16 x i8> @trunc_and_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwin ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_and_v16i64_v16i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpand %ymm5, %ymm1, %ymm1 ; AVX2-NEXT: vpand %ymm4, %ymm0, %ymm0 ; AVX2-NEXT: vpand %ymm7, %ymm3, %ymm3 @@ -3044,7 +3044,7 @@ define <16 x i8> @trunc_and_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwin ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_and_v16i64_v16i8: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpandq %zmm3, %zmm1, %zmm1 ; AVX512-NEXT: vpandq %zmm2, %zmm0, %zmm0 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0 @@ -3060,7 +3060,7 @@ define <16 x i8> @trunc_and_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwin define <16 x i8> @trunc_and_v16i32_v16i8(<16 x i32> %a0, <16 x i32> %a1) nounwind { ; SSE-LABEL: trunc_and_v16i32_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movdqa {{.*#+}} xmm8 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0] ; SSE-NEXT: pand %xmm8, %xmm7 ; SSE-NEXT: pand %xmm3, %xmm7 @@ -3076,7 +3076,7 @@ define <16 x i8> @trunc_and_v16i32_v16i8(<16 x i32> %a0, <16 x i32> %a1) nounwin ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_and_v16i32_v16i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vandps %ymm2, %ymm0, %ymm0 ; AVX1-NEXT: vandps %ymm3, %ymm1, %ymm1 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 @@ -3093,7 +3093,7 @@ define <16 x i8> @trunc_and_v16i32_v16i8(<16 x i32> %a0, <16 x i32> %a1) nounwin ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_and_v16i32_v16i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpand %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpand %ymm3, %ymm1, %ymm1 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] @@ -3109,7 +3109,7 @@ define <16 x i8> @trunc_and_v16i32_v16i8(<16 x i32> %a0, <16 x i32> %a1) nounwin ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_and_v16i32_v16i8: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpandq %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpmovdb %zmm0, %xmm0 ; AVX512-NEXT: vzeroupper @@ -3121,7 +3121,7 @@ define <16 x i8> @trunc_and_v16i32_v16i8(<16 x i32> %a0, <16 x i32> %a1) nounwin define <16 x i8> @trunc_and_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwind { ; SSE-LABEL: trunc_and_v16i16_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movdqa {{.*#+}} xmm4 = [255,255,255,255,255,255,255,255] ; SSE-NEXT: pand %xmm4, %xmm3 ; SSE-NEXT: pand %xmm1, %xmm3 @@ -3131,7 +3131,7 @@ define <16 x i8> @trunc_and_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwin ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_and_v16i16_v16i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u> @@ -3142,7 +3142,7 @@ define <16 x i8> @trunc_and_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwin ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_and_v16i16_v16i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u> @@ -3153,7 +3153,7 @@ define <16 x i8> @trunc_and_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwin ; AVX2-NEXT: retq ; ; AVX512F-LABEL: trunc_and_v16i16_v16i8: -; AVX512F: # BB#0: +; AVX512F: # %bb.0: ; AVX512F-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX512F-NEXT: vpmovsxwd %ymm0, %zmm0 ; AVX512F-NEXT: vpmovdb %zmm0, %xmm0 @@ -3161,7 +3161,7 @@ define <16 x i8> @trunc_and_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwin ; AVX512F-NEXT: retq ; ; AVX512BW-LABEL: trunc_and_v16i16_v16i8: -; AVX512BW: # BB#0: +; AVX512BW: # %bb.0: ; AVX512BW-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0 ; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> @@ -3169,7 +3169,7 @@ define <16 x i8> @trunc_and_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwin ; AVX512BW-NEXT: retq ; ; AVX512DQ-LABEL: trunc_and_v16i16_v16i8: -; AVX512DQ: # BB#0: +; AVX512DQ: # %bb.0: ; AVX512DQ-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX512DQ-NEXT: vpmovsxwd %ymm0, %zmm0 ; AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0 @@ -3186,13 +3186,13 @@ define <16 x i8> @trunc_and_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwin define <4 x i32> @trunc_and_const_v4i64_v4i32(<4 x i64> %a0) nounwind { ; SSE-LABEL: trunc_and_const_v4i64_v4i32: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; SSE-NEXT: andps {{.*}}(%rip), %xmm0 ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_and_const_v4i64_v4i32: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; AVX1-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 @@ -3200,7 +3200,7 @@ define <4 x i32> @trunc_and_const_v4i64_v4i32(<4 x i64> %a0) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_and_const_v4i64_v4i32: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7] ; AVX2-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,2,3] ; AVX2-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 @@ -3208,7 +3208,7 @@ define <4 x i32> @trunc_and_const_v4i64_v4i32(<4 x i64> %a0) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_and_const_v4i64_v4i32: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512-NEXT: vpmovqd %zmm0, %ymm0 ; AVX512-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 @@ -3221,7 +3221,7 @@ define <4 x i32> @trunc_and_const_v4i64_v4i32(<4 x i64> %a0) nounwind { define <8 x i16> @trunc_and_const_v8i64_v8i16(<8 x i64> %a0) nounwind { ; SSE-LABEL: trunc_and_const_v8i64_v8i16: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7] ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] @@ -3237,7 +3237,7 @@ define <8 x i16> @trunc_and_const_v8i64_v8i16(<8 x i64> %a0) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_and_const_v8i64_v8i16: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3 ; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0],xmm3[1,2,3],xmm2[4],xmm3[5,6,7] @@ -3253,7 +3253,7 @@ define <8 x i16> @trunc_and_const_v8i64_v8i16(<8 x i64> %a0) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_and_const_v8i64_v8i16: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] ; AVX2-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7] @@ -3266,7 +3266,7 @@ define <8 x i16> @trunc_and_const_v8i64_v8i16(<8 x i64> %a0) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_and_const_v8i64_v8i16: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpmovqw %zmm0, %xmm0 ; AVX512-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; AVX512-NEXT: vzeroupper @@ -3278,7 +3278,7 @@ define <8 x i16> @trunc_and_const_v8i64_v8i16(<8 x i64> %a0) nounwind { define <8 x i16> @trunc_and_const_v8i32_v8i16(<8 x i32> %a0) nounwind { ; SSE-LABEL: trunc_and_const_v8i32_v8i16: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: pslld $16, %xmm1 ; SSE-NEXT: psrad $16, %xmm1 ; SSE-NEXT: pslld $16, %xmm0 @@ -3288,7 +3288,7 @@ define <8 x i16> @trunc_and_const_v8i32_v8i16(<8 x i32> %a0) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_and_const_v8i32_v8i16: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 @@ -3299,7 +3299,7 @@ define <8 x i16> @trunc_and_const_v8i32_v8i16(<8 x i32> %a0) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_and_const_v8i32_v8i16: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] ; AVX2-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 @@ -3307,7 +3307,7 @@ define <8 x i16> @trunc_and_const_v8i32_v8i16(<8 x i32> %a0) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_and_const_v8i32_v8i16: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512-NEXT: vpmovdw %zmm0, %ymm0 ; AVX512-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 @@ -3320,7 +3320,7 @@ define <8 x i16> @trunc_and_const_v8i32_v8i16(<8 x i32> %a0) nounwind { define <16 x i8> @trunc_and_const_v16i64_v16i8(<16 x i64> %a0) nounwind { ; SSE-LABEL: trunc_and_const_v16i64_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movdqa {{.*#+}} xmm8 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0] ; SSE-NEXT: pand %xmm8, %xmm7 ; SSE-NEXT: pand %xmm8, %xmm6 @@ -3341,7 +3341,7 @@ define <16 x i8> @trunc_and_const_v16i64_v16i8(<16 x i64> %a0) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_and_const_v16i64_v16i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm4 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm5 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0] ; AVX1-NEXT: vpand %xmm5, %xmm4, %xmm4 @@ -3367,7 +3367,7 @@ define <16 x i8> @trunc_and_const_v16i64_v16i8(<16 x i64> %a0) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_and_const_v16i64_v16i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[0,2,2,3,4,6,6,7] ; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,2,2,3] ; AVX2-NEXT: vpshufd {{.*#+}} ymm3 = ymm3[0,2,2,3,4,6,6,7] @@ -3392,7 +3392,7 @@ define <16 x i8> @trunc_and_const_v16i64_v16i8(<16 x i64> %a0) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_and_const_v16i64_v16i8: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpmovqd %zmm0, %ymm0 ; AVX512-NEXT: vpmovqd %zmm1, %ymm1 ; AVX512-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0 @@ -3407,7 +3407,7 @@ define <16 x i8> @trunc_and_const_v16i64_v16i8(<16 x i64> %a0) nounwind { define <16 x i8> @trunc_and_const_v16i32_v16i8(<16 x i32> %a0) nounwind { ; SSE-LABEL: trunc_and_const_v16i32_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movdqa {{.*#+}} xmm4 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0] ; SSE-NEXT: pand %xmm4, %xmm3 ; SSE-NEXT: pand %xmm4, %xmm2 @@ -3420,7 +3420,7 @@ define <16 x i8> @trunc_and_const_v16i32_v16i8(<16 x i32> %a0) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_and_const_v16i32_v16i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0] ; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2 @@ -3436,7 +3436,7 @@ define <16 x i8> @trunc_and_const_v16i32_v16i8(<16 x i32> %a0) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_and_const_v16i32_v16i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpshufb %ymm2, %ymm1, %ymm1 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3] @@ -3451,7 +3451,7 @@ define <16 x i8> @trunc_and_const_v16i32_v16i8(<16 x i32> %a0) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_and_const_v16i32_v16i8: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpmovdb %zmm0, %xmm0 ; AVX512-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; AVX512-NEXT: vzeroupper @@ -3463,7 +3463,7 @@ define <16 x i8> @trunc_and_const_v16i32_v16i8(<16 x i32> %a0) nounwind { define <16 x i8> @trunc_and_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; SSE-LABEL: trunc_and_const_v16i16_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255] ; SSE-NEXT: pand %xmm2, %xmm1 ; SSE-NEXT: pand %xmm2, %xmm0 @@ -3472,7 +3472,7 @@ define <16 x i8> @trunc_and_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_and_const_v16i16_v16i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u> ; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 @@ -3483,7 +3483,7 @@ define <16 x i8> @trunc_and_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_and_const_v16i16_v16i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u> ; AVX2-NEXT: vpshufb %xmm2, %xmm1, %xmm1 @@ -3494,7 +3494,7 @@ define <16 x i8> @trunc_and_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; AVX2-NEXT: retq ; ; AVX512F-LABEL: trunc_and_const_v16i16_v16i8: -; AVX512F: # BB#0: +; AVX512F: # %bb.0: ; AVX512F-NEXT: vpmovsxwd %ymm0, %zmm0 ; AVX512F-NEXT: vpmovdb %zmm0, %xmm0 ; AVX512F-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 @@ -3502,7 +3502,7 @@ define <16 x i8> @trunc_and_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; AVX512F-NEXT: retq ; ; AVX512BW-LABEL: trunc_and_const_v16i16_v16i8: -; AVX512BW: # BB#0: +; AVX512BW: # %bb.0: ; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0 ; AVX512BW-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 @@ -3510,7 +3510,7 @@ define <16 x i8> @trunc_and_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; AVX512BW-NEXT: retq ; ; AVX512DQ-LABEL: trunc_and_const_v16i16_v16i8: -; AVX512DQ: # BB#0: +; AVX512DQ: # %bb.0: ; AVX512DQ-NEXT: vpmovsxwd %ymm0, %zmm0 ; AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0 ; AVX512DQ-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 @@ -3527,14 +3527,14 @@ define <16 x i8> @trunc_and_const_v16i16_v16i8(<16 x i16> %a0) nounwind { define <4 x i32> @trunc_xor_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; SSE-LABEL: trunc_xor_v4i64_v4i32: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: xorps %xmm3, %xmm1 ; SSE-NEXT: xorps %xmm2, %xmm0 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_xor_v4i64_v4i32: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vxorps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] @@ -3542,7 +3542,7 @@ define <4 x i32> @trunc_xor_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_xor_v4i64_v4i32: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vxorps %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7] ; AVX2-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,2,3] @@ -3551,7 +3551,7 @@ define <4 x i32> @trunc_xor_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_xor_v4i64_v4i32: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0 ; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> @@ -3564,7 +3564,7 @@ define <4 x i32> @trunc_xor_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { define <8 x i16> @trunc_xor_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; SSE-LABEL: trunc_xor_v8i64_v8i16: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: pxor %xmm6, %xmm2 ; SSE-NEXT: pxor %xmm7, %xmm3 ; SSE-NEXT: pxor %xmm4, %xmm0 @@ -3583,7 +3583,7 @@ define <8 x i16> @trunc_xor_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_xor_v8i64_v8i16: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vxorps %ymm2, %ymm0, %ymm0 ; AVX1-NEXT: vxorps %ymm3, %ymm1, %ymm1 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 @@ -3600,7 +3600,7 @@ define <8 x i16> @trunc_xor_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_xor_v8i64_v8i16: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpxor %ymm3, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7] @@ -3615,7 +3615,7 @@ define <8 x i16> @trunc_xor_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_xor_v8i64_v8i16: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpxorq %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpmovqw %zmm0, %xmm0 ; AVX512-NEXT: vzeroupper @@ -3627,7 +3627,7 @@ define <8 x i16> @trunc_xor_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { define <8 x i16> @trunc_xor_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; SSE-LABEL: trunc_xor_v8i32_v8i16: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: pxor %xmm3, %xmm1 ; SSE-NEXT: pslld $16, %xmm1 ; SSE-NEXT: psrad $16, %xmm1 @@ -3638,7 +3638,7 @@ define <8 x i16> @trunc_xor_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_xor_v8i32_v8i16: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vxorps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] @@ -3649,7 +3649,7 @@ define <8 x i16> @trunc_xor_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_xor_v8i32_v8i16: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] @@ -3658,7 +3658,7 @@ define <8 x i16> @trunc_xor_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_xor_v8i32_v8i16: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vpmovdw %zmm0, %ymm0 ; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> @@ -3671,7 +3671,7 @@ define <8 x i16> @trunc_xor_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { define <16 x i8> @trunc_xor_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwind { ; SSE-LABEL: trunc_xor_v16i64_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: pxor {{[0-9]+}}(%rsp), %xmm0 ; SSE-NEXT: pxor {{[0-9]+}}(%rsp), %xmm1 ; SSE-NEXT: pxor {{[0-9]+}}(%rsp), %xmm2 @@ -3699,7 +3699,7 @@ define <16 x i8> @trunc_xor_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwin ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_xor_v16i64_v16i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vxorps %ymm4, %ymm0, %ymm0 ; AVX1-NEXT: vxorps %ymm5, %ymm1, %ymm1 ; AVX1-NEXT: vxorps %ymm6, %ymm2, %ymm2 @@ -3728,7 +3728,7 @@ define <16 x i8> @trunc_xor_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwin ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_xor_v16i64_v16i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpxor %ymm5, %ymm1, %ymm1 ; AVX2-NEXT: vpxor %ymm4, %ymm0, %ymm0 ; AVX2-NEXT: vpxor %ymm7, %ymm3, %ymm3 @@ -3756,7 +3756,7 @@ define <16 x i8> @trunc_xor_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwin ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_xor_v16i64_v16i8: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpxorq %zmm3, %zmm1, %zmm1 ; AVX512-NEXT: vpxorq %zmm2, %zmm0, %zmm0 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0 @@ -3772,7 +3772,7 @@ define <16 x i8> @trunc_xor_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwin define <16 x i8> @trunc_xor_v16i32_v16i8(<16 x i32> %a0, <16 x i32> %a1) nounwind { ; SSE-LABEL: trunc_xor_v16i32_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: pxor %xmm4, %xmm0 ; SSE-NEXT: pxor %xmm5, %xmm1 ; SSE-NEXT: pxor %xmm6, %xmm2 @@ -3788,7 +3788,7 @@ define <16 x i8> @trunc_xor_v16i32_v16i8(<16 x i32> %a0, <16 x i32> %a1) nounwin ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_xor_v16i32_v16i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vxorps %ymm2, %ymm0, %ymm0 ; AVX1-NEXT: vxorps %ymm3, %ymm1, %ymm1 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 @@ -3805,7 +3805,7 @@ define <16 x i8> @trunc_xor_v16i32_v16i8(<16 x i32> %a0, <16 x i32> %a1) nounwin ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_xor_v16i32_v16i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpxor %ymm3, %ymm1, %ymm1 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] @@ -3821,7 +3821,7 @@ define <16 x i8> @trunc_xor_v16i32_v16i8(<16 x i32> %a0, <16 x i32> %a1) nounwin ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_xor_v16i32_v16i8: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpxorq %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpmovdb %zmm0, %xmm0 ; AVX512-NEXT: vzeroupper @@ -3833,7 +3833,7 @@ define <16 x i8> @trunc_xor_v16i32_v16i8(<16 x i32> %a0, <16 x i32> %a1) nounwin define <16 x i8> @trunc_xor_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwind { ; SSE-LABEL: trunc_xor_v16i16_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: pxor %xmm2, %xmm0 ; SSE-NEXT: pxor %xmm3, %xmm1 ; SSE-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255] @@ -3843,7 +3843,7 @@ define <16 x i8> @trunc_xor_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwin ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_xor_v16i16_v16i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vxorps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u> @@ -3854,7 +3854,7 @@ define <16 x i8> @trunc_xor_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwin ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_xor_v16i16_v16i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u> @@ -3865,7 +3865,7 @@ define <16 x i8> @trunc_xor_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwin ; AVX2-NEXT: retq ; ; AVX512F-LABEL: trunc_xor_v16i16_v16i8: -; AVX512F: # BB#0: +; AVX512F: # %bb.0: ; AVX512F-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; AVX512F-NEXT: vpmovsxwd %ymm0, %zmm0 ; AVX512F-NEXT: vpmovdb %zmm0, %xmm0 @@ -3873,7 +3873,7 @@ define <16 x i8> @trunc_xor_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwin ; AVX512F-NEXT: retq ; ; AVX512BW-LABEL: trunc_xor_v16i16_v16i8: -; AVX512BW: # BB#0: +; AVX512BW: # %bb.0: ; AVX512BW-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0 ; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> @@ -3881,7 +3881,7 @@ define <16 x i8> @trunc_xor_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwin ; AVX512BW-NEXT: retq ; ; AVX512DQ-LABEL: trunc_xor_v16i16_v16i8: -; AVX512DQ: # BB#0: +; AVX512DQ: # %bb.0: ; AVX512DQ-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; AVX512DQ-NEXT: vpmovsxwd %ymm0, %zmm0 ; AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0 @@ -3898,13 +3898,13 @@ define <16 x i8> @trunc_xor_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwin define <4 x i32> @trunc_xor_const_v4i64_v4i32(<4 x i64> %a0) nounwind { ; SSE-LABEL: trunc_xor_const_v4i64_v4i32: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; SSE-NEXT: xorps {{.*}}(%rip), %xmm0 ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_xor_const_v4i64_v4i32: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; AVX1-NEXT: vxorps {{.*}}(%rip), %xmm0, %xmm0 @@ -3912,7 +3912,7 @@ define <4 x i32> @trunc_xor_const_v4i64_v4i32(<4 x i64> %a0) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_xor_const_v4i64_v4i32: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7] ; AVX2-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,2,3] ; AVX2-NEXT: vxorps {{.*}}(%rip), %xmm0, %xmm0 @@ -3920,7 +3920,7 @@ define <4 x i32> @trunc_xor_const_v4i64_v4i32(<4 x i64> %a0) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_xor_const_v4i64_v4i32: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512-NEXT: vpmovqd %zmm0, %ymm0 ; AVX512-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0 @@ -3933,7 +3933,7 @@ define <4 x i32> @trunc_xor_const_v4i64_v4i32(<4 x i64> %a0) nounwind { define <8 x i16> @trunc_xor_const_v8i64_v8i16(<8 x i64> %a0) nounwind { ; SSE-LABEL: trunc_xor_const_v8i64_v8i16: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7] ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] @@ -3949,7 +3949,7 @@ define <8 x i16> @trunc_xor_const_v8i64_v8i16(<8 x i64> %a0) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_xor_const_v8i64_v8i16: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3 ; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0],xmm3[1,2,3],xmm2[4],xmm3[5,6,7] @@ -3965,7 +3965,7 @@ define <8 x i16> @trunc_xor_const_v8i64_v8i16(<8 x i64> %a0) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_xor_const_v8i64_v8i16: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] ; AVX2-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7] @@ -3978,7 +3978,7 @@ define <8 x i16> @trunc_xor_const_v8i64_v8i16(<8 x i64> %a0) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_xor_const_v8i64_v8i16: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpmovqw %zmm0, %xmm0 ; AVX512-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0 ; AVX512-NEXT: vzeroupper @@ -3990,7 +3990,7 @@ define <8 x i16> @trunc_xor_const_v8i64_v8i16(<8 x i64> %a0) nounwind { define <8 x i16> @trunc_xor_const_v8i32_v8i16(<8 x i32> %a0) nounwind { ; SSE-LABEL: trunc_xor_const_v8i32_v8i16: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: pslld $16, %xmm1 ; SSE-NEXT: psrad $16, %xmm1 ; SSE-NEXT: pslld $16, %xmm0 @@ -4000,7 +4000,7 @@ define <8 x i16> @trunc_xor_const_v8i32_v8i16(<8 x i32> %a0) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_xor_const_v8i32_v8i16: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 @@ -4011,7 +4011,7 @@ define <8 x i16> @trunc_xor_const_v8i32_v8i16(<8 x i32> %a0) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_xor_const_v8i32_v8i16: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] ; AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0 @@ -4019,7 +4019,7 @@ define <8 x i16> @trunc_xor_const_v8i32_v8i16(<8 x i32> %a0) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_xor_const_v8i32_v8i16: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512-NEXT: vpmovdw %zmm0, %ymm0 ; AVX512-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0 @@ -4032,7 +4032,7 @@ define <8 x i16> @trunc_xor_const_v8i32_v8i16(<8 x i32> %a0) nounwind { define <16 x i8> @trunc_xor_const_v16i64_v16i8(<16 x i64> %a0) nounwind { ; SSE-LABEL: trunc_xor_const_v16i64_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movdqa {{.*#+}} xmm8 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0] ; SSE-NEXT: pand %xmm8, %xmm7 ; SSE-NEXT: pand %xmm8, %xmm6 @@ -4053,7 +4053,7 @@ define <16 x i8> @trunc_xor_const_v16i64_v16i8(<16 x i64> %a0) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_xor_const_v16i64_v16i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm4 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm5 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0] ; AVX1-NEXT: vpand %xmm5, %xmm4, %xmm4 @@ -4079,7 +4079,7 @@ define <16 x i8> @trunc_xor_const_v16i64_v16i8(<16 x i64> %a0) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_xor_const_v16i64_v16i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[0,2,2,3,4,6,6,7] ; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,2,2,3] ; AVX2-NEXT: vpshufd {{.*#+}} ymm3 = ymm3[0,2,2,3,4,6,6,7] @@ -4104,7 +4104,7 @@ define <16 x i8> @trunc_xor_const_v16i64_v16i8(<16 x i64> %a0) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_xor_const_v16i64_v16i8: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpmovqd %zmm0, %ymm0 ; AVX512-NEXT: vpmovqd %zmm1, %ymm1 ; AVX512-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0 @@ -4119,7 +4119,7 @@ define <16 x i8> @trunc_xor_const_v16i64_v16i8(<16 x i64> %a0) nounwind { define <16 x i8> @trunc_xor_const_v16i32_v16i8(<16 x i32> %a0) nounwind { ; SSE-LABEL: trunc_xor_const_v16i32_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movdqa {{.*#+}} xmm4 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0] ; SSE-NEXT: pand %xmm4, %xmm3 ; SSE-NEXT: pand %xmm4, %xmm2 @@ -4132,7 +4132,7 @@ define <16 x i8> @trunc_xor_const_v16i32_v16i8(<16 x i32> %a0) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_xor_const_v16i32_v16i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0] ; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2 @@ -4148,7 +4148,7 @@ define <16 x i8> @trunc_xor_const_v16i32_v16i8(<16 x i32> %a0) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_xor_const_v16i32_v16i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpshufb %ymm2, %ymm1, %ymm1 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3] @@ -4163,7 +4163,7 @@ define <16 x i8> @trunc_xor_const_v16i32_v16i8(<16 x i32> %a0) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_xor_const_v16i32_v16i8: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpmovdb %zmm0, %xmm0 ; AVX512-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0 ; AVX512-NEXT: vzeroupper @@ -4175,7 +4175,7 @@ define <16 x i8> @trunc_xor_const_v16i32_v16i8(<16 x i32> %a0) nounwind { define <16 x i8> @trunc_xor_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; SSE-LABEL: trunc_xor_const_v16i16_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255] ; SSE-NEXT: pand %xmm2, %xmm1 ; SSE-NEXT: pand %xmm2, %xmm0 @@ -4184,7 +4184,7 @@ define <16 x i8> @trunc_xor_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_xor_const_v16i16_v16i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u> ; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 @@ -4195,7 +4195,7 @@ define <16 x i8> @trunc_xor_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_xor_const_v16i16_v16i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u> ; AVX2-NEXT: vpshufb %xmm2, %xmm1, %xmm1 @@ -4206,7 +4206,7 @@ define <16 x i8> @trunc_xor_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; AVX2-NEXT: retq ; ; AVX512F-LABEL: trunc_xor_const_v16i16_v16i8: -; AVX512F: # BB#0: +; AVX512F: # %bb.0: ; AVX512F-NEXT: vpmovsxwd %ymm0, %zmm0 ; AVX512F-NEXT: vpmovdb %zmm0, %xmm0 ; AVX512F-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0 @@ -4214,7 +4214,7 @@ define <16 x i8> @trunc_xor_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; AVX512F-NEXT: retq ; ; AVX512BW-LABEL: trunc_xor_const_v16i16_v16i8: -; AVX512BW: # BB#0: +; AVX512BW: # %bb.0: ; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0 ; AVX512BW-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0 @@ -4222,7 +4222,7 @@ define <16 x i8> @trunc_xor_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; AVX512BW-NEXT: retq ; ; AVX512DQ-LABEL: trunc_xor_const_v16i16_v16i8: -; AVX512DQ: # BB#0: +; AVX512DQ: # %bb.0: ; AVX512DQ-NEXT: vpmovsxwd %ymm0, %zmm0 ; AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0 ; AVX512DQ-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0 @@ -4239,14 +4239,14 @@ define <16 x i8> @trunc_xor_const_v16i16_v16i8(<16 x i16> %a0) nounwind { define <4 x i32> @trunc_or_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; SSE-LABEL: trunc_or_v4i64_v4i32: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: orps %xmm3, %xmm1 ; SSE-NEXT: orps %xmm2, %xmm0 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_or_v4i64_v4i32: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] @@ -4254,7 +4254,7 @@ define <4 x i32> @trunc_or_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_or_v4i64_v4i32: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vorps %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7] ; AVX2-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,2,3] @@ -4263,7 +4263,7 @@ define <4 x i32> @trunc_or_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_or_v4i64_v4i32: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0 ; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> @@ -4276,7 +4276,7 @@ define <4 x i32> @trunc_or_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { define <8 x i16> @trunc_or_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; SSE-LABEL: trunc_or_v8i64_v8i16: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: por %xmm6, %xmm2 ; SSE-NEXT: por %xmm7, %xmm3 ; SSE-NEXT: por %xmm4, %xmm0 @@ -4295,7 +4295,7 @@ define <8 x i16> @trunc_or_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_or_v8i64_v8i16: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vorps %ymm2, %ymm0, %ymm0 ; AVX1-NEXT: vorps %ymm3, %ymm1, %ymm1 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 @@ -4312,7 +4312,7 @@ define <8 x i16> @trunc_or_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_or_v8i64_v8i16: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpor %ymm3, %ymm1, %ymm1 ; AVX2-NEXT: vpor %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7] @@ -4327,7 +4327,7 @@ define <8 x i16> @trunc_or_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_or_v8i64_v8i16: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vporq %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpmovqw %zmm0, %xmm0 ; AVX512-NEXT: vzeroupper @@ -4339,7 +4339,7 @@ define <8 x i16> @trunc_or_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { define <8 x i16> @trunc_or_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; SSE-LABEL: trunc_or_v8i32_v8i16: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: por %xmm3, %xmm1 ; SSE-NEXT: pslld $16, %xmm1 ; SSE-NEXT: psrad $16, %xmm1 @@ -4350,7 +4350,7 @@ define <8 x i16> @trunc_or_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_or_v8i32_v8i16: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] @@ -4361,7 +4361,7 @@ define <8 x i16> @trunc_or_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_or_v8i32_v8i16: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] @@ -4370,7 +4370,7 @@ define <8 x i16> @trunc_or_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_or_v8i32_v8i16: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vpmovdw %zmm0, %ymm0 ; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> @@ -4383,7 +4383,7 @@ define <8 x i16> @trunc_or_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { define <16 x i8> @trunc_or_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwind { ; SSE-LABEL: trunc_or_v16i64_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: por {{[0-9]+}}(%rsp), %xmm0 ; SSE-NEXT: por {{[0-9]+}}(%rsp), %xmm1 ; SSE-NEXT: por {{[0-9]+}}(%rsp), %xmm2 @@ -4411,7 +4411,7 @@ define <16 x i8> @trunc_or_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwind ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_or_v16i64_v16i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vorps %ymm4, %ymm0, %ymm0 ; AVX1-NEXT: vorps %ymm5, %ymm1, %ymm1 ; AVX1-NEXT: vorps %ymm6, %ymm2, %ymm2 @@ -4440,7 +4440,7 @@ define <16 x i8> @trunc_or_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwind ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_or_v16i64_v16i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpor %ymm5, %ymm1, %ymm1 ; AVX2-NEXT: vpor %ymm4, %ymm0, %ymm0 ; AVX2-NEXT: vpor %ymm7, %ymm3, %ymm3 @@ -4468,7 +4468,7 @@ define <16 x i8> @trunc_or_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwind ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_or_v16i64_v16i8: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vporq %zmm3, %zmm1, %zmm1 ; AVX512-NEXT: vporq %zmm2, %zmm0, %zmm0 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0 @@ -4484,7 +4484,7 @@ define <16 x i8> @trunc_or_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwind define <16 x i8> @trunc_or_v16i32_v16i8(<16 x i32> %a0, <16 x i32> %a1) nounwind { ; SSE-LABEL: trunc_or_v16i32_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: por %xmm4, %xmm0 ; SSE-NEXT: por %xmm5, %xmm1 ; SSE-NEXT: por %xmm6, %xmm2 @@ -4500,7 +4500,7 @@ define <16 x i8> @trunc_or_v16i32_v16i8(<16 x i32> %a0, <16 x i32> %a1) nounwind ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_or_v16i32_v16i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vorps %ymm2, %ymm0, %ymm0 ; AVX1-NEXT: vorps %ymm3, %ymm1, %ymm1 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 @@ -4517,7 +4517,7 @@ define <16 x i8> @trunc_or_v16i32_v16i8(<16 x i32> %a0, <16 x i32> %a1) nounwind ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_or_v16i32_v16i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpor %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpor %ymm3, %ymm1, %ymm1 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] @@ -4533,7 +4533,7 @@ define <16 x i8> @trunc_or_v16i32_v16i8(<16 x i32> %a0, <16 x i32> %a1) nounwind ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_or_v16i32_v16i8: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vporq %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpmovdb %zmm0, %xmm0 ; AVX512-NEXT: vzeroupper @@ -4545,7 +4545,7 @@ define <16 x i8> @trunc_or_v16i32_v16i8(<16 x i32> %a0, <16 x i32> %a1) nounwind define <16 x i8> @trunc_or_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwind { ; SSE-LABEL: trunc_or_v16i16_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: por %xmm2, %xmm0 ; SSE-NEXT: por %xmm3, %xmm1 ; SSE-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255] @@ -4555,7 +4555,7 @@ define <16 x i8> @trunc_or_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwind ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_or_v16i16_v16i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u> @@ -4566,7 +4566,7 @@ define <16 x i8> @trunc_or_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwind ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_or_v16i16_v16i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u> @@ -4577,7 +4577,7 @@ define <16 x i8> @trunc_or_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwind ; AVX2-NEXT: retq ; ; AVX512F-LABEL: trunc_or_v16i16_v16i8: -; AVX512F: # BB#0: +; AVX512F: # %bb.0: ; AVX512F-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX512F-NEXT: vpmovsxwd %ymm0, %zmm0 ; AVX512F-NEXT: vpmovdb %zmm0, %xmm0 @@ -4585,7 +4585,7 @@ define <16 x i8> @trunc_or_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwind ; AVX512F-NEXT: retq ; ; AVX512BW-LABEL: trunc_or_v16i16_v16i8: -; AVX512BW: # BB#0: +; AVX512BW: # %bb.0: ; AVX512BW-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0 ; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> @@ -4593,7 +4593,7 @@ define <16 x i8> @trunc_or_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwind ; AVX512BW-NEXT: retq ; ; AVX512DQ-LABEL: trunc_or_v16i16_v16i8: -; AVX512DQ: # BB#0: +; AVX512DQ: # %bb.0: ; AVX512DQ-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX512DQ-NEXT: vpmovsxwd %ymm0, %zmm0 ; AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0 @@ -4610,13 +4610,13 @@ define <16 x i8> @trunc_or_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwind define <4 x i32> @trunc_or_const_v4i64_v4i32(<4 x i64> %a0) nounwind { ; SSE-LABEL: trunc_or_const_v4i64_v4i32: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; SSE-NEXT: orps {{.*}}(%rip), %xmm0 ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_or_const_v4i64_v4i32: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; AVX1-NEXT: vorps {{.*}}(%rip), %xmm0, %xmm0 @@ -4624,7 +4624,7 @@ define <4 x i32> @trunc_or_const_v4i64_v4i32(<4 x i64> %a0) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_or_const_v4i64_v4i32: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7] ; AVX2-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,2,3] ; AVX2-NEXT: vorps {{.*}}(%rip), %xmm0, %xmm0 @@ -4632,7 +4632,7 @@ define <4 x i32> @trunc_or_const_v4i64_v4i32(<4 x i64> %a0) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_or_const_v4i64_v4i32: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512-NEXT: vpmovqd %zmm0, %ymm0 ; AVX512-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0 @@ -4645,7 +4645,7 @@ define <4 x i32> @trunc_or_const_v4i64_v4i32(<4 x i64> %a0) nounwind { define <8 x i16> @trunc_or_const_v8i64_v8i16(<8 x i64> %a0) nounwind { ; SSE-LABEL: trunc_or_const_v8i64_v8i16: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7] ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] @@ -4661,7 +4661,7 @@ define <8 x i16> @trunc_or_const_v8i64_v8i16(<8 x i64> %a0) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_or_const_v8i64_v8i16: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3 ; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0],xmm3[1,2,3],xmm2[4],xmm3[5,6,7] @@ -4677,7 +4677,7 @@ define <8 x i16> @trunc_or_const_v8i64_v8i16(<8 x i64> %a0) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_or_const_v8i64_v8i16: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] ; AVX2-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7] @@ -4690,7 +4690,7 @@ define <8 x i16> @trunc_or_const_v8i64_v8i16(<8 x i64> %a0) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_or_const_v8i64_v8i16: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpmovqw %zmm0, %xmm0 ; AVX512-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0 ; AVX512-NEXT: vzeroupper @@ -4702,7 +4702,7 @@ define <8 x i16> @trunc_or_const_v8i64_v8i16(<8 x i64> %a0) nounwind { define <8 x i16> @trunc_or_const_v8i32_v8i16(<8 x i32> %a0) nounwind { ; SSE-LABEL: trunc_or_const_v8i32_v8i16: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: pslld $16, %xmm1 ; SSE-NEXT: psrad $16, %xmm1 ; SSE-NEXT: pslld $16, %xmm0 @@ -4712,7 +4712,7 @@ define <8 x i16> @trunc_or_const_v8i32_v8i16(<8 x i32> %a0) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_or_const_v8i32_v8i16: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 @@ -4723,7 +4723,7 @@ define <8 x i16> @trunc_or_const_v8i32_v8i16(<8 x i32> %a0) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_or_const_v8i32_v8i16: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] ; AVX2-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0 @@ -4731,7 +4731,7 @@ define <8 x i16> @trunc_or_const_v8i32_v8i16(<8 x i32> %a0) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_or_const_v8i32_v8i16: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512-NEXT: vpmovdw %zmm0, %ymm0 ; AVX512-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0 @@ -4744,7 +4744,7 @@ define <8 x i16> @trunc_or_const_v8i32_v8i16(<8 x i32> %a0) nounwind { define <16 x i8> @trunc_or_const_v16i64_v16i8(<16 x i64> %a0) nounwind { ; SSE-LABEL: trunc_or_const_v16i64_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movdqa {{.*#+}} xmm8 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0] ; SSE-NEXT: pand %xmm8, %xmm7 ; SSE-NEXT: pand %xmm8, %xmm6 @@ -4765,7 +4765,7 @@ define <16 x i8> @trunc_or_const_v16i64_v16i8(<16 x i64> %a0) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_or_const_v16i64_v16i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm4 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm5 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0] ; AVX1-NEXT: vpand %xmm5, %xmm4, %xmm4 @@ -4791,7 +4791,7 @@ define <16 x i8> @trunc_or_const_v16i64_v16i8(<16 x i64> %a0) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_or_const_v16i64_v16i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[0,2,2,3,4,6,6,7] ; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,2,2,3] ; AVX2-NEXT: vpshufd {{.*#+}} ymm3 = ymm3[0,2,2,3,4,6,6,7] @@ -4816,7 +4816,7 @@ define <16 x i8> @trunc_or_const_v16i64_v16i8(<16 x i64> %a0) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_or_const_v16i64_v16i8: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpmovqd %zmm0, %ymm0 ; AVX512-NEXT: vpmovqd %zmm1, %ymm1 ; AVX512-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0 @@ -4831,7 +4831,7 @@ define <16 x i8> @trunc_or_const_v16i64_v16i8(<16 x i64> %a0) nounwind { define <16 x i8> @trunc_or_const_v16i32_v16i8(<16 x i32> %a0) nounwind { ; SSE-LABEL: trunc_or_const_v16i32_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movdqa {{.*#+}} xmm4 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0] ; SSE-NEXT: pand %xmm4, %xmm3 ; SSE-NEXT: pand %xmm4, %xmm2 @@ -4844,7 +4844,7 @@ define <16 x i8> @trunc_or_const_v16i32_v16i8(<16 x i32> %a0) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_or_const_v16i32_v16i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0] ; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2 @@ -4860,7 +4860,7 @@ define <16 x i8> @trunc_or_const_v16i32_v16i8(<16 x i32> %a0) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_or_const_v16i32_v16i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpshufb %ymm2, %ymm1, %ymm1 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3] @@ -4875,7 +4875,7 @@ define <16 x i8> @trunc_or_const_v16i32_v16i8(<16 x i32> %a0) nounwind { ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_or_const_v16i32_v16i8: -; AVX512: # BB#0: +; AVX512: # %bb.0: ; AVX512-NEXT: vpmovdb %zmm0, %xmm0 ; AVX512-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0 ; AVX512-NEXT: vzeroupper @@ -4887,7 +4887,7 @@ define <16 x i8> @trunc_or_const_v16i32_v16i8(<16 x i32> %a0) nounwind { define <16 x i8> @trunc_or_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; SSE-LABEL: trunc_or_const_v16i16_v16i8: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255] ; SSE-NEXT: pand %xmm2, %xmm1 ; SSE-NEXT: pand %xmm2, %xmm0 @@ -4896,7 +4896,7 @@ define <16 x i8> @trunc_or_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; SSE-NEXT: retq ; ; AVX1-LABEL: trunc_or_const_v16i16_v16i8: -; AVX1: # BB#0: +; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u> ; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 @@ -4907,7 +4907,7 @@ define <16 x i8> @trunc_or_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_or_const_v16i16_v16i8: -; AVX2: # BB#0: +; AVX2: # %bb.0: ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u> ; AVX2-NEXT: vpshufb %xmm2, %xmm1, %xmm1 @@ -4918,7 +4918,7 @@ define <16 x i8> @trunc_or_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; AVX2-NEXT: retq ; ; AVX512F-LABEL: trunc_or_const_v16i16_v16i8: -; AVX512F: # BB#0: +; AVX512F: # %bb.0: ; AVX512F-NEXT: vpmovsxwd %ymm0, %zmm0 ; AVX512F-NEXT: vpmovdb %zmm0, %xmm0 ; AVX512F-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0 @@ -4926,7 +4926,7 @@ define <16 x i8> @trunc_or_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; AVX512F-NEXT: retq ; ; AVX512BW-LABEL: trunc_or_const_v16i16_v16i8: -; AVX512BW: # BB#0: +; AVX512BW: # %bb.0: ; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0 ; AVX512BW-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0 @@ -4934,7 +4934,7 @@ define <16 x i8> @trunc_or_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; AVX512BW-NEXT: retq ; ; AVX512DQ-LABEL: trunc_or_const_v16i16_v16i8: -; AVX512DQ: # BB#0: +; AVX512DQ: # %bb.0: ; AVX512DQ-NEXT: vpmovsxwd %ymm0, %zmm0 ; AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0 ; AVX512DQ-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0 @@ -4951,7 +4951,7 @@ define <16 x i8> @trunc_or_const_v16i16_v16i8(<16 x i16> %a0) nounwind { define <4 x i32> @mul_add_const_v4i64_v4i32(<4 x i32> %a0, <4 x i32> %a1) nounwind { ; SSE-LABEL: mul_add_const_v4i64_v4i32: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm0, %xmm2 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,1,1,3] ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,1,3,3] @@ -4982,7 +4982,7 @@ define <4 x i32> @mul_add_const_v4i64_v4i32(<4 x i32> %a0, <4 x i32> %a1) nounwi ; SSE-NEXT: retq ; ; AVX-LABEL: mul_add_const_v4i64_v4i32: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vpmulld %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: retq @@ -4996,7 +4996,7 @@ define <4 x i32> @mul_add_const_v4i64_v4i32(<4 x i32> %a0, <4 x i32> %a1) nounwi define <4 x i32> @mul_add_self_v4i64_v4i32(<4 x i32> %a0, <4 x i32> %a1) nounwind { ; SSE-LABEL: mul_add_self_v4i64_v4i32: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1] ; SSE-NEXT: movdqa %xmm2, %xmm3 ; SSE-NEXT: psrad $31, %xmm3 @@ -5037,7 +5037,7 @@ define <4 x i32> @mul_add_self_v4i64_v4i32(<4 x i32> %a0, <4 x i32> %a1) nounwin ; SSE-NEXT: retq ; ; AVX-LABEL: mul_add_self_v4i64_v4i32: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vpmulld %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpaddd %xmm0, %xmm0, %xmm0 ; AVX-NEXT: retq @@ -5051,7 +5051,7 @@ define <4 x i32> @mul_add_self_v4i64_v4i32(<4 x i32> %a0, <4 x i32> %a1) nounwin define <4 x i32> @mul_add_multiuse_v4i64_v4i32(<4 x i32> %a0, <4 x i32> %a1) nounwind { ; SSE-LABEL: mul_add_multiuse_v4i64_v4i32: -; SSE: # BB#0: +; SSE: # %bb.0: ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,1,1,3] ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm1[0,1,1,3] @@ -5081,7 +5081,7 @@ define <4 x i32> @mul_add_multiuse_v4i64_v4i32(<4 x i32> %a0, <4 x i32> %a1) nou ; SSE-NEXT: retq ; ; AVX-LABEL: mul_add_multiuse_v4i64_v4i32: -; AVX: # BB#0: +; AVX: # %bb.0: ; AVX-NEXT: vpmulld %xmm1, %xmm0, %xmm1 ; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: retq |
