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-rw-r--r--llvm/test/CodeGen/X86/vector-shift-shl-256.ll120
1 files changed, 120 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/vector-shift-shl-256.ll b/llvm/test/CodeGen/X86/vector-shift-shl-256.ll
index 980cb971f90..3daf24f1a82 100644
--- a/llvm/test/CodeGen/X86/vector-shift-shl-256.ll
+++ b/llvm/test/CodeGen/X86/vector-shift-shl-256.ll
@@ -3,6 +3,7 @@
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+xop,+avx | FileCheck %s --check-prefix=ALL --check-prefix=XOP --check-prefix=XOPAVX1
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+xop,+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=XOP --check-prefix=XOPAVX2
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl -mattr=+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=AVX512BW
;
; Variable Shifts
@@ -42,6 +43,11 @@ define <4 x i64> @var_shift_v4i64(<4 x i64> %a, <4 x i64> %b) nounwind {
; XOPAVX2: # BB#0:
; XOPAVX2-NEXT: vpsllvq %ymm1, %ymm0, %ymm0
; XOPAVX2-NEXT: retq
+;
+; AVX512-LABEL: var_shift_v4i64:
+; AVX512: ## BB#0:
+; AVX512-NEXT: vpsllvq %ymm1, %ymm0, %ymm0
+; AVX512-NEXT: retq
%shift = shl <4 x i64> %a, %b
ret <4 x i64> %shift
}
@@ -81,6 +87,11 @@ define <8 x i32> @var_shift_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind {
; XOPAVX2: # BB#0:
; XOPAVX2-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
; XOPAVX2-NEXT: retq
+;
+; AVX512-LABEL: var_shift_v8i32:
+; AVX512: ## BB#0:
+; AVX512-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
+; AVX512-NEXT: retq
%shift = shl <8 x i32> %a, %b
ret <8 x i32> %shift
}
@@ -152,6 +163,11 @@ define <16 x i16> @var_shift_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind {
; XOPAVX2-NEXT: vpshlw %xmm1, %xmm0, %xmm0
; XOPAVX2-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
; XOPAVX2-NEXT: retq
+;
+; AVX512-LABEL: var_shift_v16i16:
+; AVX512: ## BB#0:
+; AVX512-NEXT: vpsllvw %zmm1, %zmm0, %zmm0
+; AVX512-NEXT: retq
%shift = shl <16 x i16> %a, %b
ret <16 x i16> %shift
}
@@ -220,6 +236,21 @@ define <32 x i8> @var_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind {
; XOPAVX2-NEXT: vpshlb %xmm1, %xmm0, %xmm0
; XOPAVX2-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
; XOPAVX2-NEXT: retq
+;
+; AVX512-LABEL: var_shift_v32i8:
+; AVX512: ## BB#0:
+; AVX512-NEXT: vpsllw $5, %ymm1, %ymm1
+; AVX512-NEXT: vpsllw $4, %ymm0, %ymm2
+; AVX512-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2
+; AVX512-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
+; AVX512-NEXT: vpsllw $2, %ymm0, %ymm2
+; AVX512-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2
+; AVX512-NEXT: vpaddb %ymm1, %ymm1, %ymm1
+; AVX512-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
+; AVX512-NEXT: vpaddb %ymm0, %ymm0, %ymm2
+; AVX512-NEXT: vpaddb %ymm1, %ymm1, %ymm1
+; AVX512-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
+; AVX512-NEXT: retq
%shift = shl <32 x i8> %a, %b
ret <32 x i8> %shift
}
@@ -254,6 +285,11 @@ define <4 x i64> @splatvar_shift_v4i64(<4 x i64> %a, <4 x i64> %b) nounwind {
; XOPAVX2: # BB#0:
; XOPAVX2-NEXT: vpsllq %xmm1, %ymm0, %ymm0
; XOPAVX2-NEXT: retq
+;
+; AVX512-LABEL: splatvar_shift_v4i64:
+; AVX512: ## BB#0:
+; AVX512-NEXT: vpsllq %xmm1, %ymm0, %ymm0
+; AVX512-NEXT: retq
%splat = shufflevector <4 x i64> %b, <4 x i64> undef, <4 x i32> zeroinitializer
%shift = shl <4 x i64> %a, %splat
ret <4 x i64> %shift
@@ -293,6 +329,13 @@ define <8 x i32> @splatvar_shift_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind {
; XOPAVX2-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
; XOPAVX2-NEXT: vpslld %xmm1, %ymm0, %ymm0
; XOPAVX2-NEXT: retq
+;
+; AVX512-LABEL: splatvar_shift_v8i32:
+; AVX512: ## BB#0:
+; AVX512-NEXT: vxorps %xmm2, %xmm2, %xmm2
+; AVX512-NEXT: vmovss %xmm1, %xmm2, %xmm1
+; AVX512-NEXT: vpslld %xmm1, %ymm0, %ymm0
+; AVX512-NEXT: retq
%splat = shufflevector <8 x i32> %b, <8 x i32> undef, <8 x i32> zeroinitializer
%shift = shl <8 x i32> %a, %splat
ret <8 x i32> %shift
@@ -336,6 +379,14 @@ define <16 x i16> @splatvar_shift_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind
; XOPAVX2-NEXT: vmovd %eax, %xmm1
; XOPAVX2-NEXT: vpsllw %xmm1, %ymm0, %ymm0
; XOPAVX2-NEXT: retq
+;
+; AVX512-LABEL: splatvar_shift_v16i16:
+; AVX512: ## BB#0:
+; AVX512-NEXT: vmovd %xmm1, %eax
+; AVX512-NEXT: movzwl %ax, %eax
+; AVX512-NEXT: vmovd %eax, %xmm1
+; AVX512-NEXT: vpsllw %xmm1, %ymm0, %ymm0
+; AVX512-NEXT: retq
%splat = shufflevector <16 x i16> %b, <16 x i16> undef, <16 x i32> zeroinitializer
%shift = shl <16 x i16> %a, %splat
ret <16 x i16> %shift
@@ -406,6 +457,22 @@ define <32 x i8> @splatvar_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind {
; XOPAVX2-NEXT: vpshlb %xmm1, %xmm0, %xmm0
; XOPAVX2-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
; XOPAVX2-NEXT: retq
+;
+; AVX512-LABEL: splatvar_shift_v32i8:
+; AVX512: ## BB#0:
+; AVX512-NEXT: vpbroadcastb %xmm1, %ymm1
+; AVX512-NEXT: vpsllw $4, %ymm0, %ymm2
+; AVX512-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2
+; AVX512-NEXT: vpsllw $5, %ymm1, %ymm1
+; AVX512-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
+; AVX512-NEXT: vpsllw $2, %ymm0, %ymm2
+; AVX512-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2
+; AVX512-NEXT: vpaddb %ymm1, %ymm1, %ymm1
+; AVX512-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
+; AVX512-NEXT: vpaddb %ymm0, %ymm0, %ymm2
+; AVX512-NEXT: vpaddb %ymm1, %ymm1, %ymm1
+; AVX512-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
+; AVX512-NEXT: retq
%splat = shufflevector <32 x i8> %b, <32 x i8> undef, <32 x i32> zeroinitializer
%shift = shl <32 x i8> %a, %splat
ret <32 x i8> %shift
@@ -445,6 +512,11 @@ define <4 x i64> @constant_shift_v4i64(<4 x i64> %a) nounwind {
; XOPAVX2: # BB#0:
; XOPAVX2-NEXT: vpsllvq {{.*}}(%rip), %ymm0, %ymm0
; XOPAVX2-NEXT: retq
+;
+; AVX512-LABEL: constant_shift_v4i64:
+; AVX512: ## BB#0:
+; AVX512-NEXT: vpsllvq {{.*}}(%rip), %ymm0, %ymm0
+; AVX512-NEXT: retq
%shift = shl <4 x i64> %a, <i64 1, i64 7, i64 31, i64 62>
ret <4 x i64> %shift
}
@@ -475,6 +547,11 @@ define <8 x i32> @constant_shift_v8i32(<8 x i32> %a) nounwind {
; XOPAVX2: # BB#0:
; XOPAVX2-NEXT: vpsllvd {{.*}}(%rip), %ymm0, %ymm0
; XOPAVX2-NEXT: retq
+;
+; AVX512-LABEL: constant_shift_v8i32:
+; AVX512: ## BB#0:
+; AVX512-NEXT: vpsllvd {{.*}}(%rip), %ymm0, %ymm0
+; AVX512-NEXT: retq
%shift = shl <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 8, i32 7>
ret <8 x i32> %shift
}
@@ -505,6 +582,12 @@ define <16 x i16> @constant_shift_v16i16(<16 x i16> %a) nounwind {
; XOPAVX2: # BB#0:
; XOPAVX2-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0
; XOPAVX2-NEXT: retq
+;
+; AVX512-LABEL: constant_shift_v16i16:
+; AVX512: ## BB#0:
+; AVX512-NEXT: vmovdqa {{.*#+}} ymm1 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15]
+; AVX512-NEXT: vpsllvw %zmm1, %zmm0, %zmm0
+; AVX512-NEXT: retq
%shift = shl <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
ret <16 x i16> %shift
}
@@ -571,6 +654,22 @@ define <32 x i8> @constant_shift_v32i8(<32 x i8> %a) nounwind {
; XOPAVX2-NEXT: vpshlb %xmm2, %xmm0, %xmm0
; XOPAVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
; XOPAVX2-NEXT: retq
+;
+; AVX512-LABEL: constant_shift_v32i8:
+; AVX512: ## BB#0:
+; AVX512-NEXT: vmovdqa {{.*#+}} ymm1 = [0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0,0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0]
+; AVX512-NEXT: vpsllw $5, %ymm1, %ymm1
+; AVX512-NEXT: vpsllw $4, %ymm0, %ymm2
+; AVX512-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2
+; AVX512-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
+; AVX512-NEXT: vpsllw $2, %ymm0, %ymm2
+; AVX512-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2
+; AVX512-NEXT: vpaddb %ymm1, %ymm1, %ymm1
+; AVX512-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
+; AVX512-NEXT: vpaddb %ymm0, %ymm0, %ymm2
+; AVX512-NEXT: vpaddb %ymm1, %ymm1, %ymm1
+; AVX512-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
+; AVX512-NEXT: retq
%shift = shl <32 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
ret <32 x i8> %shift
}
@@ -605,6 +704,11 @@ define <4 x i64> @splatconstant_shift_v4i64(<4 x i64> %a) nounwind {
; XOPAVX2: # BB#0:
; XOPAVX2-NEXT: vpsllq $7, %ymm0, %ymm0
; XOPAVX2-NEXT: retq
+;
+; AVX512-LABEL: splatconstant_shift_v4i64:
+; AVX512: ## BB#0:
+; AVX512-NEXT: vpsllq $7, %ymm0, %ymm0
+; AVX512-NEXT: retq
%shift = shl <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7>
ret <4 x i64> %shift
}
@@ -635,6 +739,11 @@ define <8 x i32> @splatconstant_shift_v8i32(<8 x i32> %a) nounwind {
; XOPAVX2: # BB#0:
; XOPAVX2-NEXT: vpslld $5, %ymm0, %ymm0
; XOPAVX2-NEXT: retq
+;
+; AVX512-LABEL: splatconstant_shift_v8i32:
+; AVX512: ## BB#0:
+; AVX512-NEXT: vpslld $5, %ymm0, %ymm0
+; AVX512-NEXT: retq
%shift = shl <8 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
ret <8 x i32> %shift
}
@@ -665,6 +774,11 @@ define <16 x i16> @splatconstant_shift_v16i16(<16 x i16> %a) nounwind {
; XOPAVX2: # BB#0:
; XOPAVX2-NEXT: vpsllw $3, %ymm0, %ymm0
; XOPAVX2-NEXT: retq
+;
+; AVX512-LABEL: splatconstant_shift_v16i16:
+; AVX512: ## BB#0:
+; AVX512-NEXT: vpsllw $3, %ymm0, %ymm0
+; AVX512-NEXT: retq
%shift = shl <16 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
ret <16 x i16> %shift
}
@@ -701,6 +815,12 @@ define <32 x i8> @splatconstant_shift_v32i8(<32 x i8> %a) nounwind {
; XOPAVX2-NEXT: vpsllw $3, %ymm0, %ymm0
; XOPAVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
; XOPAVX2-NEXT: retq
+;
+; AVX512-LABEL: splatconstant_shift_v32i8:
+; AVX512: ## BB#0:
+; AVX512-NEXT: vpsllw $3, %ymm0, %ymm0
+; AVX512-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
+; AVX512-NEXT: retq
%shift = shl <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
ret <32 x i8> %shift
}
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