1 files changed, 110 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/X86/tbm_patterns.ll b/llvm/test/CodeGen/X86/tbm_patterns.ll
index f7bfb5bec8c..a1b8a189c93 100644
--- a/llvm/test/CodeGen/X86/tbm_patterns.ll
+++ b/llvm/test/CodeGen/X86/tbm_patterns.ll
@@ -1,8 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+tbm < %s | FileCheck %s
 
-; TODO - Patterns fail to fold with ZF flags and prevents TBM instruction selection.
-
 define i32 @test_x86_tbm_bextri_u32(i32 %a) nounwind {
 ; CHECK-LABEL: test_x86_tbm_bextri_u32:
 ; CHECK:       # %bb.0:
@@ -873,3 +871,113 @@ define  i64 @masked_blcic(i64) {
   %5 = and i64 %4, %3
   ret i64 %5
 }
+
+define i32 @blcic32_branch(i32 %x) nounwind {
+; CHECK-LABEL: blcic32_branch:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pushq %rbx
+; CHECK-NEXT:    movl %edi, %ebx
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    notl %eax
+; CHECK-NEXT:    incl %ebx
+; CHECK-NEXT:    andl %eax, %ebx
+; CHECK-NEXT:    jne .LBB69_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    callq bar
+; CHECK-NEXT:  .LBB69_2:
+; CHECK-NEXT:    movl %ebx, %eax
+; CHECK-NEXT:    popq %rbx
+; CHECK-NEXT:    retq
+  %tmp = xor i32 %x, -1
+  %tmp2 = add i32 %x, 1
+  %tmp3 = and i32 %tmp, %tmp2
+  %cmp = icmp eq i32 %tmp3, 0
+  br i1 %cmp, label %1, label %2
+
+  tail call void @bar()
+  br label %2
+  ret i32 %tmp3
+}
+
+define i64 @blcic64_branch(i64 %x) nounwind {
+; CHECK-LABEL: blcic64_branch:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pushq %rbx
+; CHECK-NEXT:    movq %rdi, %rbx
+; CHECK-NEXT:    movq %rdi, %rax
+; CHECK-NEXT:    notq %rax
+; CHECK-NEXT:    incq %rbx
+; CHECK-NEXT:    andq %rax, %rbx
+; CHECK-NEXT:    jne .LBB70_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    callq bar
+; CHECK-NEXT:  .LBB70_2:
+; CHECK-NEXT:    movq %rbx, %rax
+; CHECK-NEXT:    popq %rbx
+; CHECK-NEXT:    retq
+  %tmp = xor i64 %x, -1
+  %tmp2 = add i64 %x, 1
+  %tmp3 = and i64 %tmp, %tmp2
+  %cmp = icmp eq i64 %tmp3, 0
+  br i1 %cmp, label %1, label %2
+
+  tail call void @bar()
+  br label %2
+  ret i64 %tmp3
+}
+
+define i32 @tzmsk32_branch(i32 %x) nounwind {
+; CHECK-LABEL: tzmsk32_branch:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pushq %rbx
+; CHECK-NEXT:    movl %edi, %ebx
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    notl %eax
+; CHECK-NEXT:    decl %ebx
+; CHECK-NEXT:    andl %eax, %ebx
+; CHECK-NEXT:    jne .LBB71_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    callq bar
+; CHECK-NEXT:  .LBB71_2:
+; CHECK-NEXT:    movl %ebx, %eax
+; CHECK-NEXT:    popq %rbx
+; CHECK-NEXT:    retq
+  %tmp = xor i32 %x, -1
+  %tmp2 = add i32 %x, -1
+  %tmp3 = and i32 %tmp, %tmp2
+  %cmp = icmp eq i32 %tmp3, 0
+  br i1 %cmp, label %1, label %2
+
+  tail call void @bar()
+  br label %2
+  ret i32 %tmp3
+}
+
+define i64 @tzmsk64_branch(i64 %x) nounwind {
+; CHECK-LABEL: tzmsk64_branch:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pushq %rbx
+; CHECK-NEXT:    movq %rdi, %rbx
+; CHECK-NEXT:    movq %rdi, %rax
+; CHECK-NEXT:    notq %rax
+; CHECK-NEXT:    decq %rbx
+; CHECK-NEXT:    andq %rax, %rbx
+; CHECK-NEXT:    jne .LBB72_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    callq bar
+; CHECK-NEXT:  .LBB72_2:
+; CHECK-NEXT:    movq %rbx, %rax
+; CHECK-NEXT:    popq %rbx
+; CHECK-NEXT:    retq
+  %tmp = xor i64 %x, -1
+  %tmp2 = add i64 %x, -1
+  %tmp3 = and i64 %tmp, %tmp2
+  %cmp = icmp eq i64 %tmp3, 0
+  br i1 %cmp, label %1, label %2
+
+  tail call void @bar()
+  br label %2
+  ret i64 %tmp3
+}
+
+declare void @bar()