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Diffstat (limited to 'llvm/test/CodeGen/X86/sse2-vector-shifts.ll')
-rw-r--r--llvm/test/CodeGen/X86/sse2-vector-shifts.ll74
1 files changed, 37 insertions, 37 deletions
diff --git a/llvm/test/CodeGen/X86/sse2-vector-shifts.ll b/llvm/test/CodeGen/X86/sse2-vector-shifts.ll
index c2bb239639a..82d4b7721d9 100644
--- a/llvm/test/CodeGen/X86/sse2-vector-shifts.ll
+++ b/llvm/test/CodeGen/X86/sse2-vector-shifts.ll
@@ -5,7 +5,7 @@
define <8 x i16> @test_sllw_1(<8 x i16> %InVec) {
; CHECK-LABEL: test_sllw_1:
-; CHECK: # BB#0: # %entry
+; CHECK: # %bb.0: # %entry
; CHECK-NEXT: retq
entry:
%shl = shl <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
@@ -14,7 +14,7 @@ entry:
define <8 x i16> @test_sllw_2(<8 x i16> %InVec) {
; CHECK-LABEL: test_sllw_2:
-; CHECK: # BB#0: # %entry
+; CHECK: # %bb.0: # %entry
; CHECK-NEXT: paddw %xmm0, %xmm0
; CHECK-NEXT: retq
entry:
@@ -24,7 +24,7 @@ entry:
define <8 x i16> @test_sllw_3(<8 x i16> %InVec) {
; CHECK-LABEL: test_sllw_3:
-; CHECK: # BB#0: # %entry
+; CHECK: # %bb.0: # %entry
; CHECK-NEXT: psllw $15, %xmm0
; CHECK-NEXT: retq
entry:
@@ -34,7 +34,7 @@ entry:
define <4 x i32> @test_slld_1(<4 x i32> %InVec) {
; CHECK-LABEL: test_slld_1:
-; CHECK: # BB#0: # %entry
+; CHECK: # %bb.0: # %entry
; CHECK-NEXT: retq
entry:
%shl = shl <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
@@ -43,7 +43,7 @@ entry:
define <4 x i32> @test_slld_2(<4 x i32> %InVec) {
; CHECK-LABEL: test_slld_2:
-; CHECK: # BB#0: # %entry
+; CHECK: # %bb.0: # %entry
; CHECK-NEXT: paddd %xmm0, %xmm0
; CHECK-NEXT: retq
entry:
@@ -53,7 +53,7 @@ entry:
define <4 x i32> @test_slld_3(<4 x i32> %InVec) {
; CHECK-LABEL: test_slld_3:
-; CHECK: # BB#0: # %entry
+; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pslld $31, %xmm0
; CHECK-NEXT: retq
entry:
@@ -63,7 +63,7 @@ entry:
define <2 x i64> @test_sllq_1(<2 x i64> %InVec) {
; CHECK-LABEL: test_sllq_1:
-; CHECK: # BB#0: # %entry
+; CHECK: # %bb.0: # %entry
; CHECK-NEXT: retq
entry:
%shl = shl <2 x i64> %InVec, <i64 0, i64 0>
@@ -72,7 +72,7 @@ entry:
define <2 x i64> @test_sllq_2(<2 x i64> %InVec) {
; CHECK-LABEL: test_sllq_2:
-; CHECK: # BB#0: # %entry
+; CHECK: # %bb.0: # %entry
; CHECK-NEXT: paddq %xmm0, %xmm0
; CHECK-NEXT: retq
entry:
@@ -82,7 +82,7 @@ entry:
define <2 x i64> @test_sllq_3(<2 x i64> %InVec) {
; CHECK-LABEL: test_sllq_3:
-; CHECK: # BB#0: # %entry
+; CHECK: # %bb.0: # %entry
; CHECK-NEXT: psllq $63, %xmm0
; CHECK-NEXT: retq
entry:
@@ -94,7 +94,7 @@ entry:
define <8 x i16> @test_sraw_1(<8 x i16> %InVec) {
; CHECK-LABEL: test_sraw_1:
-; CHECK: # BB#0: # %entry
+; CHECK: # %bb.0: # %entry
; CHECK-NEXT: retq
entry:
%shl = ashr <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
@@ -103,7 +103,7 @@ entry:
define <8 x i16> @test_sraw_2(<8 x i16> %InVec) {
; CHECK-LABEL: test_sraw_2:
-; CHECK: # BB#0: # %entry
+; CHECK: # %bb.0: # %entry
; CHECK-NEXT: psraw $1, %xmm0
; CHECK-NEXT: retq
entry:
@@ -113,7 +113,7 @@ entry:
define <8 x i16> @test_sraw_3(<8 x i16> %InVec) {
; CHECK-LABEL: test_sraw_3:
-; CHECK: # BB#0: # %entry
+; CHECK: # %bb.0: # %entry
; CHECK-NEXT: psraw $15, %xmm0
; CHECK-NEXT: retq
entry:
@@ -123,7 +123,7 @@ entry:
define <4 x i32> @test_srad_1(<4 x i32> %InVec) {
; CHECK-LABEL: test_srad_1:
-; CHECK: # BB#0: # %entry
+; CHECK: # %bb.0: # %entry
; CHECK-NEXT: retq
entry:
%shl = ashr <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
@@ -132,7 +132,7 @@ entry:
define <4 x i32> @test_srad_2(<4 x i32> %InVec) {
; CHECK-LABEL: test_srad_2:
-; CHECK: # BB#0: # %entry
+; CHECK: # %bb.0: # %entry
; CHECK-NEXT: psrad $1, %xmm0
; CHECK-NEXT: retq
entry:
@@ -142,7 +142,7 @@ entry:
define <4 x i32> @test_srad_3(<4 x i32> %InVec) {
; CHECK-LABEL: test_srad_3:
-; CHECK: # BB#0: # %entry
+; CHECK: # %bb.0: # %entry
; CHECK-NEXT: psrad $31, %xmm0
; CHECK-NEXT: retq
entry:
@@ -154,7 +154,7 @@ entry:
define <8 x i16> @test_srlw_1(<8 x i16> %InVec) {
; CHECK-LABEL: test_srlw_1:
-; CHECK: # BB#0: # %entry
+; CHECK: # %bb.0: # %entry
; CHECK-NEXT: retq
entry:
%shl = lshr <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
@@ -163,7 +163,7 @@ entry:
define <8 x i16> @test_srlw_2(<8 x i16> %InVec) {
; CHECK-LABEL: test_srlw_2:
-; CHECK: # BB#0: # %entry
+; CHECK: # %bb.0: # %entry
; CHECK-NEXT: psrlw $1, %xmm0
; CHECK-NEXT: retq
entry:
@@ -173,7 +173,7 @@ entry:
define <8 x i16> @test_srlw_3(<8 x i16> %InVec) {
; CHECK-LABEL: test_srlw_3:
-; CHECK: # BB#0: # %entry
+; CHECK: # %bb.0: # %entry
; CHECK-NEXT: psrlw $15, %xmm0
; CHECK-NEXT: retq
entry:
@@ -183,7 +183,7 @@ entry:
define <4 x i32> @test_srld_1(<4 x i32> %InVec) {
; CHECK-LABEL: test_srld_1:
-; CHECK: # BB#0: # %entry
+; CHECK: # %bb.0: # %entry
; CHECK-NEXT: retq
entry:
%shl = lshr <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
@@ -192,7 +192,7 @@ entry:
define <4 x i32> @test_srld_2(<4 x i32> %InVec) {
; CHECK-LABEL: test_srld_2:
-; CHECK: # BB#0: # %entry
+; CHECK: # %bb.0: # %entry
; CHECK-NEXT: psrld $1, %xmm0
; CHECK-NEXT: retq
entry:
@@ -202,7 +202,7 @@ entry:
define <4 x i32> @test_srld_3(<4 x i32> %InVec) {
; CHECK-LABEL: test_srld_3:
-; CHECK: # BB#0: # %entry
+; CHECK: # %bb.0: # %entry
; CHECK-NEXT: psrld $31, %xmm0
; CHECK-NEXT: retq
entry:
@@ -212,7 +212,7 @@ entry:
define <2 x i64> @test_srlq_1(<2 x i64> %InVec) {
; CHECK-LABEL: test_srlq_1:
-; CHECK: # BB#0: # %entry
+; CHECK: # %bb.0: # %entry
; CHECK-NEXT: retq
entry:
%shl = lshr <2 x i64> %InVec, <i64 0, i64 0>
@@ -221,7 +221,7 @@ entry:
define <2 x i64> @test_srlq_2(<2 x i64> %InVec) {
; CHECK-LABEL: test_srlq_2:
-; CHECK: # BB#0: # %entry
+; CHECK: # %bb.0: # %entry
; CHECK-NEXT: psrlq $1, %xmm0
; CHECK-NEXT: retq
entry:
@@ -231,7 +231,7 @@ entry:
define <2 x i64> @test_srlq_3(<2 x i64> %InVec) {
; CHECK-LABEL: test_srlq_3:
-; CHECK: # BB#0: # %entry
+; CHECK: # %bb.0: # %entry
; CHECK-NEXT: psrlq $63, %xmm0
; CHECK-NEXT: retq
entry:
@@ -241,7 +241,7 @@ entry:
define <4 x i32> @sra_sra_v4i32(<4 x i32> %x) nounwind {
; CHECK-LABEL: sra_sra_v4i32:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-NEXT: psrad $6, %xmm0
; CHECK-NEXT: retq
%sra0 = ashr <4 x i32> %x, <i32 2, i32 2, i32 2, i32 2>
@@ -251,7 +251,7 @@ define <4 x i32> @sra_sra_v4i32(<4 x i32> %x) nounwind {
define <4 x i32> @srl_srl_v4i32(<4 x i32> %x) nounwind {
; CHECK-LABEL: srl_srl_v4i32:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-NEXT: psrld $6, %xmm0
; CHECK-NEXT: retq
%srl0 = lshr <4 x i32> %x, <i32 2, i32 2, i32 2, i32 2>
@@ -261,7 +261,7 @@ define <4 x i32> @srl_srl_v4i32(<4 x i32> %x) nounwind {
define <4 x i32> @srl_shl_v4i32(<4 x i32> %x) nounwind {
; CHECK-LABEL: srl_shl_v4i32:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
; CHECK-NEXT: retq
%srl0 = shl <4 x i32> %x, <i32 4, i32 4, i32 4, i32 4>
@@ -271,7 +271,7 @@ define <4 x i32> @srl_shl_v4i32(<4 x i32> %x) nounwind {
define <4 x i32> @srl_sra_31_v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
; CHECK-LABEL: srl_sra_31_v4i32:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-NEXT: psrld $31, %xmm0
; CHECK-NEXT: retq
%sra = ashr <4 x i32> %x, %y
@@ -281,7 +281,7 @@ define <4 x i32> @srl_sra_31_v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
define <4 x i32> @shl_shl_v4i32(<4 x i32> %x) nounwind {
; CHECK-LABEL: shl_shl_v4i32:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-NEXT: pslld $6, %xmm0
; CHECK-NEXT: retq
%shl0 = shl <4 x i32> %x, <i32 2, i32 2, i32 2, i32 2>
@@ -291,7 +291,7 @@ define <4 x i32> @shl_shl_v4i32(<4 x i32> %x) nounwind {
define <4 x i32> @shl_sra_v4i32(<4 x i32> %x) nounwind {
; CHECK-LABEL: shl_sra_v4i32:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
; CHECK-NEXT: retq
%shl0 = ashr <4 x i32> %x, <i32 4, i32 4, i32 4, i32 4>
@@ -301,7 +301,7 @@ define <4 x i32> @shl_sra_v4i32(<4 x i32> %x) nounwind {
define <4 x i32> @shl_srl_v4i32(<4 x i32> %x) nounwind {
; CHECK-LABEL: shl_srl_v4i32:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-NEXT: pslld $3, %xmm0
; CHECK-NEXT: pand {{.*}}(%rip), %xmm0
; CHECK-NEXT: retq
@@ -312,7 +312,7 @@ define <4 x i32> @shl_srl_v4i32(<4 x i32> %x) nounwind {
define <4 x i32> @shl_zext_srl_v4i32(<4 x i16> %x) nounwind {
; CHECK-LABEL: shl_zext_srl_v4i32:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
; CHECK-NEXT: retq
@@ -324,7 +324,7 @@ define <4 x i32> @shl_zext_srl_v4i32(<4 x i16> %x) nounwind {
define <4 x i16> @sra_trunc_srl_v4i32(<4 x i32> %x) nounwind {
; CHECK-LABEL: sra_trunc_srl_v4i32:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-NEXT: psrad $19, %xmm0
; CHECK-NEXT: retq
%srl = lshr <4 x i32> %x, <i32 16, i32 16, i32 16, i32 16>
@@ -335,7 +335,7 @@ define <4 x i16> @sra_trunc_srl_v4i32(<4 x i32> %x) nounwind {
define <4 x i32> @shl_zext_shl_v4i32(<4 x i16> %x) nounwind {
; CHECK-LABEL: shl_zext_shl_v4i32:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-NEXT: pslld $19, %xmm0
; CHECK-NEXT: retq
%shl0 = shl <4 x i16> %x, <i16 2, i16 2, i16 2, i16 2>
@@ -346,7 +346,7 @@ define <4 x i32> @shl_zext_shl_v4i32(<4 x i16> %x) nounwind {
define <4 x i32> @sra_v4i32(<4 x i32> %x) nounwind {
; CHECK-LABEL: sra_v4i32:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-NEXT: psrad $3, %xmm0
; CHECK-NEXT: retq
%sra = ashr <4 x i32> %x, <i32 3, i32 3, i32 3, i32 3>
@@ -355,7 +355,7 @@ define <4 x i32> @sra_v4i32(<4 x i32> %x) nounwind {
define <4 x i32> @srl_v4i32(<4 x i32> %x) nounwind {
; CHECK-LABEL: srl_v4i32:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-NEXT: psrld $3, %xmm0
; CHECK-NEXT: retq
%sra = lshr <4 x i32> %x, <i32 3, i32 3, i32 3, i32 3>
@@ -364,7 +364,7 @@ define <4 x i32> @srl_v4i32(<4 x i32> %x) nounwind {
define <4 x i32> @shl_v4i32(<4 x i32> %x) nounwind {
; CHECK-LABEL: shl_v4i32:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-NEXT: pslld $3, %xmm0
; CHECK-NEXT: retq
%sra = shl <4 x i32> %x, <i32 3, i32 3, i32 3, i32 3>
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