1 files changed, 14 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/rotate-extract-vector.ll b/llvm/test/CodeGen/X86/rotate-extract-vector.ll
index 4959de71172..c439ffc9498 100644
--- a/llvm/test/CodeGen/X86/rotate-extract-vector.ll
+++ b/llvm/test/CodeGen/X86/rotate-extract-vector.ll
@@ -280,3 +280,17 @@ define <2 x i64> @no_extract_udiv(<2 x i64> %i) nounwind {
   %out = or <2 x i64> %lhs_shift, %rhs_div
   ret <2 x i64> %out
 }
+
+; DAGCombiner transforms shl X, 1 into add X, X.
+define <4 x i32> @extract_add_1(<4 x i32> %i) nounwind {
+; CHECK-LABEL: extract_add_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vpaddd %xmm0, %xmm0, %xmm1
+; CHECK-NEXT:    vpsrld $31, %xmm0, %xmm0
+; CHECK-NEXT:    vpor %xmm0, %xmm1, %xmm0
+; CHECK-NEXT:    ret{{[l|q]}}
+  %ii = add <4 x i32> %i, %i
+  %rhs = lshr <4 x i32> %i, <i32 31, i32 31, i32 31, i32 31>
+  %out = or <4 x i32> %ii, %rhs
+  ret <4 x i32> %out
+}