summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen/X86/illegal-bitfield-loadstore.ll
diff options
context:
space:
mode:
Diffstat (limited to 'llvm/test/CodeGen/X86/illegal-bitfield-loadstore.ll')
-rw-r--r--llvm/test/CodeGen/X86/illegal-bitfield-loadstore.ll79
1 files changed, 38 insertions, 41 deletions
diff --git a/llvm/test/CodeGen/X86/illegal-bitfield-loadstore.ll b/llvm/test/CodeGen/X86/illegal-bitfield-loadstore.ll
index df17802fa6d..ceb46571190 100644
--- a/llvm/test/CodeGen/X86/illegal-bitfield-loadstore.ll
+++ b/llvm/test/CodeGen/X86/illegal-bitfield-loadstore.ll
@@ -23,13 +23,12 @@ define void @i24_and_or(i24* %a) {
; CHECK: # BB#0:
; CHECK-NEXT: movzwl (%rdi), %eax
; CHECK-NEXT: movzbl 2(%rdi), %ecx
+; CHECK-NEXT: movb %cl, 2(%rdi)
; CHECK-NEXT: shll $16, %ecx
; CHECK-NEXT: orl %eax, %ecx
; CHECK-NEXT: orl $384, %ecx # imm = 0x180
; CHECK-NEXT: andl $16777088, %ecx # imm = 0xFFFF80
; CHECK-NEXT: movw %cx, (%rdi)
-; CHECK-NEXT: shrl $16, %ecx
-; CHECK-NEXT: movb %cl, 2(%rdi)
; CHECK-NEXT: retq
%b = load i24, i24* %a, align 1
%c = and i24 %b, -128
@@ -44,14 +43,13 @@ define void @i24_insert_bit(i24* %a, i1 zeroext %bit) {
; CHECK-NEXT: movzbl %sil, %eax
; CHECK-NEXT: movzwl (%rdi), %ecx
; CHECK-NEXT: movzbl 2(%rdi), %edx
+; CHECK-NEXT: movb %dl, 2(%rdi)
; CHECK-NEXT: shll $16, %edx
; CHECK-NEXT: orl %ecx, %edx
; CHECK-NEXT: shll $13, %eax
; CHECK-NEXT: andl $16769023, %edx # imm = 0xFFDFFF
-; CHECK-NEXT: orl %edx, %eax
-; CHECK-NEXT: shrl $16, %edx
-; CHECK-NEXT: movb %dl, 2(%rdi)
-; CHECK-NEXT: movw %ax, (%rdi)
+; CHECK-NEXT: orl %eax, %edx
+; CHECK-NEXT: movw %dx, (%rdi)
; CHECK-NEXT: retq
%extbit = zext i1 %bit to i24
%b = load i24, i24* %a, align 1
@@ -65,20 +63,20 @@ define void @i24_insert_bit(i24* %a, i1 zeroext %bit) {
define void @i56_or(i56* %a) {
; CHECK-LABEL: i56_or:
; CHECK: # BB#0:
-; ACHECK-NEXT: movzwl 4(%rdi), %eax
-; ACHECK-NEXT: movzbl 6(%rdi), %ecx
-; ACHECK-NEXT: movl (%rdi), %edx
-; ACHECK-NEXT: movb %cl, 6(%rdi)
-; ACHECK-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<kill> %RCX<def>
-; ACHECK-NEXT: shll $16, %ecx
-; ACHECK-NEXT: orl %eax, %ecx
-; ACHECK-NEXT: shlq $32, %rcx
-; ACHECK-NEXT: orq %rcx, %rdx
-; ACHECK-NEXT: orq $384, %rdx # imm = 0x180
-; ACHECK-NEXT: movl %edx, (%rdi)
-; ACHECK-NEXT: shrq $32, %rdx
-; ACHECK-NEXT: movw %dx, 4(%rdi)
-; ACHECK-NEXT: retq
+; CHECK-NEXT: movzwl 4(%rdi), %eax
+; CHECK-NEXT: movzbl 6(%rdi), %ecx
+; CHECK-NEXT: movl (%rdi), %edx
+; CHECK-NEXT: movb %cl, 6(%rdi)
+; CHECK-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<kill> %RCX<def>
+; CHECK-NEXT: shll $16, %ecx
+; CHECK-NEXT: orl %eax, %ecx
+; CHECK-NEXT: shlq $32, %rcx
+; CHECK-NEXT: orq %rcx, %rdx
+; CHECK-NEXT: orq $384, %rdx # imm = 0x180
+; CHECK-NEXT: movl %edx, (%rdi)
+; CHECK-NEXT: shrq $32, %rdx
+; CHECK-NEXT: movw %dx, 4(%rdi)
+; CHECK-NEXT: retq
%aa = load i56, i56* %a, align 1
%b = or i56 %aa, 384
store i56 %b, i56* %a, align 1
@@ -90,20 +88,19 @@ define void @i56_and_or(i56* %a) {
; CHECK: # BB#0:
; CHECK-NEXT: movzwl 4(%rdi), %eax
; CHECK-NEXT: movzbl 6(%rdi), %ecx
+; CHECK-NEXT: movl (%rdi), %edx
+; CHECK-NEXT: movb %cl, 6(%rdi)
+; CHECK-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<kill> %RCX<def>
; CHECK-NEXT: shll $16, %ecx
; CHECK-NEXT: orl %eax, %ecx
; CHECK-NEXT: shlq $32, %rcx
-; CHECK-NEXT: movl (%rdi), %eax
-; CHECK-NEXT: orq %rcx, %rax
-; CHECK-NEXT: orq $384, %rax # imm = 0x180
-; CHECK-NEXT: movabsq $72057594037927808, %rcx # imm = 0xFFFFFFFFFFFF80
-; CHECK-NEXT: andq %rax, %rcx
-; CHECK-NEXT: movl %ecx, (%rdi)
-; CHECK-NEXT: movq %rcx, %rax
-; CHECK-NEXT: shrq $48, %rax
-; CHECK-NEXT: movb %al, 6(%rdi)
-; CHECK-NEXT: shrq $32, %rcx
-; CHECK-NEXT: movw %cx, 4(%rdi)
+; CHECK-NEXT: orq %rcx, %rdx
+; CHECK-NEXT: orq $384, %rdx # imm = 0x180
+; CHECK-NEXT: movabsq $72057594037927808, %rax # imm = 0xFFFFFFFFFFFF80
+; CHECK-NEXT: andq %rdx, %rax
+; CHECK-NEXT: movl %eax, (%rdi)
+; CHECK-NEXT: shrq $32, %rax
+; CHECK-NEXT: movw %ax, 4(%rdi)
; CHECK-NEXT: retq
%b = load i56, i56* %a, align 1
%c = and i56 %b, -128
@@ -118,20 +115,20 @@ define void @i56_insert_bit(i56* %a, i1 zeroext %bit) {
; CHECK-NEXT: movzbl %sil, %eax
; CHECK-NEXT: movzwl 4(%rdi), %ecx
; CHECK-NEXT: movzbl 6(%rdi), %edx
+; CHECK-NEXT: movl (%rdi), %esi
+; CHECK-NEXT: movb %dl, 6(%rdi)
+; CHECK-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<kill> %RDX<def>
; CHECK-NEXT: shll $16, %edx
; CHECK-NEXT: orl %ecx, %edx
; CHECK-NEXT: shlq $32, %rdx
-; CHECK-NEXT: movl (%rdi), %ecx
-; CHECK-NEXT: orq %rdx, %rcx
+; CHECK-NEXT: orq %rdx, %rsi
; CHECK-NEXT: shlq $13, %rax
-; CHECK-NEXT: movabsq $72057594037919743, %rdx # imm = 0xFFFFFFFFFFDFFF
-; CHECK-NEXT: andq %rcx, %rdx
-; CHECK-NEXT: orq %rdx, %rax
-; CHECK-NEXT: shrq $48, %rdx
-; CHECK-NEXT: movb %dl, 6(%rdi)
-; CHECK-NEXT: movl %eax, (%rdi)
-; CHECK-NEXT: shrq $32, %rax
-; CHECK-NEXT: movw %ax, 4(%rdi)
+; CHECK-NEXT: movabsq $72057594037919743, %rcx # imm = 0xFFFFFFFFFFDFFF
+; CHECK-NEXT: andq %rsi, %rcx
+; CHECK-NEXT: orq %rax, %rcx
+; CHECK-NEXT: movl %ecx, (%rdi)
+; CHECK-NEXT: shrq $32, %rcx
+; CHECK-NEXT: movw %cx, 4(%rdi)
; CHECK-NEXT: retq
%extbit = zext i1 %bit to i56
%b = load i56, i56* %a, align 1
OpenPOWER on IntegriCloud