diff options
Diffstat (limited to 'llvm/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll | 110 |
1 files changed, 55 insertions, 55 deletions
diff --git a/llvm/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll b/llvm/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll index 0bd58b34fa8..e9b568316f6 100644 --- a/llvm/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll +++ b/llvm/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll @@ -6,7 +6,7 @@ define <4 x double> @test_x86_avx_vinsertf128_pd_256_1(<4 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: test_x86_avx_vinsertf128_pd_256_1: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; CHECK-NEXT: ret{{[l|q]}} %res = call <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double> %a0, <2 x double> %a1, i8 1) @@ -16,7 +16,7 @@ declare <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double>, <2 x double> define <8 x float> @test_x86_avx_vinsertf128_ps_256_1(<8 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: test_x86_avx_vinsertf128_ps_256_1: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; CHECK-NEXT: ret{{[l|q]}} %res = call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> %a0, <4 x float> %a1, i8 1) @@ -26,7 +26,7 @@ declare <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float>, <4 x float>, i define <8 x i32> @test_x86_avx_vinsertf128_si_256_1(<8 x i32> %a0, <4 x i32> %a1) { ; CHECK-LABEL: test_x86_avx_vinsertf128_si_256_1: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; CHECK-NEXT: ret{{[l|q]}} %res = call <8 x i32> @llvm.x86.avx.vinsertf128.si.256(<8 x i32> %a0, <4 x i32> %a1, i8 1) @@ -38,7 +38,7 @@ define <8 x i32> @test_x86_avx_vinsertf128_si_256_1(<8 x i32> %a0, <4 x i32> %a1 ; not a vinsertf128 $1. define <8 x i32> @test_x86_avx_vinsertf128_si_256_2(<8 x i32> %a0, <4 x i32> %a1) { ; CHECK-LABEL: test_x86_avx_vinsertf128_si_256_2: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def> ; CHECK-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3] ; CHECK-NEXT: ret{{[l|q]}} @@ -51,7 +51,7 @@ declare <8 x i32> @llvm.x86.avx.vinsertf128.si.256(<8 x i32>, <4 x i32>, i8) nou define <2 x double> @test_x86_avx_vextractf128_pd_256_1(<4 x double> %a0) { ; CHECK-LABEL: test_x86_avx_vextractf128_pd_256_1: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0 ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: ret{{[l|q]}} @@ -62,7 +62,7 @@ declare <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double>, i8) nounwin define <4 x float> @test_x86_avx_vextractf128_ps_256_1(<8 x float> %a0) { ; CHECK-LABEL: test_x86_avx_vextractf128_ps_256_1: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0 ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: ret{{[l|q]}} @@ -73,7 +73,7 @@ declare <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float>, i8) nounwind define <4 x i32> @test_x86_avx_vextractf128_si_256_1(<8 x i32> %a0) { ; CHECK-LABEL: test_x86_avx_vextractf128_si_256_1: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0 ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: ret{{[l|q]}} @@ -87,7 +87,7 @@ declare <4 x i32> @llvm.x86.avx.vextractf128.si.256(<8 x i32>, i8) nounwind read ; not a vextractf128 of any kind. define <2 x double> @test_x86_avx_extractf128_pd_256_2(<4 x double> %a0) { ; CHECK-LABEL: test_x86_avx_extractf128_pd_256_2: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: ret{{[l|q]}} @@ -98,13 +98,13 @@ define <2 x double> @test_x86_avx_extractf128_pd_256_2(<4 x double> %a0) { define <4 x double> @test_x86_avx_vbroadcastf128_pd_256(i8* %a0) { ; X86-LABEL: test_x86_avx_vbroadcastf128_pd_256: -; X86: # BB#0: +; X86: # %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1] ; X86-NEXT: ret{{[l|q]}} ; ; X64-LABEL: test_x86_avx_vbroadcastf128_pd_256: -; X64: # BB#0: +; X64: # %bb.0: ; X64-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1] ; X64-NEXT: ret{{[l|q]}} %res = call <4 x double> @llvm.x86.avx.vbroadcastf128.pd.256(i8* %a0) ; <<4 x double>> [#uses=1] @@ -115,13 +115,13 @@ declare <4 x double> @llvm.x86.avx.vbroadcastf128.pd.256(i8*) nounwind readonly define <8 x float> @test_x86_avx_vbroadcastf128_ps_256(i8* %a0) { ; X86-LABEL: test_x86_avx_vbroadcastf128_ps_256: -; X86: # BB#0: +; X86: # %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1] ; X86-NEXT: ret{{[l|q]}} ; ; X64-LABEL: test_x86_avx_vbroadcastf128_ps_256: -; X64: # BB#0: +; X64: # %bb.0: ; X64-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1] ; X64-NEXT: ret{{[l|q]}} %res = call <8 x float> @llvm.x86.avx.vbroadcastf128.ps.256(i8* %a0) ; <<8 x float>> [#uses=1] @@ -132,7 +132,7 @@ declare <8 x float> @llvm.x86.avx.vbroadcastf128.ps.256(i8*) nounwind readonly define <4 x double> @test_x86_avx_blend_pd_256(<4 x double> %a0, <4 x double> %a1) { ; CHECK-LABEL: test_x86_avx_blend_pd_256: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3] ; CHECK-NEXT: ret{{[l|q]}} %res = call <4 x double> @llvm.x86.avx.blend.pd.256(<4 x double> %a0, <4 x double> %a1, i32 7) ; <<4 x double>> [#uses=1] @@ -143,7 +143,7 @@ declare <4 x double> @llvm.x86.avx.blend.pd.256(<4 x double>, <4 x double>, i32) define <8 x float> @test_x86_avx_blend_ps_256(<8 x float> %a0, <8 x float> %a1) { ; CHECK-LABEL: test_x86_avx_blend_ps_256: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5,6,7] ; CHECK-NEXT: ret{{[l|q]}} %res = call <8 x float> @llvm.x86.avx.blend.ps.256(<8 x float> %a0, <8 x float> %a1, i32 7) ; <<8 x float>> [#uses=1] @@ -154,7 +154,7 @@ declare <8 x float> @llvm.x86.avx.blend.ps.256(<8 x float>, <8 x float>, i32) no define <8 x float> @test_x86_avx_dp_ps_256(<8 x float> %a0, <8 x float> %a1) { ; CHECK-LABEL: test_x86_avx_dp_ps_256: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vdpps $7, %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: ret{{[l|q]}} %res = call <8 x float> @llvm.x86.avx.dp.ps.256(<8 x float> %a0, <8 x float> %a1, i32 7) ; <<8 x float>> [#uses=1] @@ -165,7 +165,7 @@ declare <8 x float> @llvm.x86.avx.dp.ps.256(<8 x float>, <8 x float>, i32) nounw define <2 x i64> @test_x86_sse2_psll_dq(<2 x i64> %a0) { ; CHECK-LABEL: test_x86_sse2_psll_dq: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vpslldq {{.*#+}} xmm0 = zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14] ; CHECK-NEXT: ret{{[l|q]}} %res = call <2 x i64> @llvm.x86.sse2.psll.dq(<2 x i64> %a0, i32 8) ; <<2 x i64>> [#uses=1] @@ -176,7 +176,7 @@ declare <2 x i64> @llvm.x86.sse2.psll.dq(<2 x i64>, i32) nounwind readnone define <2 x i64> @test_x86_sse2_psrl_dq(<2 x i64> %a0) { ; CHECK-LABEL: test_x86_sse2_psrl_dq: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],zero ; CHECK-NEXT: ret{{[l|q]}} %res = call <2 x i64> @llvm.x86.sse2.psrl.dq(<2 x i64> %a0, i32 8) ; <<2 x i64>> [#uses=1] @@ -187,7 +187,7 @@ declare <2 x i64> @llvm.x86.sse2.psrl.dq(<2 x i64>, i32) nounwind readnone define <2 x double> @test_x86_sse41_blendpd(<2 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: test_x86_sse41_blendpd: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1] ; CHECK-NEXT: ret{{[l|q]}} %res = call <2 x double> @llvm.x86.sse41.blendpd(<2 x double> %a0, <2 x double> %a1, i8 2) ; <<2 x double>> [#uses=1] @@ -198,7 +198,7 @@ declare <2 x double> @llvm.x86.sse41.blendpd(<2 x double>, <2 x double>, i8) nou define <4 x float> @test_x86_sse41_blendps(<4 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: test_x86_sse41_blendps: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3] ; CHECK-NEXT: ret{{[l|q]}} %res = call <4 x float> @llvm.x86.sse41.blendps(<4 x float> %a0, <4 x float> %a1, i8 7) ; <<4 x float>> [#uses=1] @@ -209,7 +209,7 @@ declare <4 x float> @llvm.x86.sse41.blendps(<4 x float>, <4 x float>, i8) nounwi define <8 x i16> @test_x86_sse41_pblendw(<8 x i16> %a0, <8 x i16> %a1) { ; CHECK-LABEL: test_x86_sse41_pblendw: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3,4,5,6,7] ; CHECK-NEXT: ret{{[l|q]}} %res = call <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16> %a0, <8 x i16> %a1, i8 7) ; <<8 x i16>> [#uses=1] @@ -220,7 +220,7 @@ declare <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16>, <8 x i16>, i8) nounwind rea define <4 x i32> @test_x86_sse41_pmovsxbd(<16 x i8> %a0) { ; CHECK-LABEL: test_x86_sse41_pmovsxbd: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vpmovsxbd %xmm0, %xmm0 ; CHECK-NEXT: ret{{[l|q]}} %res = call <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8> %a0) ; <<4 x i32>> [#uses=1] @@ -231,7 +231,7 @@ declare <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8>) nounwind readnone define <2 x i64> @test_x86_sse41_pmovsxbq(<16 x i8> %a0) { ; CHECK-LABEL: test_x86_sse41_pmovsxbq: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vpmovsxbq %xmm0, %xmm0 ; CHECK-NEXT: ret{{[l|q]}} %res = call <2 x i64> @llvm.x86.sse41.pmovsxbq(<16 x i8> %a0) ; <<2 x i64>> [#uses=1] @@ -242,7 +242,7 @@ declare <2 x i64> @llvm.x86.sse41.pmovsxbq(<16 x i8>) nounwind readnone define <8 x i16> @test_x86_sse41_pmovsxbw(<16 x i8> %a0) { ; CHECK-LABEL: test_x86_sse41_pmovsxbw: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vpmovsxbw %xmm0, %xmm0 ; CHECK-NEXT: ret{{[l|q]}} %res = call <8 x i16> @llvm.x86.sse41.pmovsxbw(<16 x i8> %a0) ; <<8 x i16>> [#uses=1] @@ -253,7 +253,7 @@ declare <8 x i16> @llvm.x86.sse41.pmovsxbw(<16 x i8>) nounwind readnone define <2 x i64> @test_x86_sse41_pmovsxdq(<4 x i32> %a0) { ; CHECK-LABEL: test_x86_sse41_pmovsxdq: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vpmovsxdq %xmm0, %xmm0 ; CHECK-NEXT: ret{{[l|q]}} %res = call <2 x i64> @llvm.x86.sse41.pmovsxdq(<4 x i32> %a0) ; <<2 x i64>> [#uses=1] @@ -264,7 +264,7 @@ declare <2 x i64> @llvm.x86.sse41.pmovsxdq(<4 x i32>) nounwind readnone define <4 x i32> @test_x86_sse41_pmovsxwd(<8 x i16> %a0) { ; CHECK-LABEL: test_x86_sse41_pmovsxwd: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vpmovsxwd %xmm0, %xmm0 ; CHECK-NEXT: ret{{[l|q]}} %res = call <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16> %a0) ; <<4 x i32>> [#uses=1] @@ -275,7 +275,7 @@ declare <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16>) nounwind readnone define <2 x i64> @test_x86_sse41_pmovsxwq(<8 x i16> %a0) { ; CHECK-LABEL: test_x86_sse41_pmovsxwq: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vpmovsxwq %xmm0, %xmm0 ; CHECK-NEXT: ret{{[l|q]}} %res = call <2 x i64> @llvm.x86.sse41.pmovsxwq(<8 x i16> %a0) ; <<2 x i64>> [#uses=1] @@ -286,7 +286,7 @@ declare <2 x i64> @llvm.x86.sse41.pmovsxwq(<8 x i16>) nounwind readnone define <4 x i32> @test_x86_sse41_pmovzxbd(<16 x i8> %a0) { ; CHECK-LABEL: test_x86_sse41_pmovzxbd: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero ; CHECK-NEXT: ret{{[l|q]}} %res = call <4 x i32> @llvm.x86.sse41.pmovzxbd(<16 x i8> %a0) ; <<4 x i32>> [#uses=1] @@ -297,7 +297,7 @@ declare <4 x i32> @llvm.x86.sse41.pmovzxbd(<16 x i8>) nounwind readnone define <2 x i64> @test_x86_sse41_pmovzxbq(<16 x i8> %a0) { ; CHECK-LABEL: test_x86_sse41_pmovzxbq: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vpmovzxbq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero ; CHECK-NEXT: ret{{[l|q]}} %res = call <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8> %a0) ; <<2 x i64>> [#uses=1] @@ -308,7 +308,7 @@ declare <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8>) nounwind readnone define <8 x i16> @test_x86_sse41_pmovzxbw(<16 x i8> %a0) { ; CHECK-LABEL: test_x86_sse41_pmovzxbw: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; CHECK-NEXT: ret{{[l|q]}} %res = call <8 x i16> @llvm.x86.sse41.pmovzxbw(<16 x i8> %a0) ; <<8 x i16>> [#uses=1] @@ -319,7 +319,7 @@ declare <8 x i16> @llvm.x86.sse41.pmovzxbw(<16 x i8>) nounwind readnone define <2 x i64> @test_x86_sse41_pmovzxdq(<4 x i32> %a0) { ; CHECK-LABEL: test_x86_sse41_pmovzxdq: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero ; CHECK-NEXT: ret{{[l|q]}} %res = call <2 x i64> @llvm.x86.sse41.pmovzxdq(<4 x i32> %a0) ; <<2 x i64>> [#uses=1] @@ -330,7 +330,7 @@ declare <2 x i64> @llvm.x86.sse41.pmovzxdq(<4 x i32>) nounwind readnone define <4 x i32> @test_x86_sse41_pmovzxwd(<8 x i16> %a0) { ; CHECK-LABEL: test_x86_sse41_pmovzxwd: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero ; CHECK-NEXT: ret{{[l|q]}} %res = call <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16> %a0) ; <<4 x i32>> [#uses=1] @@ -341,7 +341,7 @@ declare <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16>) nounwind readnone define <2 x i64> @test_x86_sse41_pmovzxwq(<8 x i16> %a0) { ; CHECK-LABEL: test_x86_sse41_pmovzxwq: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vpmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero ; CHECK-NEXT: ret{{[l|q]}} %res = call <2 x i64> @llvm.x86.sse41.pmovzxwq(<8 x i16> %a0) ; <<2 x i64>> [#uses=1] @@ -352,7 +352,7 @@ declare <2 x i64> @llvm.x86.sse41.pmovzxwq(<8 x i16>) nounwind readnone define <2 x double> @test_x86_sse2_cvtdq2pd(<4 x i32> %a0) { ; CHECK-LABEL: test_x86_sse2_cvtdq2pd: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vcvtdq2pd %xmm0, %xmm0 ; CHECK-NEXT: ret{{[l|q]}} %res = call <2 x double> @llvm.x86.sse2.cvtdq2pd(<4 x i32> %a0) ; <<2 x double>> [#uses=1] @@ -363,7 +363,7 @@ declare <2 x double> @llvm.x86.sse2.cvtdq2pd(<4 x i32>) nounwind readnone define <4 x double> @test_x86_avx_cvtdq2_pd_256(<4 x i32> %a0) { ; CHECK-LABEL: test_x86_avx_cvtdq2_pd_256: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vcvtdq2pd %xmm0, %ymm0 ; CHECK-NEXT: ret{{[l|q]}} %res = call <4 x double> @llvm.x86.avx.cvtdq2.pd.256(<4 x i32> %a0) ; <<4 x double>> [#uses=1] @@ -374,7 +374,7 @@ declare <4 x double> @llvm.x86.avx.cvtdq2.pd.256(<4 x i32>) nounwind readnone define <2 x double> @test_x86_sse2_cvtps2pd(<4 x float> %a0) { ; CHECK-LABEL: test_x86_sse2_cvtps2pd: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vcvtps2pd %xmm0, %xmm0 ; CHECK-NEXT: ret{{[l|q]}} %res = call <2 x double> @llvm.x86.sse2.cvtps2pd(<4 x float> %a0) ; <<2 x double>> [#uses=1] @@ -385,7 +385,7 @@ declare <2 x double> @llvm.x86.sse2.cvtps2pd(<4 x float>) nounwind readnone define <4 x double> @test_x86_avx_cvt_ps2_pd_256(<4 x float> %a0) { ; CHECK-LABEL: test_x86_avx_cvt_ps2_pd_256: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vcvtps2pd %xmm0, %ymm0 ; CHECK-NEXT: ret{{[l|q]}} %res = call <4 x double> @llvm.x86.avx.cvt.ps2.pd.256(<4 x float> %a0) ; <<4 x double>> [#uses=1] @@ -397,7 +397,7 @@ declare <4 x double> @llvm.x86.avx.cvt.ps2.pd.256(<4 x float>) nounwind readnone define void @test_x86_sse2_storeu_dq(i8* %a0, <16 x i8> %a1) { ; add operation forces the execution domain. ; X86-LABEL: test_x86_sse2_storeu_dq: -; X86: # BB#0: +; X86: # %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 ; X86-NEXT: vpsubb %xmm1, %xmm0, %xmm0 @@ -405,7 +405,7 @@ define void @test_x86_sse2_storeu_dq(i8* %a0, <16 x i8> %a1) { ; X86-NEXT: ret{{[l|q]}} ; ; X64-LABEL: test_x86_sse2_storeu_dq: -; X64: # BB#0: +; X64: # %bb.0: ; X64-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 ; X64-NEXT: vpsubb %xmm1, %xmm0, %xmm0 ; X64-NEXT: vmovdqu %xmm0, (%rdi) @@ -420,7 +420,7 @@ declare void @llvm.x86.sse2.storeu.dq(i8*, <16 x i8>) nounwind define void @test_x86_sse2_storeu_pd(i8* %a0, <2 x double> %a1) { ; fadd operation forces the execution domain. ; X86-LABEL: test_x86_sse2_storeu_pd: -; X86: # BB#0: +; X86: # %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: vxorpd %xmm1, %xmm1, %xmm1 ; X86-NEXT: vmovhpd {{.*#+}} xmm1 = xmm1[0],mem[0] @@ -429,7 +429,7 @@ define void @test_x86_sse2_storeu_pd(i8* %a0, <2 x double> %a1) { ; X86-NEXT: ret{{[l|q]}} ; ; X64-LABEL: test_x86_sse2_storeu_pd: -; X64: # BB#0: +; X64: # %bb.0: ; X64-NEXT: vxorpd %xmm1, %xmm1, %xmm1 ; X64-NEXT: vmovhpd {{.*#+}} xmm1 = xmm1[0],mem[0] ; X64-NEXT: vaddpd %xmm1, %xmm0, %xmm0 @@ -444,13 +444,13 @@ declare void @llvm.x86.sse2.storeu.pd(i8*, <2 x double>) nounwind define void @test_x86_sse_storeu_ps(i8* %a0, <4 x float> %a1) { ; X86-LABEL: test_x86_sse_storeu_ps: -; X86: # BB#0: +; X86: # %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: vmovups %xmm0, (%eax) ; X86-NEXT: ret{{[l|q]}} ; ; X64-LABEL: test_x86_sse_storeu_ps: -; X64: # BB#0: +; X64: # %bb.0: ; X64-NEXT: vmovups %xmm0, (%rdi) ; X64-NEXT: ret{{[l|q]}} call void @llvm.x86.sse.storeu.ps(i8* %a0, <4 x float> %a1) @@ -463,7 +463,7 @@ define void @test_x86_avx_storeu_dq_256(i8* %a0, <32 x i8> %a1) { ; FIXME: unfortunately the execution domain fix pass changes this to vmovups and its hard to force with no 256-bit integer instructions ; add operation forces the execution domain. ; X86-LABEL: test_x86_avx_storeu_dq_256: -; X86: # BB#0: +; X86: # %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: vextractf128 $1, %ymm0, %xmm1 ; X86-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2 @@ -475,7 +475,7 @@ define void @test_x86_avx_storeu_dq_256(i8* %a0, <32 x i8> %a1) { ; X86-NEXT: ret{{[l|q]}} ; ; X64-LABEL: test_x86_avx_storeu_dq_256: -; X64: # BB#0: +; X64: # %bb.0: ; X64-NEXT: vextractf128 $1, %ymm0, %xmm1 ; X64-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2 ; X64-NEXT: vpsubb %xmm2, %xmm1, %xmm1 @@ -494,7 +494,7 @@ declare void @llvm.x86.avx.storeu.dq.256(i8*, <32 x i8>) nounwind define void @test_x86_avx_storeu_pd_256(i8* %a0, <4 x double> %a1) { ; add operation forces the execution domain. ; X86-LABEL: test_x86_avx_storeu_pd_256: -; X86: # BB#0: +; X86: # %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: vxorpd %xmm1, %xmm1, %xmm1 ; X86-NEXT: vaddpd %ymm1, %ymm0, %ymm0 @@ -503,7 +503,7 @@ define void @test_x86_avx_storeu_pd_256(i8* %a0, <4 x double> %a1) { ; X86-NEXT: ret{{[l|q]}} ; ; X64-LABEL: test_x86_avx_storeu_pd_256: -; X64: # BB#0: +; X64: # %bb.0: ; X64-NEXT: vxorpd %xmm1, %xmm1, %xmm1 ; X64-NEXT: vaddpd %ymm1, %ymm0, %ymm0 ; X64-NEXT: vmovupd %ymm0, (%rdi) @@ -518,14 +518,14 @@ declare void @llvm.x86.avx.storeu.pd.256(i8*, <4 x double>) nounwind define void @test_x86_avx_storeu_ps_256(i8* %a0, <8 x float> %a1) { ; X86-LABEL: test_x86_avx_storeu_ps_256: -; X86: # BB#0: +; X86: # %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: vmovups %ymm0, (%eax) ; X86-NEXT: vzeroupper ; X86-NEXT: ret{{[l|q]}} ; ; X64-LABEL: test_x86_avx_storeu_ps_256: -; X64: # BB#0: +; X64: # %bb.0: ; X64-NEXT: vmovups %ymm0, (%rdi) ; X64-NEXT: vzeroupper ; X64-NEXT: ret{{[l|q]}} @@ -537,7 +537,7 @@ declare void @llvm.x86.avx.storeu.ps.256(i8*, <8 x float>) nounwind define <2 x double> @test_x86_avx_vpermil_pd(<2 x double> %a0) { ; CHECK-LABEL: test_x86_avx_vpermil_pd: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; CHECK-NEXT: ret{{[l|q]}} %res = call <2 x double> @llvm.x86.avx.vpermil.pd(<2 x double> %a0, i8 1) ; <<2 x double>> [#uses=1] @@ -548,7 +548,7 @@ declare <2 x double> @llvm.x86.avx.vpermil.pd(<2 x double>, i8) nounwind readnon define <4 x double> @test_x86_avx_vpermil_pd_256(<4 x double> %a0) { ; CHECK-LABEL: test_x86_avx_vpermil_pd_256: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[1,1,3,2] ; CHECK-NEXT: ret{{[l|q]}} %res = call <4 x double> @llvm.x86.avx.vpermil.pd.256(<4 x double> %a0, i8 7) ; <<4 x double>> [#uses=1] @@ -559,7 +559,7 @@ declare <4 x double> @llvm.x86.avx.vpermil.pd.256(<4 x double>, i8) nounwind rea define <4 x float> @test_x86_avx_vpermil_ps(<4 x float> %a0) { ; CHECK-LABEL: test_x86_avx_vpermil_ps: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,1,0,0] ; CHECK-NEXT: ret{{[l|q]}} %res = call <4 x float> @llvm.x86.avx.vpermil.ps(<4 x float> %a0, i8 7) ; <<4 x float>> [#uses=1] @@ -570,7 +570,7 @@ declare <4 x float> @llvm.x86.avx.vpermil.ps(<4 x float>, i8) nounwind readnone define <8 x float> @test_x86_avx_vpermil_ps_256(<8 x float> %a0) { ; CHECK-LABEL: test_x86_avx_vpermil_ps_256: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,1,0,0,7,5,4,4] ; CHECK-NEXT: ret{{[l|q]}} %res = call <8 x float> @llvm.x86.avx.vpermil.ps.256(<8 x float> %a0, i8 7) ; <<8 x float>> [#uses=1] @@ -581,7 +581,7 @@ declare <8 x float> @llvm.x86.avx.vpermil.ps.256(<8 x float>, i8) nounwind readn define <4 x double> @test_x86_avx_vperm2f128_pd_256(<4 x double> %a0, <4 x double> %a1) { ; CHECK-LABEL: test_x86_avx_vperm2f128_pd_256: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[0,1] ; CHECK-NEXT: ret{{[l|q]}} %res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 3) ; <<4 x double>> [#uses=1] @@ -592,7 +592,7 @@ declare <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double>, <4 x double>, define <8 x float> @test_x86_avx_vperm2f128_ps_256(<8 x float> %a0, <8 x float> %a1) { ; CHECK-LABEL: test_x86_avx_vperm2f128_ps_256: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[0,1] ; CHECK-NEXT: ret{{[l|q]}} %res = call <8 x float> @llvm.x86.avx.vperm2f128.ps.256(<8 x float> %a0, <8 x float> %a1, i8 3) ; <<8 x float>> [#uses=1] @@ -603,7 +603,7 @@ declare <8 x float> @llvm.x86.avx.vperm2f128.ps.256(<8 x float>, <8 x float>, i8 define <8 x i32> @test_x86_avx_vperm2f128_si_256(<8 x i32> %a0, <8 x i32> %a1) { ; CHECK-LABEL: test_x86_avx_vperm2f128_si_256: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[0,1] ; CHECK-NEXT: ret{{[l|q]}} %res = call <8 x i32> @llvm.x86.avx.vperm2f128.si.256(<8 x i32> %a0, <8 x i32> %a1, i8 3) ; <<8 x i32>> [#uses=1] |
