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Diffstat (limited to 'llvm/test/CodeGen/Thumb2/mve-pred-and.ll')
-rw-r--r--llvm/test/CodeGen/Thumb2/mve-pred-and.ll93
1 files changed, 31 insertions, 62 deletions
diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-and.ll b/llvm/test/CodeGen/Thumb2/mve-pred-and.ll
index 7578a842ec9..d227ebd35e5 100644
--- a/llvm/test/CodeGen/Thumb2/mve-pred-and.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-pred-and.ll
@@ -19,8 +19,7 @@ entry:
define arm_aapcs_vfpcc <4 x i32> @cmpnez_v4i1(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: cmpnez_v4i1:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vcmp.i32 eq, q0, zr
-; CHECK-NEXT: vpst
+; CHECK-NEXT: vpt.i32 eq, q0, zr
; CHECK-NEXT: vcmpt.i32 ne, q1, zr
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
@@ -35,8 +34,7 @@ entry:
define arm_aapcs_vfpcc <4 x i32> @cmpsltz_v4i1(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: cmpsltz_v4i1:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vcmp.i32 eq, q0, zr
-; CHECK-NEXT: vpst
+; CHECK-NEXT: vpt.i32 eq, q0, zr
; CHECK-NEXT: vcmpt.s32 lt, q1, zr
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
@@ -51,8 +49,7 @@ entry:
define arm_aapcs_vfpcc <4 x i32> @cmpsgtz_v4i1(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: cmpsgtz_v4i1:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vcmp.i32 eq, q0, zr
-; CHECK-NEXT: vpst
+; CHECK-NEXT: vpt.i32 eq, q0, zr
; CHECK-NEXT: vcmpt.s32 gt, q1, zr
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
@@ -67,8 +64,7 @@ entry:
define arm_aapcs_vfpcc <4 x i32> @cmpslez_v4i1(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: cmpslez_v4i1:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vcmp.i32 eq, q0, zr
-; CHECK-NEXT: vpst
+; CHECK-NEXT: vpt.i32 eq, q0, zr
; CHECK-NEXT: vcmpt.s32 le, q1, zr
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
@@ -83,8 +79,7 @@ entry:
define arm_aapcs_vfpcc <4 x i32> @cmpsgez_v4i1(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: cmpsgez_v4i1:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vcmp.i32 eq, q0, zr
-; CHECK-NEXT: vpst
+; CHECK-NEXT: vpt.i32 eq, q0, zr
; CHECK-NEXT: vcmpt.s32 ge, q1, zr
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
@@ -112,8 +107,7 @@ entry:
define arm_aapcs_vfpcc <4 x i32> @cmpugtz_v4i1(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: cmpugtz_v4i1:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vcmp.i32 eq, q0, zr
-; CHECK-NEXT: vpst
+; CHECK-NEXT: vpt.i32 eq, q0, zr
; CHECK-NEXT: vcmpt.i32 ne, q1, zr
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
@@ -128,8 +122,7 @@ entry:
define arm_aapcs_vfpcc <4 x i32> @cmpulez_v4i1(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: cmpulez_v4i1:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vcmp.i32 eq, q0, zr
-; CHECK-NEXT: vpst
+; CHECK-NEXT: vpt.i32 eq, q0, zr
; CHECK-NEXT: vcmpt.u32 cs, q1, zr
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
@@ -160,8 +153,7 @@ entry:
define arm_aapcs_vfpcc <4 x i32> @cmpeq_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
; CHECK-LABEL: cmpeq_v4i1:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vcmp.i32 eq, q0, zr
-; CHECK-NEXT: vpst
+; CHECK-NEXT: vpt.i32 eq, q0, zr
; CHECK-NEXT: vcmpt.i32 eq, q1, q2
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
@@ -176,8 +168,7 @@ entry:
define arm_aapcs_vfpcc <4 x i32> @cmpne_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
; CHECK-LABEL: cmpne_v4i1:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vcmp.i32 eq, q0, zr
-; CHECK-NEXT: vpst
+; CHECK-NEXT: vpt.i32 eq, q0, zr
; CHECK-NEXT: vcmpt.i32 ne, q1, q2
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
@@ -192,8 +183,7 @@ entry:
define arm_aapcs_vfpcc <4 x i32> @cmpslt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
; CHECK-LABEL: cmpslt_v4i1:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vcmp.i32 eq, q0, zr
-; CHECK-NEXT: vpst
+; CHECK-NEXT: vpt.i32 eq, q0, zr
; CHECK-NEXT: vcmpt.s32 gt, q2, q1
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
@@ -208,8 +198,7 @@ entry:
define arm_aapcs_vfpcc <4 x i32> @cmpsgt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
; CHECK-LABEL: cmpsgt_v4i1:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vcmp.i32 eq, q0, zr
-; CHECK-NEXT: vpst
+; CHECK-NEXT: vpt.i32 eq, q0, zr
; CHECK-NEXT: vcmpt.s32 gt, q1, q2
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
@@ -224,8 +213,7 @@ entry:
define arm_aapcs_vfpcc <4 x i32> @cmpsle_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
; CHECK-LABEL: cmpsle_v4i1:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vcmp.i32 eq, q0, zr
-; CHECK-NEXT: vpst
+; CHECK-NEXT: vpt.i32 eq, q0, zr
; CHECK-NEXT: vcmpt.s32 ge, q2, q1
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
@@ -240,8 +228,7 @@ entry:
define arm_aapcs_vfpcc <4 x i32> @cmpsge_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
; CHECK-LABEL: cmpsge_v4i1:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vcmp.i32 eq, q0, zr
-; CHECK-NEXT: vpst
+; CHECK-NEXT: vpt.i32 eq, q0, zr
; CHECK-NEXT: vcmpt.s32 ge, q1, q2
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
@@ -256,8 +243,7 @@ entry:
define arm_aapcs_vfpcc <4 x i32> @cmpult_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
; CHECK-LABEL: cmpult_v4i1:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vcmp.i32 eq, q0, zr
-; CHECK-NEXT: vpst
+; CHECK-NEXT: vpt.i32 eq, q0, zr
; CHECK-NEXT: vcmpt.u32 hi, q2, q1
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
@@ -272,8 +258,7 @@ entry:
define arm_aapcs_vfpcc <4 x i32> @cmpugt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
; CHECK-LABEL: cmpugt_v4i1:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vcmp.i32 eq, q0, zr
-; CHECK-NEXT: vpst
+; CHECK-NEXT: vpt.i32 eq, q0, zr
; CHECK-NEXT: vcmpt.u32 hi, q1, q2
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
@@ -288,8 +273,7 @@ entry:
define arm_aapcs_vfpcc <4 x i32> @cmpule_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
; CHECK-LABEL: cmpule_v4i1:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vcmp.i32 eq, q0, zr
-; CHECK-NEXT: vpst
+; CHECK-NEXT: vpt.i32 eq, q0, zr
; CHECK-NEXT: vcmpt.u32 cs, q2, q1
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
@@ -304,8 +288,7 @@ entry:
define arm_aapcs_vfpcc <4 x i32> @cmpuge_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
; CHECK-LABEL: cmpuge_v4i1:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vcmp.i32 eq, q0, zr
-; CHECK-NEXT: vpst
+; CHECK-NEXT: vpt.i32 eq, q0, zr
; CHECK-NEXT: vcmpt.u32 cs, q1, q2
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
@@ -321,8 +304,7 @@ entry:
define arm_aapcs_vfpcc <4 x i32> @cmpeqr_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
; CHECK-LABEL: cmpeqr_v4i1:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vcmp.i32 eq, q0, zr
-; CHECK-NEXT: vpst
+; CHECK-NEXT: vpt.i32 eq, q0, zr
; CHECK-NEXT: vcmpt.i32 eq, q1, r0
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
@@ -339,8 +321,7 @@ entry:
define arm_aapcs_vfpcc <4 x i32> @cmpner_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
; CHECK-LABEL: cmpner_v4i1:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vcmp.i32 eq, q0, zr
-; CHECK-NEXT: vpst
+; CHECK-NEXT: vpt.i32 eq, q0, zr
; CHECK-NEXT: vcmpt.i32 ne, q1, r0
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
@@ -357,9 +338,8 @@ entry:
define arm_aapcs_vfpcc <4 x i32> @cmpsltr_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
; CHECK-LABEL: cmpsltr_v4i1:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vcmp.i32 eq, q0, zr
; CHECK-NEXT: vdup.32 q2, r0
-; CHECK-NEXT: vpst
+; CHECK-NEXT: vpt.i32 eq, q0, zr
; CHECK-NEXT: vcmpt.s32 gt, q2, q1
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
@@ -376,8 +356,7 @@ entry:
define arm_aapcs_vfpcc <4 x i32> @cmpsgtr_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
; CHECK-LABEL: cmpsgtr_v4i1:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vcmp.i32 eq, q0, zr
-; CHECK-NEXT: vpst
+; CHECK-NEXT: vpt.i32 eq, q0, zr
; CHECK-NEXT: vcmpt.s32 gt, q1, r0
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
@@ -394,9 +373,8 @@ entry:
define arm_aapcs_vfpcc <4 x i32> @cmpsler_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
; CHECK-LABEL: cmpsler_v4i1:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vcmp.i32 eq, q0, zr
; CHECK-NEXT: vdup.32 q2, r0
-; CHECK-NEXT: vpst
+; CHECK-NEXT: vpt.i32 eq, q0, zr
; CHECK-NEXT: vcmpt.s32 ge, q2, q1
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
@@ -413,8 +391,7 @@ entry:
define arm_aapcs_vfpcc <4 x i32> @cmpsger_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
; CHECK-LABEL: cmpsger_v4i1:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vcmp.i32 eq, q0, zr
-; CHECK-NEXT: vpst
+; CHECK-NEXT: vpt.i32 eq, q0, zr
; CHECK-NEXT: vcmpt.s32 ge, q1, r0
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
@@ -431,9 +408,8 @@ entry:
define arm_aapcs_vfpcc <4 x i32> @cmpultr_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
; CHECK-LABEL: cmpultr_v4i1:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vcmp.i32 eq, q0, zr
; CHECK-NEXT: vdup.32 q2, r0
-; CHECK-NEXT: vpst
+; CHECK-NEXT: vpt.i32 eq, q0, zr
; CHECK-NEXT: vcmpt.u32 hi, q2, q1
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
@@ -450,8 +426,7 @@ entry:
define arm_aapcs_vfpcc <4 x i32> @cmpugtr_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
; CHECK-LABEL: cmpugtr_v4i1:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vcmp.i32 eq, q0, zr
-; CHECK-NEXT: vpst
+; CHECK-NEXT: vpt.i32 eq, q0, zr
; CHECK-NEXT: vcmpt.u32 hi, q1, r0
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
@@ -468,9 +443,8 @@ entry:
define arm_aapcs_vfpcc <4 x i32> @cmpuler_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
; CHECK-LABEL: cmpuler_v4i1:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vcmp.i32 eq, q0, zr
; CHECK-NEXT: vdup.32 q2, r0
-; CHECK-NEXT: vpst
+; CHECK-NEXT: vpt.i32 eq, q0, zr
; CHECK-NEXT: vcmpt.u32 cs, q2, q1
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
@@ -487,8 +461,7 @@ entry:
define arm_aapcs_vfpcc <4 x i32> @cmpuger_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
; CHECK-LABEL: cmpuger_v4i1:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vcmp.i32 eq, q0, zr
-; CHECK-NEXT: vpst
+; CHECK-NEXT: vpt.i32 eq, q0, zr
; CHECK-NEXT: vcmpt.u32 cs, q1, r0
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
@@ -522,8 +495,7 @@ entry:
define arm_aapcs_vfpcc <8 x i16> @cmpeq_v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {
; CHECK-LABEL: cmpeq_v8i1:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vcmp.i16 eq, q0, zr
-; CHECK-NEXT: vpst
+; CHECK-NEXT: vpt.i16 eq, q0, zr
; CHECK-NEXT: vcmpt.i16 eq, q1, q2
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
@@ -538,8 +510,7 @@ entry:
define arm_aapcs_vfpcc <8 x i16> @cmpeqr_v8i1(<8 x i16> %a, <8 x i16> %b, i16 %c) {
; CHECK-LABEL: cmpeqr_v8i1:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vcmp.i16 eq, q0, zr
-; CHECK-NEXT: vpst
+; CHECK-NEXT: vpt.i16 eq, q0, zr
; CHECK-NEXT: vcmpt.i16 eq, q1, r0
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
@@ -572,8 +543,7 @@ entry:
define arm_aapcs_vfpcc <16 x i8> @cmpeq_v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; CHECK-LABEL: cmpeq_v16i1:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vcmp.i8 eq, q0, zr
-; CHECK-NEXT: vpst
+; CHECK-NEXT: vpt.i8 eq, q0, zr
; CHECK-NEXT: vcmpt.i8 eq, q1, q2
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
@@ -588,8 +558,7 @@ entry:
define arm_aapcs_vfpcc <16 x i8> @cmpeqr_v16i1(<16 x i8> %a, <16 x i8> %b, i8 %c) {
; CHECK-LABEL: cmpeqr_v16i1:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vcmp.i8 eq, q0, zr
-; CHECK-NEXT: vpst
+; CHECK-NEXT: vpt.i8 eq, q0, zr
; CHECK-NEXT: vcmpt.i8 eq, q1, r0
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
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