diff options
Diffstat (limited to 'llvm/test/CodeGen/SystemZ')
19 files changed, 19 insertions, 19 deletions
diff --git a/llvm/test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir b/llvm/test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir index dfb86c028eb..88a767d0788 100644 --- a/llvm/test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir +++ b/llvm/test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir @@ -23,7 +23,7 @@ # CHECK: id: 114, class --- name: autogen_SD21418 -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: vr128bit } diff --git a/llvm/test/CodeGen/SystemZ/clear-liverange-spillreg.mir b/llvm/test/CodeGen/SystemZ/clear-liverange-spillreg.mir index 1dcf96298d5..32fad11f1d3 100644 --- a/llvm/test/CodeGen/SystemZ/clear-liverange-spillreg.mir +++ b/llvm/test/CodeGen/SystemZ/clear-liverange-spillreg.mir @@ -22,7 +22,7 @@ define void @encode_one_macroblock() { ret void } --- name: encode_one_macroblock -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: addr64bit } diff --git a/llvm/test/CodeGen/SystemZ/cond-move-04.mir b/llvm/test/CodeGen/SystemZ/cond-move-04.mir index 5651c6bdc1e..6e6bd061d53 100644 --- a/llvm/test/CodeGen/SystemZ/cond-move-04.mir +++ b/llvm/test/CodeGen/SystemZ/cond-move-04.mir @@ -37,7 +37,7 @@ --- name: fun -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: gr32bit } diff --git a/llvm/test/CodeGen/SystemZ/cond-move-05.mir b/llvm/test/CodeGen/SystemZ/cond-move-05.mir index de33f49734f..60035746c7f 100644 --- a/llvm/test/CodeGen/SystemZ/cond-move-05.mir +++ b/llvm/test/CodeGen/SystemZ/cond-move-05.mir @@ -47,7 +47,7 @@ --- name: main -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: gr64bit } diff --git a/llvm/test/CodeGen/SystemZ/cond-move-08.mir b/llvm/test/CodeGen/SystemZ/cond-move-08.mir index aa5c4cd1697..5808fc643bc 100644 --- a/llvm/test/CodeGen/SystemZ/cond-move-08.mir +++ b/llvm/test/CodeGen/SystemZ/cond-move-08.mir @@ -83,7 +83,7 @@ --- name: fun1 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: grx32bit } diff --git a/llvm/test/CodeGen/SystemZ/cond-move-regalloc-hints.mir b/llvm/test/CodeGen/SystemZ/cond-move-regalloc-hints.mir index fa0b3ee8012..f987b80e9fa 100644 --- a/llvm/test/CodeGen/SystemZ/cond-move-regalloc-hints.mir +++ b/llvm/test/CodeGen/SystemZ/cond-move-regalloc-hints.mir @@ -117,7 +117,7 @@ --- name: fun -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr64bit } diff --git a/llvm/test/CodeGen/SystemZ/debuginstr-00.mir b/llvm/test/CodeGen/SystemZ/debuginstr-00.mir index 53a43d03a22..25cda188689 100644 --- a/llvm/test/CodeGen/SystemZ/debuginstr-00.mir +++ b/llvm/test/CodeGen/SystemZ/debuginstr-00.mir @@ -52,7 +52,7 @@ ... --- name: put_charge_groups_in_box -alignment: 4 +alignment: 16 tracksRegLiveness: true frameInfo: maxCallFrameSize: 0 diff --git a/llvm/test/CodeGen/SystemZ/debuginstr-01.mir b/llvm/test/CodeGen/SystemZ/debuginstr-01.mir index bcc7f547941..162bc6df757 100644 --- a/llvm/test/CodeGen/SystemZ/debuginstr-01.mir +++ b/llvm/test/CodeGen/SystemZ/debuginstr-01.mir @@ -50,7 +50,7 @@ ... --- name: f1 -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$r2d' } diff --git a/llvm/test/CodeGen/SystemZ/debuginstr-02.mir b/llvm/test/CodeGen/SystemZ/debuginstr-02.mir index 1a209496d03..7c4f6735cf5 100644 --- a/llvm/test/CodeGen/SystemZ/debuginstr-02.mir +++ b/llvm/test/CodeGen/SystemZ/debuginstr-02.mir @@ -47,7 +47,7 @@ ... --- name: fun -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr32bit } diff --git a/llvm/test/CodeGen/SystemZ/debuginstr-cgp.mir b/llvm/test/CodeGen/SystemZ/debuginstr-cgp.mir index 8d76c33f8ff..f61ca330073 100644 --- a/llvm/test/CodeGen/SystemZ/debuginstr-cgp.mir +++ b/llvm/test/CodeGen/SystemZ/debuginstr-cgp.mir @@ -166,6 +166,6 @@ ... --- name: Fun -alignment: 4 +alignment: 16 tracksRegLiveness: true ... diff --git a/llvm/test/CodeGen/SystemZ/fp-conv-17.mir b/llvm/test/CodeGen/SystemZ/fp-conv-17.mir index 4cde00ee9d1..42c5e99a230 100644 --- a/llvm/test/CodeGen/SystemZ/fp-conv-17.mir +++ b/llvm/test/CodeGen/SystemZ/fp-conv-17.mir @@ -81,7 +81,7 @@ --- name: f0 -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: addr64bit } diff --git a/llvm/test/CodeGen/SystemZ/load-and-test-RA-hints.mir b/llvm/test/CodeGen/SystemZ/load-and-test-RA-hints.mir index 707e7c538fd..f36216e61a2 100644 --- a/llvm/test/CodeGen/SystemZ/load-and-test-RA-hints.mir +++ b/llvm/test/CodeGen/SystemZ/load-and-test-RA-hints.mir @@ -88,7 +88,7 @@ --- name: proofnumberscan -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: addr64bit } diff --git a/llvm/test/CodeGen/SystemZ/misched-readadvances.mir b/llvm/test/CodeGen/SystemZ/misched-readadvances.mir index df8ca2f5f95..12dea8b8f25 100644 --- a/llvm/test/CodeGen/SystemZ/misched-readadvances.mir +++ b/llvm/test/CodeGen/SystemZ/misched-readadvances.mir @@ -16,7 +16,7 @@ --- name: Perl_do_sv_dump -alignment: 4 +alignment: 16 tracksRegLiveness: true body: | bb.0 : diff --git a/llvm/test/CodeGen/SystemZ/postra-sched-expandedops.mir b/llvm/test/CodeGen/SystemZ/postra-sched-expandedops.mir index 43b9a1b8a13..c3ebec18424 100644 --- a/llvm/test/CodeGen/SystemZ/postra-sched-expandedops.mir +++ b/llvm/test/CodeGen/SystemZ/postra-sched-expandedops.mir @@ -55,7 +55,7 @@ ... --- name: LearnStoreTT -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$r2d' } diff --git a/llvm/test/CodeGen/SystemZ/regalloc-GR128-02.mir b/llvm/test/CodeGen/SystemZ/regalloc-GR128-02.mir index 65758bea4fd..e6a1e7e50cb 100644 --- a/llvm/test/CodeGen/SystemZ/regalloc-GR128-02.mir +++ b/llvm/test/CodeGen/SystemZ/regalloc-GR128-02.mir @@ -27,7 +27,7 @@ ... --- name: main -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: grx32bit } diff --git a/llvm/test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir b/llvm/test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir index 195dbb996ef..cf2c274b1c3 100644 --- a/llvm/test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir +++ b/llvm/test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir @@ -11,7 +11,7 @@ # PR33677 --- name: main -alignment: 2 +alignment: 4 tracksRegLiveness: true # CHECK: $r0l = COPY renamable $r1l # Although R0L partially redefines R0Q, it must not mark R0Q as kill diff --git a/llvm/test/CodeGen/SystemZ/regcoal-undef-lane-4-rm-cp-commuting-def.mir b/llvm/test/CodeGen/SystemZ/regcoal-undef-lane-4-rm-cp-commuting-def.mir index 4245dafb00d..86e22ad3644 100644 --- a/llvm/test/CodeGen/SystemZ/regcoal-undef-lane-4-rm-cp-commuting-def.mir +++ b/llvm/test/CodeGen/SystemZ/regcoal-undef-lane-4-rm-cp-commuting-def.mir @@ -17,7 +17,7 @@ # PR40215. --- name: main -alignment: 4 +alignment: 16 tracksRegLiveness: true machineFunctionInfo: {} body: | diff --git a/llvm/test/CodeGen/SystemZ/subregliveness-06.mir b/llvm/test/CodeGen/SystemZ/subregliveness-06.mir index d0dc1652c15..96aa9109a51 100644 --- a/llvm/test/CodeGen/SystemZ/subregliveness-06.mir +++ b/llvm/test/CodeGen/SystemZ/subregliveness-06.mir @@ -144,7 +144,7 @@ ... --- name: func_32 -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$r2d', virtual-reg: '%10' } diff --git a/llvm/test/CodeGen/SystemZ/subregliveness-07.mir b/llvm/test/CodeGen/SystemZ/subregliveness-07.mir index 599e5a5e10f..e8f951ea2a1 100644 --- a/llvm/test/CodeGen/SystemZ/subregliveness-07.mir +++ b/llvm/test/CodeGen/SystemZ/subregliveness-07.mir @@ -18,7 +18,7 @@ --- name: main -alignment: 4 +alignment: 16 tracksRegLiveness: true body: | bb.0: |
