summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen/SystemZ/vec-cmp-cmp-logic-select.ll
diff options
context:
space:
mode:
Diffstat (limited to 'llvm/test/CodeGen/SystemZ/vec-cmp-cmp-logic-select.ll')
-rw-r--r--llvm/test/CodeGen/SystemZ/vec-cmp-cmp-logic-select.ll84
1 files changed, 42 insertions, 42 deletions
diff --git a/llvm/test/CodeGen/SystemZ/vec-cmp-cmp-logic-select.ll b/llvm/test/CodeGen/SystemZ/vec-cmp-cmp-logic-select.ll
index eafb0122e90..ac12861603a 100644
--- a/llvm/test/CodeGen/SystemZ/vec-cmp-cmp-logic-select.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-cmp-cmp-logic-select.ll
@@ -7,7 +7,7 @@
define <2 x i8> @fun0(<2 x i8> %val1, <2 x i8> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x i8> %val5, <2 x i8> %val6) {
; CHECK-LABEL: fun0:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-DAG: vceqb [[REG0:%v[0-9]+]], %v24, %v26
; CHECK-DAG: vceqb [[REG1:%v[0-9]+]], %v28, %v30
; CHECK-NEXT: vn %v0, [[REG0]], [[REG1]]
@@ -22,7 +22,7 @@ define <2 x i8> @fun0(<2 x i8> %val1, <2 x i8> %val2, <2 x i8> %val3, <2 x i8> %
define <2 x i16> @fun1(<2 x i8> %val1, <2 x i8> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x i16> %val5, <2 x i16> %val6) {
; CHECK-LABEL: fun1:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-DAG: vceqb [[REG0:%v[0-9]+]], %v24, %v26
; CHECK-DAG: vceqb [[REG1:%v[0-9]+]], %v28, %v30
; CHECK-NEXT: vn %v0, [[REG0]], [[REG1]]
@@ -38,7 +38,7 @@ define <2 x i16> @fun1(<2 x i8> %val1, <2 x i8> %val2, <2 x i8> %val3, <2 x i8>
define <16 x i8> @fun2(<16 x i8> %val1, <16 x i8> %val2, <16 x i16> %val3, <16 x i16> %val4, <16 x i8> %val5, <16 x i8> %val6) {
; CHECK-LABEL: fun2:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-DAG: vceqh [[REG0:%v[0-9]+]], %v30, %v27
; CHECK-DAG: vceqh [[REG1:%v[0-9]+]], %v28, %v25
; CHECK-DAG: vceqb [[REG2:%v[0-9]+]], %v24, %v26
@@ -55,7 +55,7 @@ define <16 x i8> @fun2(<16 x i8> %val1, <16 x i8> %val2, <16 x i16> %val3, <16 x
define <16 x i16> @fun3(<16 x i8> %val1, <16 x i8> %val2, <16 x i16> %val3, <16 x i16> %val4, <16 x i16> %val5, <16 x i16> %val6) {
; CHECK-LABEL: fun3:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-DAG: vceqb [[REG0:%v[0-9]+]], %v24, %v26
; CHECK-DAG: vuphb [[REG2:%v[0-9]+]], [[REG0]]
; CHECK-DAG: vmrlg [[REG1:%v[0-9]+]], [[REG0]], [[REG0]]
@@ -78,7 +78,7 @@ define <16 x i16> @fun3(<16 x i8> %val1, <16 x i8> %val2, <16 x i16> %val3, <16
define <32 x i8> @fun4(<32 x i8> %val1, <32 x i8> %val2, <32 x i8> %val3, <32 x i8> %val4, <32 x i8> %val5, <32 x i8> %val6) {
; CHECK-LABEL: fun4:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-DAG: vceqb [[REG0:%v[0-9]+]], %v24, %v28
; CHECK-DAG: vceqb [[REG1:%v[0-9]+]], %v26, %v30
; CHECK-DAG: vceqb [[REG2:%v[0-9]+]], %v25, %v29
@@ -101,7 +101,7 @@ define <32 x i8> @fun4(<32 x i8> %val1, <32 x i8> %val2, <32 x i8> %val3, <32 x
define <2 x i8> @fun5(<2 x i16> %val1, <2 x i16> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x i8> %val5, <2 x i8> %val6) {
; CHECK-LABEL: fun5:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-DAG: vceqh [[REG0:%v[0-9]+]], %v24, %v26
; CHECK-DAG: vpkh [[REG1:%v[0-9]+]], [[REG0]], [[REG0]]
; CHECK-DAG: vceqb [[REG2:%v[0-9]+]], %v28, %v30
@@ -117,7 +117,7 @@ define <2 x i8> @fun5(<2 x i16> %val1, <2 x i16> %val2, <2 x i8> %val3, <2 x i8>
define <2 x i16> @fun6(<2 x i16> %val1, <2 x i16> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x i16> %val5, <2 x i16> %val6) {
; CHECK-LABEL: fun6:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-NEXT: vceqb %v1, %v28, %v30
; CHECK-NEXT: vceqh %v0, %v24, %v26
; CHECK-NEXT: vuphb %v1, %v1
@@ -133,7 +133,7 @@ define <2 x i16> @fun6(<2 x i16> %val1, <2 x i16> %val2, <2 x i8> %val3, <2 x i8
define <2 x i32> @fun7(<2 x i16> %val1, <2 x i16> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x i32> %val5, <2 x i32> %val6) {
; CHECK-LABEL: fun7:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-NEXT: vceqb %v1, %v28, %v30
; CHECK-NEXT: vceqh %v0, %v24, %v26
; CHECK-NEXT: vuphb %v1, %v1
@@ -150,7 +150,7 @@ define <2 x i32> @fun7(<2 x i16> %val1, <2 x i16> %val2, <2 x i8> %val3, <2 x i8
define <8 x i8> @fun8(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3, <8 x i16> %val4, <8 x i8> %val5, <8 x i8> %val6) {
; CHECK-LABEL: fun8:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-DAG: vceqh [[REG0:%v[0-9]+]], %v24, %v26
; CHECK-DAG: vceqh [[REG1:%v[0-9]+]], %v28, %v30
; CHECK-NEXT: vx %v0, [[REG0]], [[REG1]]
@@ -166,7 +166,7 @@ define <8 x i8> @fun8(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3, <8 x i1
define <8 x i16> @fun9(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3, <8 x i16> %val4, <8 x i16> %val5, <8 x i16> %val6) {
; CHECK-LABEL: fun9:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-DAG: vceqh [[REG0:%v[0-9]+]], %v24, %v26
; CHECK-DAG: vceqh [[REG1:%v[0-9]+]], %v28, %v30
; CHECK-NEXT: vx %v0, [[REG0]], [[REG1]]
@@ -181,7 +181,7 @@ define <8 x i16> @fun9(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3, <8 x i
define <8 x i32> @fun10(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3, <8 x i16> %val4, <8 x i32> %val5, <8 x i32> %val6) {
; CHECK-LABEL: fun10:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-DAG: vceqh [[REG0:%v[0-9]+]], %v24, %v26
; CHECK-DAG: vceqh [[REG1:%v[0-9]+]], %v28, %v30
; CHECK-NEXT: vx [[REG2:%v[0-9]+]], [[REG0]], [[REG1]]
@@ -200,7 +200,7 @@ define <8 x i32> @fun10(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3, <8 x
define <16 x i8> @fun11(<16 x i16> %val1, <16 x i16> %val2, <16 x i32> %val3, <16 x i32> %val4, <16 x i8> %val5, <16 x i8> %val6) {
; CHECK-LABEL: fun11:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-DAG: vl [[REG0:%v[0-9]+]], 192(%r15)
; CHECK-DAG: vl [[REG1:%v[0-9]+]], 208(%r15)
; CHECK-DAG: vl [[REG2:%v[0-9]+]], 160(%r15)
@@ -229,7 +229,7 @@ define <16 x i8> @fun11(<16 x i16> %val1, <16 x i16> %val2, <16 x i32> %val3, <1
define <16 x i16> @fun12(<16 x i16> %val1, <16 x i16> %val2, <16 x i32> %val3, <16 x i32> %val4, <16 x i16> %val5, <16 x i16> %val6) {
; CHECK-LABEL: fun12:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-DAG: vl [[REG0:%v[0-9]+]], 192(%r15)
; CHECK-DAG: vl [[REG1:%v[0-9]+]], 208(%r15)
; CHECK-DAG: vl [[REG2:%v[0-9]+]], 160(%r15)
@@ -260,7 +260,7 @@ define <16 x i16> @fun12(<16 x i16> %val1, <16 x i16> %val2, <16 x i32> %val3, <
define <2 x i16> @fun13(<2 x i32> %val1, <2 x i32> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i16> %val5, <2 x i16> %val6) {
; CHECK-LABEL: fun13:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-NEXT: vceqg %v1, %v28, %v30
; CHECK-NEXT: vceqf %v0, %v24, %v26
; CHECK-NEXT: vpkg %v1, %v1, %v1
@@ -277,7 +277,7 @@ define <2 x i16> @fun13(<2 x i32> %val1, <2 x i32> %val2, <2 x i64> %val3, <2 x
define <2 x i32> @fun14(<2 x i32> %val1, <2 x i32> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i32> %val5, <2 x i32> %val6) {
; CHECK-LABEL: fun14:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-NEXT: vceqg %v1, %v28, %v30
; CHECK-NEXT: vceqf %v0, %v24, %v26
; CHECK-NEXT: vpkg %v1, %v1, %v1
@@ -293,7 +293,7 @@ define <2 x i32> @fun14(<2 x i32> %val1, <2 x i32> %val2, <2 x i64> %val3, <2 x
define <2 x i64> @fun15(<2 x i32> %val1, <2 x i32> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i64> %val5, <2 x i64> %val6) {
; CHECK-LABEL: fun15:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-DAG: vceqf [[REG0:%v[0-9]+]], %v24, %v26
; CHECK-DAG: vuphf [[REG1:%v[0-9]+]], [[REG0]]
; CHECK-DAG: vceqg [[REG2:%v[0-9]+]], %v28, %v30
@@ -309,7 +309,7 @@ define <2 x i64> @fun15(<2 x i32> %val1, <2 x i32> %val2, <2 x i64> %val3, <2 x
define <4 x i16> @fun16(<4 x i32> %val1, <4 x i32> %val2, <4 x i16> %val3, <4 x i16> %val4, <4 x i16> %val5, <4 x i16> %val6) {
; CHECK-LABEL: fun16:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-DAG: vceqf [[REG0:%v[0-9]+]], %v24, %v26
; CHECK-DAG: vpkf [[REG1:%v[0-9]+]], [[REG0]], [[REG0]]
; CHECK-DAG: vceqh [[REG2:%v[0-9]+]], %v28, %v30
@@ -325,7 +325,7 @@ define <4 x i16> @fun16(<4 x i32> %val1, <4 x i32> %val2, <4 x i16> %val3, <4 x
define <4 x i32> @fun17(<4 x i32> %val1, <4 x i32> %val2, <4 x i16> %val3, <4 x i16> %val4, <4 x i32> %val5, <4 x i32> %val6) {
; CHECK-LABEL: fun17:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-NEXT: vceqh %v1, %v28, %v30
; CHECK-NEXT: vceqf %v0, %v24, %v26
; CHECK-NEXT: vuphh %v1, %v1
@@ -341,7 +341,7 @@ define <4 x i32> @fun17(<4 x i32> %val1, <4 x i32> %val2, <4 x i16> %val3, <4 x
define <4 x i64> @fun18(<4 x i32> %val1, <4 x i32> %val2, <4 x i16> %val3, <4 x i16> %val4, <4 x i64> %val5, <4 x i64> %val6) {
; CHECK-LABEL: fun18:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-NEXT: vceqh %v1, %v28, %v30
; CHECK-NEXT: vceqf %v0, %v24, %v26
; CHECK-NEXT: vuphh %v1, %v1
@@ -361,7 +361,7 @@ define <4 x i64> @fun18(<4 x i32> %val1, <4 x i32> %val2, <4 x i16> %val3, <4 x
define <8 x i16> @fun19(<8 x i32> %val1, <8 x i32> %val2, <8 x i32> %val3, <8 x i32> %val4, <8 x i16> %val5, <8 x i16> %val6) {
; CHECK-LABEL: fun19:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-DAG: vceqf [[REG0:%v[0-9]+]], %v24, %v28
; CHECK-DAG: vceqf [[REG1:%v[0-9]+]], %v26, %v30
; CHECK-DAG: vceqf [[REG2:%v[0-9]+]], %v25, %v29
@@ -382,7 +382,7 @@ define <8 x i16> @fun19(<8 x i32> %val1, <8 x i32> %val2, <8 x i32> %val3, <8 x
define <8 x i32> @fun20(<8 x i32> %val1, <8 x i32> %val2, <8 x i32> %val3, <8 x i32> %val4, <8 x i32> %val5, <8 x i32> %val6) {
; CHECK-LABEL: fun20:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-DAG: vceqf [[REG0:%v[0-9]+]], %v24, %v28
; CHECK-DAG: vceqf [[REG1:%v[0-9]+]], %v26, %v30
; CHECK-DAG: vceqf [[REG2:%v[0-9]+]], %v25, %v29
@@ -405,7 +405,7 @@ define <8 x i32> @fun20(<8 x i32> %val1, <8 x i32> %val2, <8 x i32> %val3, <8 x
define <2 x i32> @fun21(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i32> %val5, <2 x i32> %val6) {
; CHECK-LABEL: fun21:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-DAG: vceqg [[REG0:%v[0-9]+]], %v24, %v26
; CHECK-DAG: vceqg [[REG1:%v[0-9]+]], %v28, %v30
; CHECK-NEXT: vn %v0, [[REG0]], [[REG1]]
@@ -421,7 +421,7 @@ define <2 x i32> @fun21(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3, <2 x
define <2 x i64> @fun22(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i64> %val5, <2 x i64> %val6) {
; CHECK-LABEL: fun22:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-DAG: vceqg [[REG0:%v[0-9]+]], %v24, %v26
; CHECK-DAG: vceqg [[REG1:%v[0-9]+]], %v28, %v30
; CHECK-NEXT: vn %v0, [[REG0]], [[REG1]]
@@ -436,7 +436,7 @@ define <2 x i64> @fun22(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3, <2 x
define <4 x i32> @fun23(<4 x i64> %val1, <4 x i64> %val2, <4 x i32> %val3, <4 x i32> %val4, <4 x i32> %val5, <4 x i32> %val6) {
; CHECK-LABEL: fun23:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-NEXT: vceqg %v0, %v26, %v30
; CHECK-NEXT: vceqg %v1, %v24, %v28
; CHECK-NEXT: vpkg %v0, %v1, %v0
@@ -453,7 +453,7 @@ define <4 x i32> @fun23(<4 x i64> %val1, <4 x i64> %val2, <4 x i32> %val3, <4 x
define <4 x i64> @fun24(<4 x i64> %val1, <4 x i64> %val2, <4 x i32> %val3, <4 x i32> %val4, <4 x i64> %val5, <4 x i64> %val6) {
; CHECK-LABEL: fun24:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-NEXT: vceqf [[REG0:%v[0-9]+]], %v25, %v27
; CHECK-NEXT: vuphf [[REG1:%v[0-9]+]], [[REG0]]
; CHECK-NEXT: vmrlg [[REG2:%v[0-9]+]], [[REG0]], [[REG0]]
@@ -476,7 +476,7 @@ define <4 x i64> @fun24(<4 x i64> %val1, <4 x i64> %val2, <4 x i32> %val3, <4 x
define <2 x float> @fun25(<2 x float> %val1, <2 x float> %val2, <2 x double> %val3, <2 x double> %val4, <2 x float> %val5, <2 x float> %val6) {
; CHECK-LABEL: fun25:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-NEXT: vmrlf %v0, %v26, %v26
; CHECK-NEXT: vmrlf %v1, %v24, %v24
; CHECK-NEXT: vldeb %v0, %v0
@@ -495,7 +495,7 @@ define <2 x float> @fun25(<2 x float> %val1, <2 x float> %val2, <2 x double> %va
; CHECK-NEXT: br %r14
;
; CHECK-Z14-LABEL: fun25:
-; CHECK-Z14: # BB#0:
+; CHECK-Z14: # %bb.0:
; CHECK-Z14-NEXT: vfchdb %v1, %v28, %v30
; CHECK-Z14-NEXT: vfchsb %v0, %v24, %v26
; CHECK-Z14-NEXT: vpkg %v1, %v1, %v1
@@ -511,7 +511,7 @@ define <2 x float> @fun25(<2 x float> %val1, <2 x float> %val2, <2 x double> %va
define <2 x double> @fun26(<2 x float> %val1, <2 x float> %val2, <2 x double> %val3, <2 x double> %val4, <2 x double> %val5, <2 x double> %val6) {
; CHECK-LABEL: fun26:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-NEXT: vmrlf %v0, %v26, %v26
; CHECK-NEXT: vmrlf %v1, %v24, %v24
; CHECK-NEXT: vldeb %v0, %v0
@@ -530,7 +530,7 @@ define <2 x double> @fun26(<2 x float> %val1, <2 x float> %val2, <2 x double> %v
; CHECK-NEXT: br %r14
;
; CHECK-Z14-LABEL: fun26:
-; CHECK-Z14: # BB#0:
+; CHECK-Z14: # %bb.0:
; CHECK-Z14-NEXT: vfchsb %v0, %v24, %v26
; CHECK-Z14-NEXT: vuphf %v0, %v0
; CHECK-Z14-NEXT: vfchdb %v1, %v28, %v30
@@ -547,7 +547,7 @@ define <2 x double> @fun26(<2 x float> %val1, <2 x float> %val2, <2 x double> %v
; Also check a widening select of a vector of floats
define <2 x float> @fun27(<2 x i8> %val1, <2 x i8> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x float> %val5, <2 x float> %val6) {
; CHECK-LABEL: fun27:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-DAG: vceqb [[REG0:%v[0-9]+]], %v24, %v26
; CHECK-DAG: vceqb [[REG1:%v[0-9]+]], %v28, %v30
; CHECK-NEXT: vo %v0, [[REG0]], [[REG1]]
@@ -564,7 +564,7 @@ define <2 x float> @fun27(<2 x i8> %val1, <2 x i8> %val2, <2 x i8> %val3, <2 x i
define <4 x float> @fun28(<4 x float> %val1, <4 x float> %val2, <4 x float> %val3, <4 x float> %val4, <4 x float> %val5, <4 x float> %val6) {
; CHECK-LABEL: fun28:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-DAG: vmrlf [[REG0:%v[0-9]+]], %v26, %v26
; CHECK-DAG: vmrlf [[REG1:%v[0-9]+]], %v24, %v24
; CHECK-DAG: vldeb [[REG2:%v[0-9]+]], [[REG0]]
@@ -592,7 +592,7 @@ define <4 x float> @fun28(<4 x float> %val1, <4 x float> %val2, <4 x float> %val
; CHECK-NEXT: br %r14
;
; CHECK-Z14-LABEL: fun28:
-; CHECK-Z14: # BB#0:
+; CHECK-Z14: # %bb.0:
; CHECK-Z14-NEXT: vfchsb %v0, %v24, %v26
; CHECK-Z14-NEXT: vfchsb %v1, %v28, %v30
; CHECK-Z14-NEXT: vx %v0, %v0, %v1
@@ -607,7 +607,7 @@ define <4 x float> @fun28(<4 x float> %val1, <4 x float> %val2, <4 x float> %val
define <4 x double> @fun29(<4 x float> %val1, <4 x float> %val2, <4 x float> %val3, <4 x float> %val4, <4 x double> %val5, <4 x double> %val6) {
; CHECK-LABEL: fun29:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-NEXT: vmrlf %v0, %v26, %v26
; CHECK-NEXT: vmrlf %v1, %v24, %v24
; CHECK-NEXT: vldeb %v0, %v0
@@ -639,7 +639,7 @@ define <4 x double> @fun29(<4 x float> %val1, <4 x float> %val2, <4 x float> %va
; CHECK-NEXT: br %r14
;
; CHECK-Z14-LABEL: fun29:
-; CHECK-Z14: # BB#0:
+; CHECK-Z14: # %bb.0:
; CHECK-Z14-NEXT: vfchsb %v0, %v24, %v26
; CHECK-Z14-NEXT: vfchsb %v1, %v28, %v30
; CHECK-Z14-NEXT: vx %v0, %v0, %v1
@@ -658,7 +658,7 @@ define <4 x double> @fun29(<4 x float> %val1, <4 x float> %val2, <4 x float> %va
define <8 x float> @fun30(<8 x float> %val1, <8 x float> %val2, <8 x double> %val3, <8 x double> %val4, <8 x float> %val5, <8 x float> %val6) {
; CHECK-LABEL: fun30:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-NEXT: vmrlf %v16, %v28, %v28
; CHECK-NEXT: vmrlf %v17, %v24, %v24
; CHECK-NEXT: vldeb %v16, %v16
@@ -702,7 +702,7 @@ define <8 x float> @fun30(<8 x float> %val1, <8 x float> %val2, <8 x double> %va
; CHECK-NEXT: br %r14
;
; CHECK-Z14-LABEL: fun30:
-; CHECK-Z14: # BB#0:
+; CHECK-Z14: # %bb.0:
; CHECK-Z14-NEXT: vl %v4, 192(%r15)
; CHECK-Z14-NEXT: vl %v5, 208(%r15)
; CHECK-Z14-NEXT: vl %v6, 160(%r15)
@@ -733,7 +733,7 @@ define <8 x float> @fun30(<8 x float> %val1, <8 x float> %val2, <8 x double> %va
define <2 x float> @fun31(<2 x double> %val1, <2 x double> %val2, <2 x double> %val3, <2 x double> %val4, <2 x float> %val5, <2 x float> %val6) {
; CHECK-LABEL: fun31:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-DAG: vfchdb [[REG0:%v[0-9]+]], %v24, %v26
; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v28, %v30
; CHECK-NEXT: vx %v0, [[REG0]], [[REG1]]
@@ -749,7 +749,7 @@ define <2 x float> @fun31(<2 x double> %val1, <2 x double> %val2, <2 x double> %
define <2 x double> @fun32(<2 x double> %val1, <2 x double> %val2, <2 x double> %val3, <2 x double> %val4, <2 x double> %val5, <2 x double> %val6) {
; CHECK-LABEL: fun32:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-DAG: vfchdb [[REG0:%v[0-9]+]], %v24, %v26
; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v28, %v30
; CHECK-NEXT: vx %v0, [[REG0]], [[REG1]]
@@ -764,7 +764,7 @@ define <2 x double> @fun32(<2 x double> %val1, <2 x double> %val2, <2 x double>
define <4 x float> @fun33(<4 x double> %val1, <4 x double> %val2, <4 x float> %val3, <4 x float> %val4, <4 x float> %val5, <4 x float> %val6) {
; CHECK-LABEL: fun33:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-NEXT: vfchdb %v0, %v26, %v30
; CHECK-NEXT: vfchdb %v1, %v24, %v28
; CHECK-NEXT: vpkg %v0, %v1, %v0
@@ -784,7 +784,7 @@ define <4 x float> @fun33(<4 x double> %val1, <4 x double> %val2, <4 x float> %v
; CHECK-NEXT: br %r14
;
; CHECK-Z14-LABEL: fun33:
-; CHECK-Z14: # BB#0:
+; CHECK-Z14: # %bb.0:
; CHECK-Z14-NEXT: vfchdb %v0, %v26, %v30
; CHECK-Z14-NEXT: vfchdb %v1, %v24, %v28
; CHECK-Z14-NEXT: vpkg %v0, %v1, %v0
@@ -801,7 +801,7 @@ define <4 x float> @fun33(<4 x double> %val1, <4 x double> %val2, <4 x float> %v
define <4 x double> @fun34(<4 x double> %val1, <4 x double> %val2, <4 x float> %val3, <4 x float> %val4, <4 x double> %val5, <4 x double> %val6) {
; CHECK-LABEL: fun34:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
; CHECK-NEXT: vmrlf [[REG0:%v[0-9]+]], %v27, %v27
; CHECK-NEXT: vmrlf [[REG1:%v[0-9]+]], %v25, %v25
; CHECK-NEXT: vldeb [[REG2:%v[0-9]+]], [[REG0]]
@@ -827,7 +827,7 @@ define <4 x double> @fun34(<4 x double> %val1, <4 x double> %val2, <4 x float> %
; CHECK-NEXT: br %r14
;
; CHECK-Z14-LABEL: fun34:
-; CHECK-Z14: # BB#0:
+; CHECK-Z14: # %bb.0:
; CHECK-Z14-NEXT: vfchsb %v4, %v25, %v27
; CHECK-Z14-NEXT: vuphf %v5, %v4
; CHECK-Z14-NEXT: vmrlg %v4, %v4, %v4
OpenPOWER on IntegriCloud