diff options
Diffstat (limited to 'llvm/test/CodeGen/SystemZ/Large')
| -rw-r--r-- | llvm/test/CodeGen/SystemZ/Large/branch-range-09.py | 107 | ||||
| -rw-r--r-- | llvm/test/CodeGen/SystemZ/Large/branch-range-10.py | 111 | ||||
| -rw-r--r-- | llvm/test/CodeGen/SystemZ/Large/branch-range-11.py | 127 | ||||
| -rw-r--r-- | llvm/test/CodeGen/SystemZ/Large/branch-range-12.py | 127 |
4 files changed, 472 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/SystemZ/Large/branch-range-09.py b/llvm/test/CodeGen/SystemZ/Large/branch-range-09.py new file mode 100644 index 00000000000..b3fd81324da --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/Large/branch-range-09.py @@ -0,0 +1,107 @@ +# Test 32-bit COMPARE LOGICAL AND BRANCH in cases where the sheer number of +# instructions causes some branches to be out of range. +# RUN: python %s | llc -mtriple=s390x-linux-gnu | FileCheck %s + +# Construct: +# +# before0: +# conditional branch to after0 +# ... +# beforeN: +# conditional branch to after0 +# main: +# 0xffcc bytes, from MVIY instructions +# conditional branch to main +# after0: +# ... +# conditional branch to main +# afterN: +# +# Each conditional branch sequence occupies 12 bytes if it uses a short +# branch and 14 if it uses a long one. The ones before "main:" have to +# take the branch length into account, which is 6 for short branches, +# so the final (0x34 - 6) / 12 == 3 blocks can use short branches. +# The ones after "main:" do not, so the first 0x34 / 12 == 4 blocks +# can use short branches. +# +# CHECK: lb [[REG:%r[0-5]]], 0(%r3) +# CHECK: clr %r4, [[REG]] +# CHECK: jgl [[LABEL:\.L[^ ]*]] +# CHECK: lb [[REG:%r[0-5]]], 1(%r3) +# CHECK: clr %r4, [[REG]] +# CHECK: jgl [[LABEL]] +# CHECK: lb [[REG:%r[0-5]]], 2(%r3) +# CHECK: clr %r4, [[REG]] +# CHECK: jgl [[LABEL]] +# CHECK: lb [[REG:%r[0-5]]], 3(%r3) +# CHECK: clr %r4, [[REG]] +# CHECK: jgl [[LABEL]] +# CHECK: lb [[REG:%r[0-5]]], 4(%r3) +# CHECK: clr %r4, [[REG]] +# CHECK: jgl [[LABEL]] +# CHECK: lb [[REG:%r[0-5]]], 5(%r3) +# CHECK: clrjl %r4, [[REG]], [[LABEL]] +# CHECK: lb [[REG:%r[0-5]]], 6(%r3) +# CHECK: clrjl %r4, [[REG]], [[LABEL]] +# CHECK: lb [[REG:%r[0-5]]], 7(%r3) +# CHECK: clrjl %r4, [[REG]], [[LABEL]] +# ...main goes here... +# CHECK: lb [[REG:%r[0-5]]], 25(%r3) +# CHECK: clrjl %r4, [[REG]], [[LABEL:\.L[^ ]*]] +# CHECK: lb [[REG:%r[0-5]]], 26(%r3) +# CHECK: clrjl %r4, [[REG]], [[LABEL]] +# CHECK: lb [[REG:%r[0-5]]], 27(%r3) +# CHECK: clrjl %r4, [[REG]], [[LABEL]] +# CHECK: lb [[REG:%r[0-5]]], 28(%r3) +# CHECK: clrjl %r4, [[REG]], [[LABEL]] +# CHECK: lb [[REG:%r[0-5]]], 29(%r3) +# CHECK: clr %r4, [[REG]] +# CHECK: jgl [[LABEL]] +# CHECK: lb [[REG:%r[0-5]]], 30(%r3) +# CHECK: clr %r4, [[REG]] +# CHECK: jgl [[LABEL]] +# CHECK: lb [[REG:%r[0-5]]], 31(%r3) +# CHECK: clr %r4, [[REG]] +# CHECK: jgl [[LABEL]] +# CHECK: lb [[REG:%r[0-5]]], 32(%r3) +# CHECK: clr %r4, [[REG]] +# CHECK: jgl [[LABEL]] + +branch_blocks = 8 +main_size = 0xffcc + +print 'define void @f1(i8 *%base, i8 *%stop, i32 %limit) {' +print 'entry:' +print ' br label %before0' +print '' + +for i in xrange(branch_blocks): + next = 'before%d' % (i + 1) if i + 1 < branch_blocks else 'main' + print 'before%d:' % i + print ' %%bstop%d = getelementptr i8 *%%stop, i64 %d' % (i, i) + print ' %%bcur%d = load volatile i8 *%%bstop%d' % (i, i) + print ' %%bext%d = sext i8 %%bcur%d to i32' % (i, i) + print ' %%btest%d = icmp ult i32 %%limit, %%bext%d' % (i, i) + print ' br i1 %%btest%d, label %%after0, label %%%s' % (i, next) + print '' + +print '%s:' % next +a, b = 1, 1 +for i in xrange(0, main_size, 6): + a, b = b, a + b + offset = 4096 + b % 500000 + value = a % 256 + print ' %%ptr%d = getelementptr i8 *%%base, i64 %d' % (i, offset) + print ' store volatile i8 %d, i8 *%%ptr%d' % (value, i) + +for i in xrange(branch_blocks): + print ' %%astop%d = getelementptr i8 *%%stop, i64 %d' % (i, i + 25) + print ' %%acur%d = load volatile i8 *%%astop%d' % (i, i) + print ' %%aext%d = sext i8 %%acur%d to i32' % (i, i) + print ' %%atest%d = icmp ult i32 %%limit, %%aext%d' % (i, i) + print ' br i1 %%atest%d, label %%main, label %%after%d' % (i, i) + print '' + print 'after%d:' % i + +print ' ret void' +print '}' diff --git a/llvm/test/CodeGen/SystemZ/Large/branch-range-10.py b/llvm/test/CodeGen/SystemZ/Large/branch-range-10.py new file mode 100644 index 00000000000..3aeea3ebccd --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/Large/branch-range-10.py @@ -0,0 +1,111 @@ +# Test 64-bit COMPARE LOGICAL AND BRANCH in cases where the sheer number of +# instructions causes some branches to be out of range. +# RUN: python %s | llc -mtriple=s390x-linux-gnu | FileCheck %s + +# Construct: +# +# before0: +# conditional branch to after0 +# ... +# beforeN: +# conditional branch to after0 +# main: +# 0xffcc bytes, from MVIY instructions +# conditional branch to main +# after0: +# ... +# conditional branch to main +# afterN: +# +# Each conditional branch sequence occupies 12 bytes if it uses a short +# branch and 16 if it uses a long one. The ones before "main:" have to +# take the branch length into account, which is 6 for short branches, +# so the final (0x34 - 6) / 12 == 3 blocks can use short branches. +# The ones after "main:" do not, so the first 0x34 / 12 == 4 blocks +# can use short branches. The conservative algorithm we use makes +# one of the forward branches unnecessarily long, as noted in the +# check output below. +# +# CHECK: lgb [[REG:%r[0-5]]], 0(%r3) +# CHECK: clgr %r4, [[REG]] +# CHECK: jgl [[LABEL:\.L[^ ]*]] +# CHECK: lgb [[REG:%r[0-5]]], 1(%r3) +# CHECK: clgr %r4, [[REG]] +# CHECK: jgl [[LABEL]] +# CHECK: lgb [[REG:%r[0-5]]], 2(%r3) +# CHECK: clgr %r4, [[REG]] +# CHECK: jgl [[LABEL]] +# CHECK: lgb [[REG:%r[0-5]]], 3(%r3) +# CHECK: clgr %r4, [[REG]] +# CHECK: jgl [[LABEL]] +# CHECK: lgb [[REG:%r[0-5]]], 4(%r3) +# CHECK: clgr %r4, [[REG]] +# CHECK: jgl [[LABEL]] +# ...as mentioned above, the next one could be a CLGRJL instead... +# CHECK: lgb [[REG:%r[0-5]]], 5(%r3) +# CHECK: clgr %r4, [[REG]] +# CHECK: jgl [[LABEL]] +# CHECK: lgb [[REG:%r[0-5]]], 6(%r3) +# CHECK: clgrjl %r4, [[REG]], [[LABEL]] +# CHECK: lgb [[REG:%r[0-5]]], 7(%r3) +# CHECK: clgrjl %r4, [[REG]], [[LABEL]] +# ...main goes here... +# CHECK: lgb [[REG:%r[0-5]]], 25(%r3) +# CHECK: clgrjl %r4, [[REG]], [[LABEL:\.L[^ ]*]] +# CHECK: lgb [[REG:%r[0-5]]], 26(%r3) +# CHECK: clgrjl %r4, [[REG]], [[LABEL]] +# CHECK: lgb [[REG:%r[0-5]]], 27(%r3) +# CHECK: clgrjl %r4, [[REG]], [[LABEL]] +# CHECK: lgb [[REG:%r[0-5]]], 28(%r3) +# CHECK: clgrjl %r4, [[REG]], [[LABEL]] +# CHECK: lgb [[REG:%r[0-5]]], 29(%r3) +# CHECK: clgr %r4, [[REG]] +# CHECK: jgl [[LABEL]] +# CHECK: lgb [[REG:%r[0-5]]], 30(%r3) +# CHECK: clgr %r4, [[REG]] +# CHECK: jgl [[LABEL]] +# CHECK: lgb [[REG:%r[0-5]]], 31(%r3) +# CHECK: clgr %r4, [[REG]] +# CHECK: jgl [[LABEL]] +# CHECK: lgb [[REG:%r[0-5]]], 32(%r3) +# CHECK: clgr %r4, [[REG]] +# CHECK: jgl [[LABEL]] + +branch_blocks = 8 +main_size = 0xffcc + +print 'define void @f1(i8 *%base, i8 *%stop, i64 %limit) {' +print 'entry:' +print ' br label %before0' +print '' + +for i in xrange(branch_blocks): + next = 'before%d' % (i + 1) if i + 1 < branch_blocks else 'main' + print 'before%d:' % i + print ' %%bstop%d = getelementptr i8 *%%stop, i64 %d' % (i, i) + print ' %%bcur%d = load volatile i8 *%%bstop%d' % (i, i) + print ' %%bext%d = sext i8 %%bcur%d to i64' % (i, i) + print ' %%btest%d = icmp ult i64 %%limit, %%bext%d' % (i, i) + print ' br i1 %%btest%d, label %%after0, label %%%s' % (i, next) + print '' + +print '%s:' % next +a, b = 1, 1 +for i in xrange(0, main_size, 6): + a, b = b, a + b + offset = 4096 + b % 500000 + value = a % 256 + print ' %%ptr%d = getelementptr i8 *%%base, i64 %d' % (i, offset) + print ' store volatile i8 %d, i8 *%%ptr%d' % (value, i) + +for i in xrange(branch_blocks): + print ' %%astop%d = getelementptr i8 *%%stop, i64 %d' % (i, i + 25) + print ' %%acur%d = load volatile i8 *%%astop%d' % (i, i) + print ' %%aext%d = sext i8 %%acur%d to i64' % (i, i) + print ' %%atest%d = icmp ult i64 %%limit, %%aext%d' % (i, i) + print ' br i1 %%atest%d, label %%main, label %%after%d' % (i, i) + print '' + print 'after%d:' % i + +print ' ret void' +print '}' diff --git a/llvm/test/CodeGen/SystemZ/Large/branch-range-11.py b/llvm/test/CodeGen/SystemZ/Large/branch-range-11.py new file mode 100644 index 00000000000..034902c4a34 --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/Large/branch-range-11.py @@ -0,0 +1,127 @@ +# Test 32-bit COMPARE LOGICAL IMMEDIATE AND BRANCH in cases where the sheer +# number of instructions causes some branches to be out of range. +# RUN: python %s | llc -mtriple=s390x-linux-gnu | FileCheck %s + +# Construct: +# +# before0: +# conditional branch to after0 +# ... +# beforeN: +# conditional branch to after0 +# main: +# 0xffc6 bytes, from MVIY instructions +# conditional branch to main +# after0: +# ... +# conditional branch to main +# afterN: +# +# Each conditional branch sequence occupies 14 bytes if it uses a short +# branch and 20 if it uses a long one. The ones before "main:" have to +# take the branch length into account, which is 6 for short branches, +# so the final (0x3a - 6) / 14 == 3 blocks can use short branches. +# The ones after "main:" do not, so the first 0x3a / 14 == 4 blocks +# can use short branches. The conservative algorithm we use makes +# one of the forward branches unnecessarily long, as noted in the +# check output below. +# +# CHECK: l [[REG:%r[0-5]]], 0(%r3) +# CHECK: s [[REG]], 0(%r4) +# CHECK: clfi [[REG]], 50 +# CHECK: jgl [[LABEL:\.L[^ ]*]] +# CHECK: l [[REG:%r[0-5]]], 0(%r3) +# CHECK: s [[REG]], 0(%r4) +# CHECK: clfi [[REG]], 51 +# CHECK: jgl [[LABEL]] +# CHECK: l [[REG:%r[0-5]]], 0(%r3) +# CHECK: s [[REG]], 0(%r4) +# CHECK: clfi [[REG]], 52 +# CHECK: jgl [[LABEL]] +# CHECK: l [[REG:%r[0-5]]], 0(%r3) +# CHECK: s [[REG]], 0(%r4) +# CHECK: clfi [[REG]], 53 +# CHECK: jgl [[LABEL]] +# CHECK: l [[REG:%r[0-5]]], 0(%r3) +# CHECK: s [[REG]], 0(%r4) +# CHECK: clfi [[REG]], 54 +# CHECK: jgl [[LABEL]] +# ...as mentioned above, the next one could be a CLIJL instead... +# CHECK: l [[REG:%r[0-5]]], 0(%r3) +# CHECK: s [[REG]], 0(%r4) +# CHECK: clfi [[REG]], 55 +# CHECK: jgl [[LABEL]] +# CHECK: l [[REG:%r[0-5]]], 0(%r3) +# CHECK: s [[REG]], 0(%r4) +# CHECK: clijl [[REG]], 56, [[LABEL]] +# CHECK: l [[REG:%r[0-5]]], 0(%r3) +# CHECK: s [[REG]], 0(%r4) +# CHECK: clijl [[REG]], 57, [[LABEL]] +# ...main goes here... +# CHECK: l [[REG:%r[0-5]]], 0(%r3) +# CHECK: s [[REG]], 0(%r4) +# CHECK: clijl [[REG]], 100, [[LABEL:\.L[^ ]*]] +# CHECK: l [[REG:%r[0-5]]], 0(%r3) +# CHECK: s [[REG]], 0(%r4) +# CHECK: clijl [[REG]], 101, [[LABEL]] +# CHECK: l [[REG:%r[0-5]]], 0(%r3) +# CHECK: s [[REG]], 0(%r4) +# CHECK: clijl [[REG]], 102, [[LABEL]] +# CHECK: l [[REG:%r[0-5]]], 0(%r3) +# CHECK: s [[REG]], 0(%r4) +# CHECK: clijl [[REG]], 103, [[LABEL]] +# CHECK: l [[REG:%r[0-5]]], 0(%r3) +# CHECK: s [[REG]], 0(%r4) +# CHECK: clfi [[REG]], 104 +# CHECK: jgl [[LABEL]] +# CHECK: l [[REG:%r[0-5]]], 0(%r3) +# CHECK: s [[REG]], 0(%r4) +# CHECK: clfi [[REG]], 105 +# CHECK: jgl [[LABEL]] +# CHECK: l [[REG:%r[0-5]]], 0(%r3) +# CHECK: s [[REG]], 0(%r4) +# CHECK: clfi [[REG]], 106 +# CHECK: jgl [[LABEL]] +# CHECK: l [[REG:%r[0-5]]], 0(%r3) +# CHECK: s [[REG]], 0(%r4) +# CHECK: clfi [[REG]], 107 +# CHECK: jgl [[LABEL]] + +branch_blocks = 8 +main_size = 0xffc6 + +print 'define void @f1(i8 *%base, i32 *%stopa, i32 *%stopb) {' +print 'entry:' +print ' br label %before0' +print '' + +for i in xrange(branch_blocks): + next = 'before%d' % (i + 1) if i + 1 < branch_blocks else 'main' + print 'before%d:' % i + print ' %%bcur%da = load volatile i32 *%%stopa' % i + print ' %%bcur%db = load volatile i32 *%%stopb' % i + print ' %%bsub%d = sub i32 %%bcur%da, %%bcur%db' % (i, i, i) + print ' %%btest%d = icmp ult i32 %%bsub%d, %d' % (i, i, i + 50) + print ' br i1 %%btest%d, label %%after0, label %%%s' % (i, next) + print '' + +print '%s:' % next +a, b = 1, 1 +for i in xrange(0, main_size, 6): + a, b = b, a + b + offset = 4096 + b % 500000 + value = a % 256 + print ' %%ptr%d = getelementptr i8 *%%base, i64 %d' % (i, offset) + print ' store volatile i8 %d, i8 *%%ptr%d' % (value, i) + +for i in xrange(branch_blocks): + print ' %%acur%da = load volatile i32 *%%stopa' % i + print ' %%acur%db = load volatile i32 *%%stopb' % i + print ' %%asub%d = sub i32 %%acur%da, %%acur%db' % (i, i, i) + print ' %%atest%d = icmp ult i32 %%asub%d, %d' % (i, i, i + 100) + print ' br i1 %%atest%d, label %%main, label %%after%d' % (i, i) + print '' + print 'after%d:' % i + +print ' ret void' +print '}' diff --git a/llvm/test/CodeGen/SystemZ/Large/branch-range-12.py b/llvm/test/CodeGen/SystemZ/Large/branch-range-12.py new file mode 100644 index 00000000000..007d477e214 --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/Large/branch-range-12.py @@ -0,0 +1,127 @@ +# Test 64-bit COMPARE LOGICAL IMMEDIATE AND BRANCH in cases where the sheer +# number of instructions causes some branches to be out of range. +# RUN: python %s | llc -mtriple=s390x-linux-gnu | FileCheck %s + +# Construct: +# +# before0: +# conditional branch to after0 +# ... +# beforeN: +# conditional branch to after0 +# main: +# 0xffb4 bytes, from MVIY instructions +# conditional branch to main +# after0: +# ... +# conditional branch to main +# afterN: +# +# Each conditional branch sequence occupies 18 bytes if it uses a short +# branch and 24 if it uses a long one. The ones before "main:" have to +# take the branch length into account, which is 6 for short branches, +# so the final (0x4c - 6) / 18 == 3 blocks can use short branches. +# The ones after "main:" do not, so the first 0x4c / 18 == 4 blocks +# can use short branches. The conservative algorithm we use makes +# one of the forward branches unnecessarily long, as noted in the +# check output below. +# +# CHECK: lg [[REG:%r[0-5]]], 0(%r3) +# CHECK: sg [[REG]], 0(%r4) +# CHECK: clgfi [[REG]], 50 +# CHECK: jgl [[LABEL:\.L[^ ]*]] +# CHECK: lg [[REG:%r[0-5]]], 0(%r3) +# CHECK: sg [[REG]], 0(%r4) +# CHECK: clgfi [[REG]], 51 +# CHECK: jgl [[LABEL]] +# CHECK: lg [[REG:%r[0-5]]], 0(%r3) +# CHECK: sg [[REG]], 0(%r4) +# CHECK: clgfi [[REG]], 52 +# CHECK: jgl [[LABEL]] +# CHECK: lg [[REG:%r[0-5]]], 0(%r3) +# CHECK: sg [[REG]], 0(%r4) +# CHECK: clgfi [[REG]], 53 +# CHECK: jgl [[LABEL]] +# CHECK: lg [[REG:%r[0-5]]], 0(%r3) +# CHECK: sg [[REG]], 0(%r4) +# CHECK: clgfi [[REG]], 54 +# CHECK: jgl [[LABEL]] +# ...as mentioned above, the next one could be a CLGIJL instead... +# CHECK: lg [[REG:%r[0-5]]], 0(%r3) +# CHECK: sg [[REG]], 0(%r4) +# CHECK: clgfi [[REG]], 55 +# CHECK: jgl [[LABEL]] +# CHECK: lg [[REG:%r[0-5]]], 0(%r3) +# CHECK: sg [[REG]], 0(%r4) +# CHECK: clgijl [[REG]], 56, [[LABEL]] +# CHECK: lg [[REG:%r[0-5]]], 0(%r3) +# CHECK: sg [[REG]], 0(%r4) +# CHECK: clgijl [[REG]], 57, [[LABEL]] +# ...main goes here... +# CHECK: lg [[REG:%r[0-5]]], 0(%r3) +# CHECK: sg [[REG]], 0(%r4) +# CHECK: clgijl [[REG]], 100, [[LABEL:\.L[^ ]*]] +# CHECK: lg [[REG:%r[0-5]]], 0(%r3) +# CHECK: sg [[REG]], 0(%r4) +# CHECK: clgijl [[REG]], 101, [[LABEL]] +# CHECK: lg [[REG:%r[0-5]]], 0(%r3) +# CHECK: sg [[REG]], 0(%r4) +# CHECK: clgijl [[REG]], 102, [[LABEL]] +# CHECK: lg [[REG:%r[0-5]]], 0(%r3) +# CHECK: sg [[REG]], 0(%r4) +# CHECK: clgijl [[REG]], 103, [[LABEL]] +# CHECK: lg [[REG:%r[0-5]]], 0(%r3) +# CHECK: sg [[REG]], 0(%r4) +# CHECK: clgfi [[REG]], 104 +# CHECK: jgl [[LABEL]] +# CHECK: lg [[REG:%r[0-5]]], 0(%r3) +# CHECK: sg [[REG]], 0(%r4) +# CHECK: clgfi [[REG]], 105 +# CHECK: jgl [[LABEL]] +# CHECK: lg [[REG:%r[0-5]]], 0(%r3) +# CHECK: sg [[REG]], 0(%r4) +# CHECK: clgfi [[REG]], 106 +# CHECK: jgl [[LABEL]] +# CHECK: lg [[REG:%r[0-5]]], 0(%r3) +# CHECK: sg [[REG]], 0(%r4) +# CHECK: clgfi [[REG]], 107 +# CHECK: jgl [[LABEL]] + +branch_blocks = 8 +main_size = 0xffb4 + +print 'define void @f1(i8 *%base, i64 *%stopa, i64 *%stopb) {' +print 'entry:' +print ' br label %before0' +print '' + +for i in xrange(branch_blocks): + next = 'before%d' % (i + 1) if i + 1 < branch_blocks else 'main' + print 'before%d:' % i + print ' %%bcur%da = load volatile i64 *%%stopa' % i + print ' %%bcur%db = load volatile i64 *%%stopb' % i + print ' %%bsub%d = sub i64 %%bcur%da, %%bcur%db' % (i, i, i) + print ' %%btest%d = icmp ult i64 %%bsub%d, %d' % (i, i, i + 50) + print ' br i1 %%btest%d, label %%after0, label %%%s' % (i, next) + print '' + +print '%s:' % next +a, b = 1, 1 +for i in xrange(0, main_size, 6): + a, b = b, a + b + offset = 4096 + b % 500000 + value = a % 256 + print ' %%ptr%d = getelementptr i8 *%%base, i64 %d' % (i, offset) + print ' store volatile i8 %d, i8 *%%ptr%d' % (value, i) + +for i in xrange(branch_blocks): + print ' %%acur%da = load volatile i64 *%%stopa' % i + print ' %%acur%db = load volatile i64 *%%stopb' % i + print ' %%asub%d = sub i64 %%acur%da, %%acur%db' % (i, i, i) + print ' %%atest%d = icmp ult i64 %%asub%d, %d' % (i, i, i + 100) + print ' br i1 %%atest%d, label %%main, label %%after%d' % (i, i) + print '' + print 'after%d:' % i + +print ' ret void' +print '}' |
