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-rw-r--r--llvm/test/CodeGen/RISCV/stack-realignment.ll186
1 files changed, 56 insertions, 130 deletions
diff --git a/llvm/test/CodeGen/RISCV/stack-realignment.ll b/llvm/test/CodeGen/RISCV/stack-realignment.ll
index dd06d6f0bff..c15e6e14b9a 100644
--- a/llvm/test/CodeGen/RISCV/stack-realignment.ll
+++ b/llvm/test/CodeGen/RISCV/stack-realignment.ll
@@ -309,20 +309,11 @@ define void @caller_no_realign512() nounwind "no-realign-stack" {
define void @caller1024() nounwind {
; RV32I-LABEL: caller1024:
; RV32I: # %bb.0:
-; RV32I-NEXT: lui a0, 1
-; RV32I-NEXT: addi a0, a0, -1024
-; RV32I-NEXT: sub sp, sp, a0
-; RV32I-NEXT: lui a0, 1
-; RV32I-NEXT: addi a0, a0, -1028
-; RV32I-NEXT: add a0, sp, a0
-; RV32I-NEXT: sw ra, 0(a0)
-; RV32I-NEXT: lui a0, 1
-; RV32I-NEXT: addi a0, a0, -1032
-; RV32I-NEXT: add a0, sp, a0
-; RV32I-NEXT: sw s0, 0(a0)
-; RV32I-NEXT: lui a0, 1
-; RV32I-NEXT: addi a0, a0, -1024
-; RV32I-NEXT: add s0, sp, a0
+; RV32I-NEXT: addi sp, sp, -2032
+; RV32I-NEXT: sw ra, 2028(sp)
+; RV32I-NEXT: sw s0, 2024(sp)
+; RV32I-NEXT: addi s0, sp, 2032
+; RV32I-NEXT: addi sp, sp, -1040
; RV32I-NEXT: andi sp, sp, -1024
; RV32I-NEXT: lui a0, 1
; RV32I-NEXT: addi a0, a0, -2048
@@ -332,35 +323,19 @@ define void @caller1024() nounwind {
; RV32I-NEXT: lui a0, 1
; RV32I-NEXT: addi a0, a0, -1024
; RV32I-NEXT: sub sp, s0, a0
-; RV32I-NEXT: lui a0, 1
-; RV32I-NEXT: addi a0, a0, -1032
-; RV32I-NEXT: add a0, sp, a0
-; RV32I-NEXT: lw s0, 0(a0)
-; RV32I-NEXT: lui a0, 1
-; RV32I-NEXT: addi a0, a0, -1028
-; RV32I-NEXT: add a0, sp, a0
-; RV32I-NEXT: lw ra, 0(a0)
-; RV32I-NEXT: lui a0, 1
-; RV32I-NEXT: addi a0, a0, -1024
-; RV32I-NEXT: add sp, sp, a0
+; RV32I-NEXT: addi sp, sp, 1040
+; RV32I-NEXT: lw s0, 2024(sp)
+; RV32I-NEXT: lw ra, 2028(sp)
+; RV32I-NEXT: addi sp, sp, 2032
; RV32I-NEXT: ret
;
; RV64I-LABEL: caller1024:
; RV64I: # %bb.0:
-; RV64I-NEXT: lui a0, 1
-; RV64I-NEXT: addiw a0, a0, -1024
-; RV64I-NEXT: sub sp, sp, a0
-; RV64I-NEXT: lui a0, 1
-; RV64I-NEXT: addiw a0, a0, -1032
-; RV64I-NEXT: add a0, sp, a0
-; RV64I-NEXT: sd ra, 0(a0)
-; RV64I-NEXT: lui a0, 1
-; RV64I-NEXT: addiw a0, a0, -1040
-; RV64I-NEXT: add a0, sp, a0
-; RV64I-NEXT: sd s0, 0(a0)
-; RV64I-NEXT: lui a0, 1
-; RV64I-NEXT: addiw a0, a0, -1024
-; RV64I-NEXT: add s0, sp, a0
+; RV64I-NEXT: addi sp, sp, -2032
+; RV64I-NEXT: sd ra, 2024(sp)
+; RV64I-NEXT: sd s0, 2016(sp)
+; RV64I-NEXT: addi s0, sp, 2032
+; RV64I-NEXT: addi sp, sp, -1040
; RV64I-NEXT: andi sp, sp, -1024
; RV64I-NEXT: lui a0, 1
; RV64I-NEXT: addiw a0, a0, -2048
@@ -370,17 +345,10 @@ define void @caller1024() nounwind {
; RV64I-NEXT: lui a0, 1
; RV64I-NEXT: addiw a0, a0, -1024
; RV64I-NEXT: sub sp, s0, a0
-; RV64I-NEXT: lui a0, 1
-; RV64I-NEXT: addiw a0, a0, -1040
-; RV64I-NEXT: add a0, sp, a0
-; RV64I-NEXT: ld s0, 0(a0)
-; RV64I-NEXT: lui a0, 1
-; RV64I-NEXT: addiw a0, a0, -1032
-; RV64I-NEXT: add a0, sp, a0
-; RV64I-NEXT: ld ra, 0(a0)
-; RV64I-NEXT: lui a0, 1
-; RV64I-NEXT: addiw a0, a0, -1024
-; RV64I-NEXT: add sp, sp, a0
+; RV64I-NEXT: addi sp, sp, 1040
+; RV64I-NEXT: ld s0, 2016(sp)
+; RV64I-NEXT: ld ra, 2024(sp)
+; RV64I-NEXT: addi sp, sp, 2032
; RV64I-NEXT: ret
%1 = alloca i8, align 1024
call void @callee(i8* %1)
@@ -415,20 +383,13 @@ define void @caller_no_realign1024() nounwind "no-realign-stack" {
define void @caller2048() nounwind {
; RV32I-LABEL: caller2048:
; RV32I: # %bb.0:
-; RV32I-NEXT: lui a0, 2
-; RV32I-NEXT: addi a0, a0, -2048
-; RV32I-NEXT: sub sp, sp, a0
+; RV32I-NEXT: addi sp, sp, -2032
+; RV32I-NEXT: sw ra, 2028(sp)
+; RV32I-NEXT: sw s0, 2024(sp)
+; RV32I-NEXT: addi s0, sp, 2032
; RV32I-NEXT: lui a0, 1
-; RV32I-NEXT: addi a0, a0, 2044
-; RV32I-NEXT: add a0, sp, a0
-; RV32I-NEXT: sw ra, 0(a0)
-; RV32I-NEXT: lui a0, 1
-; RV32I-NEXT: addi a0, a0, 2040
-; RV32I-NEXT: add a0, sp, a0
-; RV32I-NEXT: sw s0, 0(a0)
-; RV32I-NEXT: lui a0, 2
-; RV32I-NEXT: addi a0, a0, -2048
-; RV32I-NEXT: add s0, sp, a0
+; RV32I-NEXT: addi a0, a0, 16
+; RV32I-NEXT: sub sp, sp, a0
; RV32I-NEXT: andi sp, sp, -2048
; RV32I-NEXT: lui a0, 1
; RV32I-NEXT: add a0, sp, a0
@@ -438,34 +399,22 @@ define void @caller2048() nounwind {
; RV32I-NEXT: addi a0, a0, -2048
; RV32I-NEXT: sub sp, s0, a0
; RV32I-NEXT: lui a0, 1
-; RV32I-NEXT: addi a0, a0, 2040
-; RV32I-NEXT: add a0, sp, a0
-; RV32I-NEXT: lw s0, 0(a0)
-; RV32I-NEXT: lui a0, 1
-; RV32I-NEXT: addi a0, a0, 2044
-; RV32I-NEXT: add a0, sp, a0
-; RV32I-NEXT: lw ra, 0(a0)
-; RV32I-NEXT: lui a0, 2
-; RV32I-NEXT: addi a0, a0, -2048
+; RV32I-NEXT: addi a0, a0, 16
; RV32I-NEXT: add sp, sp, a0
+; RV32I-NEXT: lw s0, 2024(sp)
+; RV32I-NEXT: lw ra, 2028(sp)
+; RV32I-NEXT: addi sp, sp, 2032
; RV32I-NEXT: ret
;
; RV64I-LABEL: caller2048:
; RV64I: # %bb.0:
-; RV64I-NEXT: lui a0, 2
-; RV64I-NEXT: addiw a0, a0, -2048
-; RV64I-NEXT: sub sp, sp, a0
+; RV64I-NEXT: addi sp, sp, -2032
+; RV64I-NEXT: sd ra, 2024(sp)
+; RV64I-NEXT: sd s0, 2016(sp)
+; RV64I-NEXT: addi s0, sp, 2032
; RV64I-NEXT: lui a0, 1
-; RV64I-NEXT: addiw a0, a0, 2040
-; RV64I-NEXT: add a0, sp, a0
-; RV64I-NEXT: sd ra, 0(a0)
-; RV64I-NEXT: lui a0, 1
-; RV64I-NEXT: addiw a0, a0, 2032
-; RV64I-NEXT: add a0, sp, a0
-; RV64I-NEXT: sd s0, 0(a0)
-; RV64I-NEXT: lui a0, 2
-; RV64I-NEXT: addiw a0, a0, -2048
-; RV64I-NEXT: add s0, sp, a0
+; RV64I-NEXT: addiw a0, a0, 16
+; RV64I-NEXT: sub sp, sp, a0
; RV64I-NEXT: andi sp, sp, -2048
; RV64I-NEXT: lui a0, 1
; RV64I-NEXT: add a0, sp, a0
@@ -475,16 +424,11 @@ define void @caller2048() nounwind {
; RV64I-NEXT: addiw a0, a0, -2048
; RV64I-NEXT: sub sp, s0, a0
; RV64I-NEXT: lui a0, 1
-; RV64I-NEXT: addiw a0, a0, 2032
-; RV64I-NEXT: add a0, sp, a0
-; RV64I-NEXT: ld s0, 0(a0)
-; RV64I-NEXT: lui a0, 1
-; RV64I-NEXT: addiw a0, a0, 2040
-; RV64I-NEXT: add a0, sp, a0
-; RV64I-NEXT: ld ra, 0(a0)
-; RV64I-NEXT: lui a0, 2
-; RV64I-NEXT: addiw a0, a0, -2048
+; RV64I-NEXT: addiw a0, a0, 16
; RV64I-NEXT: add sp, sp, a0
+; RV64I-NEXT: ld s0, 2016(sp)
+; RV64I-NEXT: ld ra, 2024(sp)
+; RV64I-NEXT: addi sp, sp, 2032
; RV64I-NEXT: ret
%1 = alloca i8, align 2048
call void @callee(i8* %1)
@@ -519,18 +463,13 @@ define void @caller_no_realign2048() nounwind "no-realign-stack" {
define void @caller4096() nounwind {
; RV32I-LABEL: caller4096:
; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -2032
+; RV32I-NEXT: sw ra, 2028(sp)
+; RV32I-NEXT: sw s0, 2024(sp)
+; RV32I-NEXT: addi s0, sp, 2032
; RV32I-NEXT: lui a0, 3
+; RV32I-NEXT: addi a0, a0, -2032
; RV32I-NEXT: sub sp, sp, a0
-; RV32I-NEXT: lui a0, 3
-; RV32I-NEXT: addi a0, a0, -4
-; RV32I-NEXT: add a0, sp, a0
-; RV32I-NEXT: sw ra, 0(a0)
-; RV32I-NEXT: lui a0, 3
-; RV32I-NEXT: addi a0, a0, -8
-; RV32I-NEXT: add a0, sp, a0
-; RV32I-NEXT: sw s0, 0(a0)
-; RV32I-NEXT: lui a0, 3
-; RV32I-NEXT: add s0, sp, a0
; RV32I-NEXT: srli a0, sp, 12
; RV32I-NEXT: slli sp, a0, 12
; RV32I-NEXT: lui a0, 2
@@ -540,31 +479,22 @@ define void @caller4096() nounwind {
; RV32I-NEXT: lui a0, 3
; RV32I-NEXT: sub sp, s0, a0
; RV32I-NEXT: lui a0, 3
-; RV32I-NEXT: addi a0, a0, -8
-; RV32I-NEXT: add a0, sp, a0
-; RV32I-NEXT: lw s0, 0(a0)
-; RV32I-NEXT: lui a0, 3
-; RV32I-NEXT: addi a0, a0, -4
-; RV32I-NEXT: add a0, sp, a0
-; RV32I-NEXT: lw ra, 0(a0)
-; RV32I-NEXT: lui a0, 3
+; RV32I-NEXT: addi a0, a0, -2032
; RV32I-NEXT: add sp, sp, a0
+; RV32I-NEXT: lw s0, 2024(sp)
+; RV32I-NEXT: lw ra, 2028(sp)
+; RV32I-NEXT: addi sp, sp, 2032
; RV32I-NEXT: ret
;
; RV64I-LABEL: caller4096:
; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -2032
+; RV64I-NEXT: sd ra, 2024(sp)
+; RV64I-NEXT: sd s0, 2016(sp)
+; RV64I-NEXT: addi s0, sp, 2032
; RV64I-NEXT: lui a0, 3
+; RV64I-NEXT: addiw a0, a0, -2032
; RV64I-NEXT: sub sp, sp, a0
-; RV64I-NEXT: lui a0, 3
-; RV64I-NEXT: addiw a0, a0, -8
-; RV64I-NEXT: add a0, sp, a0
-; RV64I-NEXT: sd ra, 0(a0)
-; RV64I-NEXT: lui a0, 3
-; RV64I-NEXT: addiw a0, a0, -16
-; RV64I-NEXT: add a0, sp, a0
-; RV64I-NEXT: sd s0, 0(a0)
-; RV64I-NEXT: lui a0, 3
-; RV64I-NEXT: add s0, sp, a0
; RV64I-NEXT: srli a0, sp, 12
; RV64I-NEXT: slli sp, a0, 12
; RV64I-NEXT: lui a0, 2
@@ -574,15 +504,11 @@ define void @caller4096() nounwind {
; RV64I-NEXT: lui a0, 3
; RV64I-NEXT: sub sp, s0, a0
; RV64I-NEXT: lui a0, 3
-; RV64I-NEXT: addiw a0, a0, -16
-; RV64I-NEXT: add a0, sp, a0
-; RV64I-NEXT: ld s0, 0(a0)
-; RV64I-NEXT: lui a0, 3
-; RV64I-NEXT: addiw a0, a0, -8
-; RV64I-NEXT: add a0, sp, a0
-; RV64I-NEXT: ld ra, 0(a0)
-; RV64I-NEXT: lui a0, 3
+; RV64I-NEXT: addiw a0, a0, -2032
; RV64I-NEXT: add sp, sp, a0
+; RV64I-NEXT: ld s0, 2016(sp)
+; RV64I-NEXT: ld ra, 2024(sp)
+; RV64I-NEXT: addi sp, sp, 2032
; RV64I-NEXT: ret
%1 = alloca i8, align 4096
call void @callee(i8* %1)
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