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-rw-r--r--llvm/test/CodeGen/RISCV/shifts.ll114
1 files changed, 55 insertions, 59 deletions
diff --git a/llvm/test/CodeGen/RISCV/shifts.ll b/llvm/test/CodeGen/RISCV/shifts.ll
index 54c49f3f3ef..80cf136144d 100644
--- a/llvm/test/CodeGen/RISCV/shifts.ll
+++ b/llvm/test/CodeGen/RISCV/shifts.ll
@@ -17,14 +17,13 @@ define i64 @lshr64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB0_2:
-; RV32I-NEXT: srl a0, a0, a2
; RV32I-NEXT: addi a3, zero, 31
; RV32I-NEXT: sub a3, a3, a2
; RV32I-NEXT: slli a4, a1, 1
; RV32I-NEXT: sll a3, a4, a3
+; RV32I-NEXT: srl a0, a0, a2
; RV32I-NEXT: or a0, a0, a3
-; RV32I-NEXT: srl a2, a1, a2
-; RV32I-NEXT: mv a1, a2
+; RV32I-NEXT: srl a1, a1, a2
; RV32I-NEXT: ret
;
; RV64I-LABEL: lshr64:
@@ -63,11 +62,11 @@ define i64 @ashr64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: srai a1, a1, 31
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB2_2:
-; RV32I-NEXT: srl a0, a0, a2
; RV32I-NEXT: addi a3, zero, 31
; RV32I-NEXT: sub a3, a3, a2
; RV32I-NEXT: slli a4, a1, 1
; RV32I-NEXT: sll a3, a4, a3
+; RV32I-NEXT: srl a0, a0, a2
; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: sra a1, a1, a2
; RV32I-NEXT: ret
@@ -108,14 +107,13 @@ define i64 @shl64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB4_2:
-; RV32I-NEXT: sll a1, a1, a2
; RV32I-NEXT: addi a3, zero, 31
; RV32I-NEXT: sub a3, a3, a2
; RV32I-NEXT: srli a4, a0, 1
; RV32I-NEXT: srl a3, a4, a3
+; RV32I-NEXT: sll a1, a1, a2
; RV32I-NEXT: or a1, a1, a3
-; RV32I-NEXT: sll a2, a0, a2
-; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: sll a0, a0, a2
; RV32I-NEXT: ret
;
; RV64I-LABEL: shl64:
@@ -150,27 +148,27 @@ define i128 @lshr128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: sw ra, 44(sp)
; RV32I-NEXT: sw s0, 40(sp)
-; RV32I-NEXT: lw a2, 0(a2)
-; RV32I-NEXT: lw a3, 0(a1)
-; RV32I-NEXT: lw a4, 4(a1)
-; RV32I-NEXT: lw a5, 8(a1)
-; RV32I-NEXT: lw a1, 12(a1)
; RV32I-NEXT: mv s0, a0
-; RV32I-NEXT: sw a1, 20(sp)
-; RV32I-NEXT: sw a5, 16(sp)
-; RV32I-NEXT: sw a4, 12(sp)
+; RV32I-NEXT: lw a0, 12(a1)
+; RV32I-NEXT: sw a0, 20(sp)
+; RV32I-NEXT: lw a0, 8(a1)
+; RV32I-NEXT: sw a0, 16(sp)
+; RV32I-NEXT: lw a0, 4(a1)
+; RV32I-NEXT: sw a0, 12(sp)
+; RV32I-NEXT: lw a0, 0(a1)
+; RV32I-NEXT: sw a0, 8(sp)
+; RV32I-NEXT: lw a2, 0(a2)
; RV32I-NEXT: addi a0, sp, 24
; RV32I-NEXT: addi a1, sp, 8
-; RV32I-NEXT: sw a3, 8(sp)
; RV32I-NEXT: call __lshrti3
; RV32I-NEXT: lw a0, 36(sp)
-; RV32I-NEXT: lw a1, 32(sp)
-; RV32I-NEXT: lw a2, 28(sp)
-; RV32I-NEXT: lw a3, 24(sp)
; RV32I-NEXT: sw a0, 12(s0)
-; RV32I-NEXT: sw a1, 8(s0)
-; RV32I-NEXT: sw a2, 4(s0)
-; RV32I-NEXT: sw a3, 0(s0)
+; RV32I-NEXT: lw a0, 32(sp)
+; RV32I-NEXT: sw a0, 8(s0)
+; RV32I-NEXT: lw a0, 28(sp)
+; RV32I-NEXT: sw a0, 4(s0)
+; RV32I-NEXT: lw a0, 24(sp)
+; RV32I-NEXT: sw a0, 0(s0)
; RV32I-NEXT: lw s0, 40(sp)
; RV32I-NEXT: lw ra, 44(sp)
; RV32I-NEXT: addi sp, sp, 48
@@ -185,14 +183,13 @@ define i128 @lshr128(i128 %a, i128 %b) nounwind {
; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB6_2:
-; RV64I-NEXT: srl a0, a0, a2
; RV64I-NEXT: addi a3, zero, 63
; RV64I-NEXT: sub a3, a3, a2
; RV64I-NEXT: slli a4, a1, 1
; RV64I-NEXT: sll a3, a4, a3
+; RV64I-NEXT: srl a0, a0, a2
; RV64I-NEXT: or a0, a0, a3
-; RV64I-NEXT: srl a2, a1, a2
-; RV64I-NEXT: mv a1, a2
+; RV64I-NEXT: srl a1, a1, a2
; RV64I-NEXT: ret
%1 = lshr i128 %a, %b
ret i128 %1
@@ -204,27 +201,27 @@ define i128 @ashr128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: sw ra, 44(sp)
; RV32I-NEXT: sw s0, 40(sp)
-; RV32I-NEXT: lw a2, 0(a2)
-; RV32I-NEXT: lw a3, 0(a1)
-; RV32I-NEXT: lw a4, 4(a1)
-; RV32I-NEXT: lw a5, 8(a1)
-; RV32I-NEXT: lw a1, 12(a1)
; RV32I-NEXT: mv s0, a0
-; RV32I-NEXT: sw a1, 20(sp)
-; RV32I-NEXT: sw a5, 16(sp)
-; RV32I-NEXT: sw a4, 12(sp)
+; RV32I-NEXT: lw a0, 12(a1)
+; RV32I-NEXT: sw a0, 20(sp)
+; RV32I-NEXT: lw a0, 8(a1)
+; RV32I-NEXT: sw a0, 16(sp)
+; RV32I-NEXT: lw a0, 4(a1)
+; RV32I-NEXT: sw a0, 12(sp)
+; RV32I-NEXT: lw a0, 0(a1)
+; RV32I-NEXT: sw a0, 8(sp)
+; RV32I-NEXT: lw a2, 0(a2)
; RV32I-NEXT: addi a0, sp, 24
; RV32I-NEXT: addi a1, sp, 8
-; RV32I-NEXT: sw a3, 8(sp)
; RV32I-NEXT: call __ashrti3
; RV32I-NEXT: lw a0, 36(sp)
-; RV32I-NEXT: lw a1, 32(sp)
-; RV32I-NEXT: lw a2, 28(sp)
-; RV32I-NEXT: lw a3, 24(sp)
; RV32I-NEXT: sw a0, 12(s0)
-; RV32I-NEXT: sw a1, 8(s0)
-; RV32I-NEXT: sw a2, 4(s0)
-; RV32I-NEXT: sw a3, 0(s0)
+; RV32I-NEXT: lw a0, 32(sp)
+; RV32I-NEXT: sw a0, 8(s0)
+; RV32I-NEXT: lw a0, 28(sp)
+; RV32I-NEXT: sw a0, 4(s0)
+; RV32I-NEXT: lw a0, 24(sp)
+; RV32I-NEXT: sw a0, 0(s0)
; RV32I-NEXT: lw s0, 40(sp)
; RV32I-NEXT: lw ra, 44(sp)
; RV32I-NEXT: addi sp, sp, 48
@@ -239,11 +236,11 @@ define i128 @ashr128(i128 %a, i128 %b) nounwind {
; RV64I-NEXT: srai a1, a1, 63
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB7_2:
-; RV64I-NEXT: srl a0, a0, a2
; RV64I-NEXT: addi a3, zero, 63
; RV64I-NEXT: sub a3, a3, a2
; RV64I-NEXT: slli a4, a1, 1
; RV64I-NEXT: sll a3, a4, a3
+; RV64I-NEXT: srl a0, a0, a2
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: sra a1, a1, a2
; RV64I-NEXT: ret
@@ -257,27 +254,27 @@ define i128 @shl128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: sw ra, 44(sp)
; RV32I-NEXT: sw s0, 40(sp)
-; RV32I-NEXT: lw a2, 0(a2)
-; RV32I-NEXT: lw a3, 0(a1)
-; RV32I-NEXT: lw a4, 4(a1)
-; RV32I-NEXT: lw a5, 8(a1)
-; RV32I-NEXT: lw a1, 12(a1)
; RV32I-NEXT: mv s0, a0
-; RV32I-NEXT: sw a1, 20(sp)
-; RV32I-NEXT: sw a5, 16(sp)
-; RV32I-NEXT: sw a4, 12(sp)
+; RV32I-NEXT: lw a0, 12(a1)
+; RV32I-NEXT: sw a0, 20(sp)
+; RV32I-NEXT: lw a0, 8(a1)
+; RV32I-NEXT: sw a0, 16(sp)
+; RV32I-NEXT: lw a0, 4(a1)
+; RV32I-NEXT: sw a0, 12(sp)
+; RV32I-NEXT: lw a0, 0(a1)
+; RV32I-NEXT: sw a0, 8(sp)
+; RV32I-NEXT: lw a2, 0(a2)
; RV32I-NEXT: addi a0, sp, 24
; RV32I-NEXT: addi a1, sp, 8
-; RV32I-NEXT: sw a3, 8(sp)
; RV32I-NEXT: call __ashlti3
; RV32I-NEXT: lw a0, 36(sp)
-; RV32I-NEXT: lw a1, 32(sp)
-; RV32I-NEXT: lw a2, 28(sp)
-; RV32I-NEXT: lw a3, 24(sp)
; RV32I-NEXT: sw a0, 12(s0)
-; RV32I-NEXT: sw a1, 8(s0)
-; RV32I-NEXT: sw a2, 4(s0)
-; RV32I-NEXT: sw a3, 0(s0)
+; RV32I-NEXT: lw a0, 32(sp)
+; RV32I-NEXT: sw a0, 8(s0)
+; RV32I-NEXT: lw a0, 28(sp)
+; RV32I-NEXT: sw a0, 4(s0)
+; RV32I-NEXT: lw a0, 24(sp)
+; RV32I-NEXT: sw a0, 0(s0)
; RV32I-NEXT: lw s0, 40(sp)
; RV32I-NEXT: lw ra, 44(sp)
; RV32I-NEXT: addi sp, sp, 48
@@ -292,14 +289,13 @@ define i128 @shl128(i128 %a, i128 %b) nounwind {
; RV64I-NEXT: mv a0, zero
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB8_2:
-; RV64I-NEXT: sll a1, a1, a2
; RV64I-NEXT: addi a3, zero, 63
; RV64I-NEXT: sub a3, a3, a2
; RV64I-NEXT: srli a4, a0, 1
; RV64I-NEXT: srl a3, a4, a3
+; RV64I-NEXT: sll a1, a1, a2
; RV64I-NEXT: or a1, a1, a3
-; RV64I-NEXT: sll a2, a0, a2
-; RV64I-NEXT: mv a0, a2
+; RV64I-NEXT: sll a0, a0, a2
; RV64I-NEXT: ret
%1 = shl i128 %a, %b
ret i128 %1
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