1 files changed, 60 insertions, 86 deletions
diff --git a/llvm/test/CodeGen/RISCV/select-optimize-multiple.ll b/llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
index d38f3d57714..3a18b4a54ea 100644
--- a/llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
+++ b/llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
@@ -40,41 +40,27 @@ define i128 @cmovcc128(i64 signext %a, i128 %b, i128 %c) nounwind {
 ; RV32I-LABEL: cmovcc128:
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    xori a1, a1, 123
-; RV32I-NEXT:    or a2, a1, a2
-; RV32I-NEXT:    mv a1, a3
-; RV32I-NEXT:    beqz a2, .LBB1_2
+; RV32I-NEXT:    or a1, a1, a2
+; RV32I-NEXT:    beqz a1, .LBB1_2
 ; RV32I-NEXT:  # %bb.1: # %entry
-; RV32I-NEXT:    mv a1, a4
-; RV32I-NEXT:  .LBB1_2: # %entry
-; RV32I-NEXT:    lw a6, 0(a1)
-; RV32I-NEXT:    beqz a2, .LBB1_6
-; RV32I-NEXT:  # %bb.3: # %entry
 ; RV32I-NEXT:    addi a1, a4, 4
-; RV32I-NEXT:    lw a5, 0(a1)
-; RV32I-NEXT:    bnez a2, .LBB1_7
-; RV32I-NEXT:  .LBB1_4:
-; RV32I-NEXT:    addi a1, a3, 8
-; RV32I-NEXT:    lw a1, 0(a1)
-; RV32I-NEXT:    bnez a2, .LBB1_8
-; RV32I-NEXT:  .LBB1_5:
-; RV32I-NEXT:    addi a2, a3, 12
-; RV32I-NEXT:    j .LBB1_9
-; RV32I-NEXT:  .LBB1_6:
+; RV32I-NEXT:    addi a2, a4, 8
+; RV32I-NEXT:    addi a5, a4, 12
+; RV32I-NEXT:    mv a3, a4
+; RV32I-NEXT:    j .LBB1_3
+; RV32I-NEXT:  .LBB1_2:
 ; RV32I-NEXT:    addi a1, a3, 4
-; RV32I-NEXT:    lw a5, 0(a1)
-; RV32I-NEXT:    beqz a2, .LBB1_4
-; RV32I-NEXT:  .LBB1_7: # %entry
-; RV32I-NEXT:    addi a1, a4, 8
-; RV32I-NEXT:    lw a1, 0(a1)
-; RV32I-NEXT:    beqz a2, .LBB1_5
-; RV32I-NEXT:  .LBB1_8: # %entry
-; RV32I-NEXT:    addi a2, a4, 12
-; RV32I-NEXT:  .LBB1_9: # %entry
+; RV32I-NEXT:    addi a2, a3, 8
+; RV32I-NEXT:    addi a5, a3, 12
+; RV32I-NEXT:  .LBB1_3: # %entry
+; RV32I-NEXT:    lw a4, 0(a5)
+; RV32I-NEXT:    sw a4, 12(a0)
 ; RV32I-NEXT:    lw a2, 0(a2)
-; RV32I-NEXT:    sw a2, 12(a0)
-; RV32I-NEXT:    sw a1, 8(a0)
-; RV32I-NEXT:    sw a5, 4(a0)
-; RV32I-NEXT:    sw a6, 0(a0)
+; RV32I-NEXT:    sw a2, 8(a0)
+; RV32I-NEXT:    lw a1, 0(a1)
+; RV32I-NEXT:    sw a1, 4(a0)
+; RV32I-NEXT:    lw a1, 0(a3)
+; RV32I-NEXT:    sw a1, 0(a0)
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: cmovcc128:
@@ -97,24 +83,24 @@ entry:
 define i64 @cmov64(i1 %a, i64 %b, i64 %c) nounwind {
 ; RV32I-LABEL: cmov64:
 ; RV32I:       # %bb.0: # %entry
-; RV32I-NEXT:    andi a5, a0, 1
-; RV32I-NEXT:    mv a0, a1
-; RV32I-NEXT:    bnez a5, .LBB2_2
+; RV32I-NEXT:    andi a0, a0, 1
+; RV32I-NEXT:    bnez a0, .LBB2_2
 ; RV32I-NEXT:  # %bb.1: # %entry
-; RV32I-NEXT:    mv a0, a3
+; RV32I-NEXT:    mv a1, a3
 ; RV32I-NEXT:    mv a2, a4
 ; RV32I-NEXT:  .LBB2_2: # %entry
+; RV32I-NEXT:    mv a0, a1
 ; RV32I-NEXT:    mv a1, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: cmov64:
 ; RV64I:       # %bb.0: # %entry
-; RV64I-NEXT:    andi a3, a0, 1
-; RV64I-NEXT:    mv a0, a1
-; RV64I-NEXT:    bnez a3, .LBB2_2
+; RV64I-NEXT:    andi a0, a0, 1
+; RV64I-NEXT:    bnez a0, .LBB2_2
 ; RV64I-NEXT:  # %bb.1: # %entry
-; RV64I-NEXT:    mv a0, a2
+; RV64I-NEXT:    mv a1, a2
 ; RV64I-NEXT:  .LBB2_2: # %entry
+; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:    ret
 entry:
   %cond = select i1 %a, i64 %b, i64 %c
@@ -124,52 +110,38 @@ entry:
 define i128 @cmov128(i1 %a, i128 %b, i128 %c) nounwind {
 ; RV32I-LABEL: cmov128:
 ; RV32I:       # %bb.0: # %entry
-; RV32I-NEXT:    andi a4, a1, 1
-; RV32I-NEXT:    mv a1, a2
-; RV32I-NEXT:    bnez a4, .LBB3_2
+; RV32I-NEXT:    andi a1, a1, 1
+; RV32I-NEXT:    bnez a1, .LBB3_2
 ; RV32I-NEXT:  # %bb.1: # %entry
-; RV32I-NEXT:    mv a1, a3
-; RV32I-NEXT:  .LBB3_2: # %entry
-; RV32I-NEXT:    lw a6, 0(a1)
-; RV32I-NEXT:    bnez a4, .LBB3_6
-; RV32I-NEXT:  # %bb.3: # %entry
 ; RV32I-NEXT:    addi a1, a3, 4
-; RV32I-NEXT:    lw a5, 0(a1)
-; RV32I-NEXT:    beqz a4, .LBB3_7
-; RV32I-NEXT:  .LBB3_4:
-; RV32I-NEXT:    addi a1, a2, 8
-; RV32I-NEXT:    lw a1, 0(a1)
-; RV32I-NEXT:    beqz a4, .LBB3_8
-; RV32I-NEXT:  .LBB3_5:
-; RV32I-NEXT:    addi a2, a2, 12
-; RV32I-NEXT:    j .LBB3_9
-; RV32I-NEXT:  .LBB3_6:
+; RV32I-NEXT:    addi a4, a3, 8
+; RV32I-NEXT:    addi a5, a3, 12
+; RV32I-NEXT:    mv a2, a3
+; RV32I-NEXT:    j .LBB3_3
+; RV32I-NEXT:  .LBB3_2:
 ; RV32I-NEXT:    addi a1, a2, 4
-; RV32I-NEXT:    lw a5, 0(a1)
-; RV32I-NEXT:    bnez a4, .LBB3_4
-; RV32I-NEXT:  .LBB3_7: # %entry
-; RV32I-NEXT:    addi a1, a3, 8
+; RV32I-NEXT:    addi a4, a2, 8
+; RV32I-NEXT:    addi a5, a2, 12
+; RV32I-NEXT:  .LBB3_3: # %entry
+; RV32I-NEXT:    lw a3, 0(a5)
+; RV32I-NEXT:    sw a3, 12(a0)
+; RV32I-NEXT:    lw a3, 0(a4)
+; RV32I-NEXT:    sw a3, 8(a0)
 ; RV32I-NEXT:    lw a1, 0(a1)
-; RV32I-NEXT:    bnez a4, .LBB3_5
-; RV32I-NEXT:  .LBB3_8: # %entry
-; RV32I-NEXT:    addi a2, a3, 12
-; RV32I-NEXT:  .LBB3_9: # %entry
-; RV32I-NEXT:    lw a2, 0(a2)
-; RV32I-NEXT:    sw a2, 12(a0)
-; RV32I-NEXT:    sw a1, 8(a0)
-; RV32I-NEXT:    sw a5, 4(a0)
-; RV32I-NEXT:    sw a6, 0(a0)
+; RV32I-NEXT:    sw a1, 4(a0)
+; RV32I-NEXT:    lw a1, 0(a2)
+; RV32I-NEXT:    sw a1, 0(a0)
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: cmov128:
 ; RV64I:       # %bb.0: # %entry
-; RV64I-NEXT:    andi a5, a0, 1
-; RV64I-NEXT:    mv a0, a1
-; RV64I-NEXT:    bnez a5, .LBB3_2
+; RV64I-NEXT:    andi a0, a0, 1
+; RV64I-NEXT:    bnez a0, .LBB3_2
 ; RV64I-NEXT:  # %bb.1: # %entry
-; RV64I-NEXT:    mv a0, a3
+; RV64I-NEXT:    mv a1, a3
 ; RV64I-NEXT:    mv a2, a4
 ; RV64I-NEXT:  .LBB3_2: # %entry
+; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:    mv a1, a2
 ; RV64I-NEXT:    ret
 entry:
@@ -308,37 +280,39 @@ entry:
 define i32 @cmovdiffcc(i1 %a, i1 %b, i32 %c, i32 %d, i32 %e, i32 %f) nounwind {
 ; RV32I-LABEL: cmovdiffcc:
 ; RV32I:       # %bb.0: # %entry
-; RV32I-NEXT:    andi a0, a0, 1
 ; RV32I-NEXT:    andi a1, a1, 1
-; RV32I-NEXT:    beqz a0, .LBB7_3
+; RV32I-NEXT:    beqz a1, .LBB7_3
 ; RV32I-NEXT:  # %bb.1: # %entry
-; RV32I-NEXT:    beqz a1, .LBB7_4
+; RV32I-NEXT:    andi a0, a0, 1
+; RV32I-NEXT:    beqz a0, .LBB7_4
 ; RV32I-NEXT:  .LBB7_2: # %entry
 ; RV32I-NEXT:    add a0, a2, a4
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB7_3: # %entry
-; RV32I-NEXT:    mv a2, a3
-; RV32I-NEXT:    bnez a1, .LBB7_2
-; RV32I-NEXT:  .LBB7_4: # %entry
 ; RV32I-NEXT:    mv a4, a5
+; RV32I-NEXT:    andi a0, a0, 1
+; RV32I-NEXT:    bnez a0, .LBB7_2
+; RV32I-NEXT:  .LBB7_4: # %entry
+; RV32I-NEXT:    mv a2, a3
 ; RV32I-NEXT:    add a0, a2, a4
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: cmovdiffcc:
 ; RV64I:       # %bb.0: # %entry
-; RV64I-NEXT:    andi a0, a0, 1
 ; RV64I-NEXT:    andi a1, a1, 1
-; RV64I-NEXT:    beqz a0, .LBB7_3
+; RV64I-NEXT:    beqz a1, .LBB7_3
 ; RV64I-NEXT:  # %bb.1: # %entry
-; RV64I-NEXT:    beqz a1, .LBB7_4
+; RV64I-NEXT:    andi a0, a0, 1
+; RV64I-NEXT:    beqz a0, .LBB7_4
 ; RV64I-NEXT:  .LBB7_2: # %entry
 ; RV64I-NEXT:    addw a0, a2, a4
 ; RV64I-NEXT:    ret
 ; RV64I-NEXT:  .LBB7_3: # %entry
-; RV64I-NEXT:    mv a2, a3
-; RV64I-NEXT:    bnez a1, .LBB7_2
-; RV64I-NEXT:  .LBB7_4: # %entry
 ; RV64I-NEXT:    mv a4, a5
+; RV64I-NEXT:    andi a0, a0, 1
+; RV64I-NEXT:    bnez a0, .LBB7_2
+; RV64I-NEXT:  .LBB7_4: # %entry
+; RV64I-NEXT:    mv a2, a3
 ; RV64I-NEXT:    addw a0, a2, a4
 ; RV64I-NEXT:    ret
 entry: