1 files changed, 43 insertions, 43 deletions
diff --git a/llvm/test/CodeGen/RISCV/fp128.ll b/llvm/test/CodeGen/RISCV/fp128.ll
index 91b1702911a..a928d69fe9e 100644
--- a/llvm/test/CodeGen/RISCV/fp128.ll
+++ b/llvm/test/CodeGen/RISCV/fp128.ll
@@ -13,28 +13,28 @@ define i32 @test_load_and_cmp() nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -48
 ; RV32I-NEXT:    sw ra, 44(sp)
-; RV32I-NEXT:    lui a0, %hi(x)
-; RV32I-NEXT:    addi a1, a0, %lo(x)
-; RV32I-NEXT:    lw a6, 4(a1)
-; RV32I-NEXT:    lw a7, 8(a1)
-; RV32I-NEXT:    lw a1, 12(a1)
-; RV32I-NEXT:    lw a0, %lo(x)(a0)
-; RV32I-NEXT:    lui a4, %hi(y)
-; RV32I-NEXT:    addi a5, a4, %lo(y)
-; RV32I-NEXT:    lw a2, 4(a5)
-; RV32I-NEXT:    lw a3, 8(a5)
-; RV32I-NEXT:    lw a5, 12(a5)
-; RV32I-NEXT:    lw a4, %lo(y)(a4)
-; RV32I-NEXT:    sw a4, 8(sp)
-; RV32I-NEXT:    sw a0, 24(sp)
-; RV32I-NEXT:    sw a5, 20(sp)
-; RV32I-NEXT:    sw a3, 16(sp)
-; RV32I-NEXT:    sw a2, 12(sp)
+; RV32I-NEXT:    lui a0, %hi(y)
+; RV32I-NEXT:    lw a1, %lo(y)(a0)
+; RV32I-NEXT:    sw a1, 8(sp)
+; RV32I-NEXT:    lui a1, %hi(x)
+; RV32I-NEXT:    lw a2, %lo(x)(a1)
+; RV32I-NEXT:    sw a2, 24(sp)
+; RV32I-NEXT:    addi a0, a0, %lo(y)
+; RV32I-NEXT:    lw a2, 12(a0)
+; RV32I-NEXT:    sw a2, 20(sp)
+; RV32I-NEXT:    lw a2, 8(a0)
+; RV32I-NEXT:    sw a2, 16(sp)
+; RV32I-NEXT:    lw a0, 4(a0)
+; RV32I-NEXT:    sw a0, 12(sp)
+; RV32I-NEXT:    addi a0, a1, %lo(x)
+; RV32I-NEXT:    lw a1, 12(a0)
 ; RV32I-NEXT:    sw a1, 36(sp)
-; RV32I-NEXT:    sw a7, 32(sp)
+; RV32I-NEXT:    lw a1, 8(a0)
+; RV32I-NEXT:    sw a1, 32(sp)
+; RV32I-NEXT:    lw a0, 4(a0)
+; RV32I-NEXT:    sw a0, 28(sp)
 ; RV32I-NEXT:    addi a0, sp, 24
 ; RV32I-NEXT:    addi a1, sp, 8
-; RV32I-NEXT:    sw a6, 28(sp)
 ; RV32I-NEXT:    call __netf2
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    lw ra, 44(sp)
@@ -52,39 +52,39 @@ define i32 @test_add_and_fptosi() nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -80
 ; RV32I-NEXT:    sw ra, 76(sp)
-; RV32I-NEXT:    lui a0, %hi(x)
-; RV32I-NEXT:    addi a1, a0, %lo(x)
-; RV32I-NEXT:    lw a6, 4(a1)
-; RV32I-NEXT:    lw a7, 8(a1)
-; RV32I-NEXT:    lw a1, 12(a1)
-; RV32I-NEXT:    lw a0, %lo(x)(a0)
-; RV32I-NEXT:    lui a4, %hi(y)
-; RV32I-NEXT:    addi a5, a4, %lo(y)
-; RV32I-NEXT:    lw a3, 4(a5)
-; RV32I-NEXT:    lw a2, 8(a5)
-; RV32I-NEXT:    lw a5, 12(a5)
-; RV32I-NEXT:    lw a4, %lo(y)(a4)
-; RV32I-NEXT:    sw a4, 24(sp)
-; RV32I-NEXT:    sw a0, 40(sp)
-; RV32I-NEXT:    sw a5, 36(sp)
+; RV32I-NEXT:    lui a0, %hi(y)
+; RV32I-NEXT:    lw a1, %lo(y)(a0)
+; RV32I-NEXT:    sw a1, 24(sp)
+; RV32I-NEXT:    lui a1, %hi(x)
+; RV32I-NEXT:    lw a2, %lo(x)(a1)
+; RV32I-NEXT:    sw a2, 40(sp)
+; RV32I-NEXT:    addi a0, a0, %lo(y)
+; RV32I-NEXT:    lw a2, 12(a0)
+; RV32I-NEXT:    sw a2, 36(sp)
+; RV32I-NEXT:    lw a2, 8(a0)
 ; RV32I-NEXT:    sw a2, 32(sp)
-; RV32I-NEXT:    sw a3, 28(sp)
+; RV32I-NEXT:    lw a0, 4(a0)
+; RV32I-NEXT:    sw a0, 28(sp)
+; RV32I-NEXT:    addi a0, a1, %lo(x)
+; RV32I-NEXT:    lw a1, 12(a0)
 ; RV32I-NEXT:    sw a1, 52(sp)
-; RV32I-NEXT:    sw a7, 48(sp)
+; RV32I-NEXT:    lw a1, 8(a0)
+; RV32I-NEXT:    sw a1, 48(sp)
+; RV32I-NEXT:    lw a0, 4(a0)
+; RV32I-NEXT:    sw a0, 44(sp)
 ; RV32I-NEXT:    addi a0, sp, 56
 ; RV32I-NEXT:    addi a1, sp, 40
 ; RV32I-NEXT:    addi a2, sp, 24
-; RV32I-NEXT:    sw a6, 44(sp)
 ; RV32I-NEXT:    call __addtf3
-; RV32I-NEXT:    lw a1, 56(sp)
+; RV32I-NEXT:    lw a0, 68(sp)
+; RV32I-NEXT:    sw a0, 20(sp)
+; RV32I-NEXT:    lw a0, 64(sp)
+; RV32I-NEXT:    sw a0, 16(sp)
 ; RV32I-NEXT:    lw a0, 60(sp)
-; RV32I-NEXT:    lw a2, 64(sp)
-; RV32I-NEXT:    lw a3, 68(sp)
-; RV32I-NEXT:    sw a3, 20(sp)
-; RV32I-NEXT:    sw a2, 16(sp)
 ; RV32I-NEXT:    sw a0, 12(sp)
+; RV32I-NEXT:    lw a0, 56(sp)
+; RV32I-NEXT:    sw a0, 8(sp)
 ; RV32I-NEXT:    addi a0, sp, 8
-; RV32I-NEXT:    sw a1, 8(sp)
 ; RV32I-NEXT:    call __fixtfsi
 ; RV32I-NEXT:    lw ra, 76(sp)
 ; RV32I-NEXT:    addi sp, sp, 80