diff options
Diffstat (limited to 'llvm/test/CodeGen/RISCV/atomic-rmw.ll')
| -rw-r--r-- | llvm/test/CodeGen/RISCV/atomic-rmw.ll | 10596 |
1 files changed, 5238 insertions, 5358 deletions
diff --git a/llvm/test/CodeGen/RISCV/atomic-rmw.ll b/llvm/test/CodeGen/RISCV/atomic-rmw.ll index dc396efd530..c12a298b15e 100644 --- a/llvm/test/CodeGen/RISCV/atomic-rmw.ll +++ b/llvm/test/CodeGen/RISCV/atomic-rmw.ll @@ -21,23 +21,23 @@ define i8 @atomicrmw_xchg_i8_monotonic(i8* %a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_xchg_i8_monotonic: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a3, a3, a0 +; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a4, (a2) +; RV32IA-NEXT: lr.w a4, (a0) ; RV32IA-NEXT: add a5, zero, a1 ; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: sc.w a5, a5, (a2) +; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB0_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a4, a0 +; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_i8_monotonic: @@ -52,23 +52,23 @@ define i8 @atomicrmw_xchg_i8_monotonic(i8* %a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_xchg_i8_monotonic: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a3, a3, a0 +; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w a4, (a2) +; RV64IA-NEXT: lr.w a4, (a0) ; RV64IA-NEXT: add a5, zero, a1 ; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: xor a5, a4, a5 -; RV64IA-NEXT: sc.w a5, a5, (a2) +; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB0_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a4, a0 +; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: ret %1 = atomicrmw xchg i8* %a, i8 %b monotonic ret i8 %1 @@ -87,23 +87,23 @@ define i8 @atomicrmw_xchg_i8_acquire(i8* %a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_xchg_i8_acquire: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a3, a3, a0 +; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aq a4, (a2) +; RV32IA-NEXT: lr.w.aq a4, (a0) ; RV32IA-NEXT: add a5, zero, a1 ; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: sc.w a5, a5, (a2) +; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB1_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a4, a0 +; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_i8_acquire: @@ -118,23 +118,23 @@ define i8 @atomicrmw_xchg_i8_acquire(i8* %a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_xchg_i8_acquire: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a3, a3, a0 +; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aq a4, (a2) +; RV64IA-NEXT: lr.w.aq a4, (a0) ; RV64IA-NEXT: add a5, zero, a1 ; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: xor a5, a4, a5 -; RV64IA-NEXT: sc.w a5, a5, (a2) +; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB1_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a4, a0 +; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: ret %1 = atomicrmw xchg i8* %a, i8 %b acquire ret i8 %1 @@ -153,23 +153,23 @@ define i8 @atomicrmw_xchg_i8_release(i8* %a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_xchg_i8_release: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a3, a3, a0 +; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a4, (a2) +; RV32IA-NEXT: lr.w a4, (a0) ; RV32IA-NEXT: add a5, zero, a1 ; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB2_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a4, a0 +; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_i8_release: @@ -184,23 +184,23 @@ define i8 @atomicrmw_xchg_i8_release(i8* %a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_xchg_i8_release: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a3, a3, a0 +; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w a4, (a2) +; RV64IA-NEXT: lr.w a4, (a0) ; RV64IA-NEXT: add a5, zero, a1 ; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: xor a5, a4, a5 -; RV64IA-NEXT: sc.w.rl a5, a5, (a2) +; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB2_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a4, a0 +; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: ret %1 = atomicrmw xchg i8* %a, i8 %b release ret i8 %1 @@ -219,23 +219,23 @@ define i8 @atomicrmw_xchg_i8_acq_rel(i8* %a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_xchg_i8_acq_rel: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a3, a3, a0 +; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aq a4, (a2) +; RV32IA-NEXT: lr.w.aq a4, (a0) ; RV32IA-NEXT: add a5, zero, a1 ; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB3_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a4, a0 +; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_i8_acq_rel: @@ -250,23 +250,23 @@ define i8 @atomicrmw_xchg_i8_acq_rel(i8* %a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_xchg_i8_acq_rel: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a3, a3, a0 +; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aq a4, (a2) +; RV64IA-NEXT: lr.w.aq a4, (a0) ; RV64IA-NEXT: add a5, zero, a1 ; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: xor a5, a4, a5 -; RV64IA-NEXT: sc.w.rl a5, a5, (a2) +; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB3_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a4, a0 +; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: ret %1 = atomicrmw xchg i8* %a, i8 %b acq_rel ret i8 %1 @@ -285,23 +285,23 @@ define i8 @atomicrmw_xchg_i8_seq_cst(i8* %a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_xchg_i8_seq_cst: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a3, a3, a0 +; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aqrl a4, (a2) +; RV32IA-NEXT: lr.w.aqrl a4, (a0) ; RV32IA-NEXT: add a5, zero, a1 ; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: sc.w.aqrl a5, a5, (a2) +; RV32IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB4_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a4, a0 +; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_i8_seq_cst: @@ -316,23 +316,23 @@ define i8 @atomicrmw_xchg_i8_seq_cst(i8* %a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_xchg_i8_seq_cst: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a3, a3, a0 +; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aqrl a4, (a2) +; RV64IA-NEXT: lr.w.aqrl a4, (a0) ; RV64IA-NEXT: add a5, zero, a1 ; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: xor a5, a4, a5 -; RV64IA-NEXT: sc.w.aqrl a5, a5, (a2) +; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB4_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a4, a0 +; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: ret %1 = atomicrmw xchg i8* %a, i8 %b seq_cst ret i8 %1 @@ -351,23 +351,23 @@ define i8 @atomicrmw_add_i8_monotonic(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_add_i8_monotonic: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a3, a3, a0 +; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a4, (a2) +; RV32IA-NEXT: lr.w a4, (a0) ; RV32IA-NEXT: add a5, a4, a1 ; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: sc.w a5, a5, (a2) +; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB5_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a4, a0 +; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_add_i8_monotonic: @@ -382,23 +382,23 @@ define i8 @atomicrmw_add_i8_monotonic(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_add_i8_monotonic: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a3, a3, a0 +; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w a4, (a2) +; RV64IA-NEXT: lr.w a4, (a0) ; RV64IA-NEXT: add a5, a4, a1 ; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: xor a5, a4, a5 -; RV64IA-NEXT: sc.w a5, a5, (a2) +; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB5_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a4, a0 +; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: ret %1 = atomicrmw add i8* %a, i8 %b monotonic ret i8 %1 @@ -417,23 +417,23 @@ define i8 @atomicrmw_add_i8_acquire(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_add_i8_acquire: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a3, a3, a0 +; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aq a4, (a2) +; RV32IA-NEXT: lr.w.aq a4, (a0) ; RV32IA-NEXT: add a5, a4, a1 ; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: sc.w a5, a5, (a2) +; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB6_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a4, a0 +; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_add_i8_acquire: @@ -448,23 +448,23 @@ define i8 @atomicrmw_add_i8_acquire(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_add_i8_acquire: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a3, a3, a0 +; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aq a4, (a2) +; RV64IA-NEXT: lr.w.aq a4, (a0) ; RV64IA-NEXT: add a5, a4, a1 ; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: xor a5, a4, a5 -; RV64IA-NEXT: sc.w a5, a5, (a2) +; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB6_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a4, a0 +; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: ret %1 = atomicrmw add i8* %a, i8 %b acquire ret i8 %1 @@ -483,23 +483,23 @@ define i8 @atomicrmw_add_i8_release(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_add_i8_release: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a3, a3, a0 +; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a4, (a2) +; RV32IA-NEXT: lr.w a4, (a0) ; RV32IA-NEXT: add a5, a4, a1 ; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB7_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a4, a0 +; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_add_i8_release: @@ -514,23 +514,23 @@ define i8 @atomicrmw_add_i8_release(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_add_i8_release: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a3, a3, a0 +; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w a4, (a2) +; RV64IA-NEXT: lr.w a4, (a0) ; RV64IA-NEXT: add a5, a4, a1 ; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: xor a5, a4, a5 -; RV64IA-NEXT: sc.w.rl a5, a5, (a2) +; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB7_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a4, a0 +; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: ret %1 = atomicrmw add i8* %a, i8 %b release ret i8 %1 @@ -549,23 +549,23 @@ define i8 @atomicrmw_add_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_add_i8_acq_rel: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a3, a3, a0 +; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aq a4, (a2) +; RV32IA-NEXT: lr.w.aq a4, (a0) ; RV32IA-NEXT: add a5, a4, a1 ; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB8_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a4, a0 +; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_add_i8_acq_rel: @@ -580,23 +580,23 @@ define i8 @atomicrmw_add_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_add_i8_acq_rel: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a3, a3, a0 +; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aq a4, (a2) +; RV64IA-NEXT: lr.w.aq a4, (a0) ; RV64IA-NEXT: add a5, a4, a1 ; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: xor a5, a4, a5 -; RV64IA-NEXT: sc.w.rl a5, a5, (a2) +; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB8_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a4, a0 +; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: ret %1 = atomicrmw add i8* %a, i8 %b acq_rel ret i8 %1 @@ -615,23 +615,23 @@ define i8 @atomicrmw_add_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_add_i8_seq_cst: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a3, a3, a0 +; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aqrl a4, (a2) +; RV32IA-NEXT: lr.w.aqrl a4, (a0) ; RV32IA-NEXT: add a5, a4, a1 ; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: sc.w.aqrl a5, a5, (a2) +; RV32IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB9_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a4, a0 +; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_add_i8_seq_cst: @@ -646,23 +646,23 @@ define i8 @atomicrmw_add_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_add_i8_seq_cst: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a3, a3, a0 +; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aqrl a4, (a2) +; RV64IA-NEXT: lr.w.aqrl a4, (a0) ; RV64IA-NEXT: add a5, a4, a1 ; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: xor a5, a4, a5 -; RV64IA-NEXT: sc.w.aqrl a5, a5, (a2) +; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB9_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a4, a0 +; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: ret %1 = atomicrmw add i8* %a, i8 %b seq_cst ret i8 %1 @@ -681,23 +681,23 @@ define i8 @atomicrmw_sub_i8_monotonic(i8* %a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_sub_i8_monotonic: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a3, a3, a0 +; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a4, (a2) +; RV32IA-NEXT: lr.w a4, (a0) ; RV32IA-NEXT: sub a5, a4, a1 ; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: sc.w a5, a5, (a2) +; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB10_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a4, a0 +; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_sub_i8_monotonic: @@ -712,23 +712,23 @@ define i8 @atomicrmw_sub_i8_monotonic(i8* %a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_sub_i8_monotonic: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a3, a3, a0 +; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w a4, (a2) +; RV64IA-NEXT: lr.w a4, (a0) ; RV64IA-NEXT: sub a5, a4, a1 ; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: xor a5, a4, a5 -; RV64IA-NEXT: sc.w a5, a5, (a2) +; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB10_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a4, a0 +; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: ret %1 = atomicrmw sub i8* %a, i8 %b monotonic ret i8 %1 @@ -747,23 +747,23 @@ define i8 @atomicrmw_sub_i8_acquire(i8* %a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_sub_i8_acquire: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a3, a3, a0 +; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aq a4, (a2) +; RV32IA-NEXT: lr.w.aq a4, (a0) ; RV32IA-NEXT: sub a5, a4, a1 ; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: sc.w a5, a5, (a2) +; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB11_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a4, a0 +; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_sub_i8_acquire: @@ -778,23 +778,23 @@ define i8 @atomicrmw_sub_i8_acquire(i8* %a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_sub_i8_acquire: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a3, a3, a0 +; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aq a4, (a2) +; RV64IA-NEXT: lr.w.aq a4, (a0) ; RV64IA-NEXT: sub a5, a4, a1 ; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: xor a5, a4, a5 -; RV64IA-NEXT: sc.w a5, a5, (a2) +; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB11_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a4, a0 +; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: ret %1 = atomicrmw sub i8* %a, i8 %b acquire ret i8 %1 @@ -813,23 +813,23 @@ define i8 @atomicrmw_sub_i8_release(i8* %a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_sub_i8_release: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a3, a3, a0 +; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a4, (a2) +; RV32IA-NEXT: lr.w a4, (a0) ; RV32IA-NEXT: sub a5, a4, a1 ; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB12_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a4, a0 +; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_sub_i8_release: @@ -844,23 +844,23 @@ define i8 @atomicrmw_sub_i8_release(i8* %a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_sub_i8_release: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a3, a3, a0 +; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w a4, (a2) +; RV64IA-NEXT: lr.w a4, (a0) ; RV64IA-NEXT: sub a5, a4, a1 ; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: xor a5, a4, a5 -; RV64IA-NEXT: sc.w.rl a5, a5, (a2) +; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB12_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a4, a0 +; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: ret %1 = atomicrmw sub i8* %a, i8 %b release ret i8 %1 @@ -879,23 +879,23 @@ define i8 @atomicrmw_sub_i8_acq_rel(i8* %a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_sub_i8_acq_rel: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a3, a3, a0 +; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aq a4, (a2) +; RV32IA-NEXT: lr.w.aq a4, (a0) ; RV32IA-NEXT: sub a5, a4, a1 ; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB13_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a4, a0 +; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_sub_i8_acq_rel: @@ -910,23 +910,23 @@ define i8 @atomicrmw_sub_i8_acq_rel(i8* %a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_sub_i8_acq_rel: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a3, a3, a0 +; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aq a4, (a2) +; RV64IA-NEXT: lr.w.aq a4, (a0) ; RV64IA-NEXT: sub a5, a4, a1 ; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: xor a5, a4, a5 -; RV64IA-NEXT: sc.w.rl a5, a5, (a2) +; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB13_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a4, a0 +; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: ret %1 = atomicrmw sub i8* %a, i8 %b acq_rel ret i8 %1 @@ -945,23 +945,23 @@ define i8 @atomicrmw_sub_i8_seq_cst(i8* %a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_sub_i8_seq_cst: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a3, a3, a0 +; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aqrl a4, (a2) +; RV32IA-NEXT: lr.w.aqrl a4, (a0) ; RV32IA-NEXT: sub a5, a4, a1 ; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: sc.w.aqrl a5, a5, (a2) +; RV32IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB14_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a4, a0 +; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_sub_i8_seq_cst: @@ -976,23 +976,23 @@ define i8 @atomicrmw_sub_i8_seq_cst(i8* %a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_sub_i8_seq_cst: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a3, a3, a0 +; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aqrl a4, (a2) +; RV64IA-NEXT: lr.w.aqrl a4, (a0) ; RV64IA-NEXT: sub a5, a4, a1 ; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: xor a5, a4, a5 -; RV64IA-NEXT: sc.w.aqrl a5, a5, (a2) +; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB14_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a4, a0 +; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: ret %1 = atomicrmw sub i8* %a, i8 %b seq_cst ret i8 %1 @@ -1011,17 +1011,17 @@ define i8 @atomicrmw_and_i8_monotonic(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_and_i8_monotonic: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 +; RV32IA-NEXT: andi a1, a1, 255 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a3, a3, a0 +; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: not a3, a3 -; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: or a1, a3, a1 -; RV32IA-NEXT: amoand.w a1, a1, (a2) -; RV32IA-NEXT: srl a0, a1, a0 +; RV32IA-NEXT: andi a0, a0, -4 +; RV32IA-NEXT: amoand.w a0, a1, (a0) +; RV32IA-NEXT: srl a0, a0, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_and_i8_monotonic: @@ -1036,17 +1036,17 @@ define i8 @atomicrmw_and_i8_monotonic(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_and_i8_monotonic: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 +; RV64IA-NEXT: andi a1, a1, 255 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a3, a3, a0 +; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: not a3, a3 -; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: or a1, a3, a1 -; RV64IA-NEXT: amoand.w a1, a1, (a2) -; RV64IA-NEXT: srlw a0, a1, a0 +; RV64IA-NEXT: andi a0, a0, -4 +; RV64IA-NEXT: amoand.w a0, a1, (a0) +; RV64IA-NEXT: srlw a0, a0, a2 ; RV64IA-NEXT: ret %1 = atomicrmw and i8* %a, i8 %b monotonic ret i8 %1 @@ -1065,17 +1065,17 @@ define i8 @atomicrmw_and_i8_acquire(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_and_i8_acquire: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 +; RV32IA-NEXT: andi a1, a1, 255 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a3, a3, a0 +; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: not a3, a3 -; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: or a1, a3, a1 -; RV32IA-NEXT: amoand.w.aq a1, a1, (a2) -; RV32IA-NEXT: srl a0, a1, a0 +; RV32IA-NEXT: andi a0, a0, -4 +; RV32IA-NEXT: amoand.w.aq a0, a1, (a0) +; RV32IA-NEXT: srl a0, a0, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_and_i8_acquire: @@ -1090,17 +1090,17 @@ define i8 @atomicrmw_and_i8_acquire(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_and_i8_acquire: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 +; RV64IA-NEXT: andi a1, a1, 255 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a3, a3, a0 +; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: not a3, a3 -; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: or a1, a3, a1 -; RV64IA-NEXT: amoand.w.aq a1, a1, (a2) -; RV64IA-NEXT: srlw a0, a1, a0 +; RV64IA-NEXT: andi a0, a0, -4 +; RV64IA-NEXT: amoand.w.aq a0, a1, (a0) +; RV64IA-NEXT: srlw a0, a0, a2 ; RV64IA-NEXT: ret %1 = atomicrmw and i8* %a, i8 %b acquire ret i8 %1 @@ -1119,17 +1119,17 @@ define i8 @atomicrmw_and_i8_release(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_and_i8_release: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 +; RV32IA-NEXT: andi a1, a1, 255 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a3, a3, a0 +; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: not a3, a3 -; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: or a1, a3, a1 -; RV32IA-NEXT: amoand.w.rl a1, a1, (a2) -; RV32IA-NEXT: srl a0, a1, a0 +; RV32IA-NEXT: andi a0, a0, -4 +; RV32IA-NEXT: amoand.w.rl a0, a1, (a0) +; RV32IA-NEXT: srl a0, a0, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_and_i8_release: @@ -1144,17 +1144,17 @@ define i8 @atomicrmw_and_i8_release(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_and_i8_release: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 +; RV64IA-NEXT: andi a1, a1, 255 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a3, a3, a0 +; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: not a3, a3 -; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: or a1, a3, a1 -; RV64IA-NEXT: amoand.w.rl a1, a1, (a2) -; RV64IA-NEXT: srlw a0, a1, a0 +; RV64IA-NEXT: andi a0, a0, -4 +; RV64IA-NEXT: amoand.w.rl a0, a1, (a0) +; RV64IA-NEXT: srlw a0, a0, a2 ; RV64IA-NEXT: ret %1 = atomicrmw and i8* %a, i8 %b release ret i8 %1 @@ -1173,17 +1173,17 @@ define i8 @atomicrmw_and_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_and_i8_acq_rel: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 +; RV32IA-NEXT: andi a1, a1, 255 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a3, a3, a0 +; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: not a3, a3 -; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: or a1, a3, a1 -; RV32IA-NEXT: amoand.w.aqrl a1, a1, (a2) -; RV32IA-NEXT: srl a0, a1, a0 +; RV32IA-NEXT: andi a0, a0, -4 +; RV32IA-NEXT: amoand.w.aqrl a0, a1, (a0) +; RV32IA-NEXT: srl a0, a0, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_and_i8_acq_rel: @@ -1198,17 +1198,17 @@ define i8 @atomicrmw_and_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_and_i8_acq_rel: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 +; RV64IA-NEXT: andi a1, a1, 255 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a3, a3, a0 +; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: not a3, a3 -; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: or a1, a3, a1 -; RV64IA-NEXT: amoand.w.aqrl a1, a1, (a2) -; RV64IA-NEXT: srlw a0, a1, a0 +; RV64IA-NEXT: andi a0, a0, -4 +; RV64IA-NEXT: amoand.w.aqrl a0, a1, (a0) +; RV64IA-NEXT: srlw a0, a0, a2 ; RV64IA-NEXT: ret %1 = atomicrmw and i8* %a, i8 %b acq_rel ret i8 %1 @@ -1227,17 +1227,17 @@ define i8 @atomicrmw_and_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_and_i8_seq_cst: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 +; RV32IA-NEXT: andi a1, a1, 255 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: sll a1, a1, a2 ; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a3, a3, a0 +; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: not a3, a3 -; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: or a1, a3, a1 -; RV32IA-NEXT: amoand.w.aqrl a1, a1, (a2) -; RV32IA-NEXT: srl a0, a1, a0 +; RV32IA-NEXT: andi a0, a0, -4 +; RV32IA-NEXT: amoand.w.aqrl a0, a1, (a0) +; RV32IA-NEXT: srl a0, a0, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_and_i8_seq_cst: @@ -1252,17 +1252,17 @@ define i8 @atomicrmw_and_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_and_i8_seq_cst: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 +; RV64IA-NEXT: andi a1, a1, 255 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: sllw a1, a1, a2 ; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a3, a3, a0 +; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: not a3, a3 -; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: or a1, a3, a1 -; RV64IA-NEXT: amoand.w.aqrl a1, a1, (a2) -; RV64IA-NEXT: srlw a0, a1, a0 +; RV64IA-NEXT: andi a0, a0, -4 +; RV64IA-NEXT: amoand.w.aqrl a0, a1, (a0) +; RV64IA-NEXT: srlw a0, a0, a2 ; RV64IA-NEXT: ret %1 = atomicrmw and i8* %a, i8 %b seq_cst ret i8 %1 @@ -1281,24 +1281,24 @@ define i8 @atomicrmw_nand_i8_monotonic(i8* %a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_nand_i8_monotonic: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a3, a3, a0 +; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a4, (a2) +; RV32IA-NEXT: lr.w a4, (a0) ; RV32IA-NEXT: and a5, a4, a1 ; RV32IA-NEXT: not a5, a5 ; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: sc.w a5, a5, (a2) +; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB20_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a4, a0 +; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_nand_i8_monotonic: @@ -1313,24 +1313,24 @@ define i8 @atomicrmw_nand_i8_monotonic(i8* %a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_nand_i8_monotonic: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a3, a3, a0 +; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w a4, (a2) +; RV64IA-NEXT: lr.w a4, (a0) ; RV64IA-NEXT: and a5, a4, a1 ; RV64IA-NEXT: not a5, a5 ; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: xor a5, a4, a5 -; RV64IA-NEXT: sc.w a5, a5, (a2) +; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB20_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a4, a0 +; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: ret %1 = atomicrmw nand i8* %a, i8 %b monotonic ret i8 %1 @@ -1349,24 +1349,24 @@ define i8 @atomicrmw_nand_i8_acquire(i8* %a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_nand_i8_acquire: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a3, a3, a0 +; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aq a4, (a2) +; RV32IA-NEXT: lr.w.aq a4, (a0) ; RV32IA-NEXT: and a5, a4, a1 ; RV32IA-NEXT: not a5, a5 ; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: sc.w a5, a5, (a2) +; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB21_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a4, a0 +; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_nand_i8_acquire: @@ -1381,24 +1381,24 @@ define i8 @atomicrmw_nand_i8_acquire(i8* %a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_nand_i8_acquire: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a3, a3, a0 +; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aq a4, (a2) +; RV64IA-NEXT: lr.w.aq a4, (a0) ; RV64IA-NEXT: and a5, a4, a1 ; RV64IA-NEXT: not a5, a5 ; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: xor a5, a4, a5 -; RV64IA-NEXT: sc.w a5, a5, (a2) +; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB21_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a4, a0 +; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: ret %1 = atomicrmw nand i8* %a, i8 %b acquire ret i8 %1 @@ -1417,24 +1417,24 @@ define i8 @atomicrmw_nand_i8_release(i8* %a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_nand_i8_release: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a3, a3, a0 +; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a4, (a2) +; RV32IA-NEXT: lr.w a4, (a0) ; RV32IA-NEXT: and a5, a4, a1 ; RV32IA-NEXT: not a5, a5 ; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB22_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a4, a0 +; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_nand_i8_release: @@ -1449,24 +1449,24 @@ define i8 @atomicrmw_nand_i8_release(i8* %a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_nand_i8_release: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a3, a3, a0 +; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w a4, (a2) +; RV64IA-NEXT: lr.w a4, (a0) ; RV64IA-NEXT: and a5, a4, a1 ; RV64IA-NEXT: not a5, a5 ; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: xor a5, a4, a5 -; RV64IA-NEXT: sc.w.rl a5, a5, (a2) +; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB22_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a4, a0 +; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: ret %1 = atomicrmw nand i8* %a, i8 %b release ret i8 %1 @@ -1485,24 +1485,24 @@ define i8 @atomicrmw_nand_i8_acq_rel(i8* %a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_nand_i8_acq_rel: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a3, a3, a0 +; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aq a4, (a2) +; RV32IA-NEXT: lr.w.aq a4, (a0) ; RV32IA-NEXT: and a5, a4, a1 ; RV32IA-NEXT: not a5, a5 ; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB23_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a4, a0 +; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_nand_i8_acq_rel: @@ -1517,24 +1517,24 @@ define i8 @atomicrmw_nand_i8_acq_rel(i8* %a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_nand_i8_acq_rel: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a3, a3, a0 +; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aq a4, (a2) +; RV64IA-NEXT: lr.w.aq a4, (a0) ; RV64IA-NEXT: and a5, a4, a1 ; RV64IA-NEXT: not a5, a5 ; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: xor a5, a4, a5 -; RV64IA-NEXT: sc.w.rl a5, a5, (a2) +; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB23_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a4, a0 +; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: ret %1 = atomicrmw nand i8* %a, i8 %b acq_rel ret i8 %1 @@ -1553,24 +1553,24 @@ define i8 @atomicrmw_nand_i8_seq_cst(i8* %a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_nand_i8_seq_cst: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a3, a3, a0 +; RV32IA-NEXT: sll a3, a3, a2 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aqrl a4, (a2) +; RV32IA-NEXT: lr.w.aqrl a4, (a0) ; RV32IA-NEXT: and a5, a4, a1 ; RV32IA-NEXT: not a5, a5 ; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: sc.w.aqrl a5, a5, (a2) +; RV32IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB24_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a4, a0 +; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_nand_i8_seq_cst: @@ -1585,24 +1585,24 @@ define i8 @atomicrmw_nand_i8_seq_cst(i8* %a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_nand_i8_seq_cst: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a3, a3, a0 +; RV64IA-NEXT: sllw a3, a3, a2 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aqrl a4, (a2) +; RV64IA-NEXT: lr.w.aqrl a4, (a0) ; RV64IA-NEXT: and a5, a4, a1 ; RV64IA-NEXT: not a5, a5 ; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: xor a5, a4, a5 -; RV64IA-NEXT: sc.w.aqrl a5, a5, (a2) +; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB24_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a4, a0 +; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: ret %1 = atomicrmw nand i8* %a, i8 %b seq_cst ret i8 %1 @@ -1621,13 +1621,13 @@ define i8 @atomicrmw_or_i8_monotonic(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_or_i8_monotonic: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: amoor.w a1, a1, (a2) -; RV32IA-NEXT: srl a0, a1, a0 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 +; RV32IA-NEXT: amoor.w a0, a1, (a0) +; RV32IA-NEXT: srl a0, a0, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_or_i8_monotonic: @@ -1642,13 +1642,13 @@ define i8 @atomicrmw_or_i8_monotonic(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_or_i8_monotonic: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: amoor.w a1, a1, (a2) -; RV64IA-NEXT: srlw a0, a1, a0 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 +; RV64IA-NEXT: amoor.w a0, a1, (a0) +; RV64IA-NEXT: srlw a0, a0, a2 ; RV64IA-NEXT: ret %1 = atomicrmw or i8* %a, i8 %b monotonic ret i8 %1 @@ -1667,13 +1667,13 @@ define i8 @atomicrmw_or_i8_acquire(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_or_i8_acquire: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: amoor.w.aq a1, a1, (a2) -; RV32IA-NEXT: srl a0, a1, a0 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 +; RV32IA-NEXT: amoor.w.aq a0, a1, (a0) +; RV32IA-NEXT: srl a0, a0, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_or_i8_acquire: @@ -1688,13 +1688,13 @@ define i8 @atomicrmw_or_i8_acquire(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_or_i8_acquire: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: amoor.w.aq a1, a1, (a2) -; RV64IA-NEXT: srlw a0, a1, a0 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 +; RV64IA-NEXT: amoor.w.aq a0, a1, (a0) +; RV64IA-NEXT: srlw a0, a0, a2 ; RV64IA-NEXT: ret %1 = atomicrmw or i8* %a, i8 %b acquire ret i8 %1 @@ -1713,13 +1713,13 @@ define i8 @atomicrmw_or_i8_release(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_or_i8_release: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: amoor.w.rl a1, a1, (a2) -; RV32IA-NEXT: srl a0, a1, a0 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 +; RV32IA-NEXT: amoor.w.rl a0, a1, (a0) +; RV32IA-NEXT: srl a0, a0, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_or_i8_release: @@ -1734,13 +1734,13 @@ define i8 @atomicrmw_or_i8_release(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_or_i8_release: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: amoor.w.rl a1, a1, (a2) -; RV64IA-NEXT: srlw a0, a1, a0 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 +; RV64IA-NEXT: amoor.w.rl a0, a1, (a0) +; RV64IA-NEXT: srlw a0, a0, a2 ; RV64IA-NEXT: ret %1 = atomicrmw or i8* %a, i8 %b release ret i8 %1 @@ -1759,13 +1759,13 @@ define i8 @atomicrmw_or_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_or_i8_acq_rel: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: amoor.w.aqrl a1, a1, (a2) -; RV32IA-NEXT: srl a0, a1, a0 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 +; RV32IA-NEXT: amoor.w.aqrl a0, a1, (a0) +; RV32IA-NEXT: srl a0, a0, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_or_i8_acq_rel: @@ -1780,13 +1780,13 @@ define i8 @atomicrmw_or_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_or_i8_acq_rel: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: amoor.w.aqrl a1, a1, (a2) -; RV64IA-NEXT: srlw a0, a1, a0 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 +; RV64IA-NEXT: amoor.w.aqrl a0, a1, (a0) +; RV64IA-NEXT: srlw a0, a0, a2 ; RV64IA-NEXT: ret %1 = atomicrmw or i8* %a, i8 %b acq_rel ret i8 %1 @@ -1805,13 +1805,13 @@ define i8 @atomicrmw_or_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_or_i8_seq_cst: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: amoor.w.aqrl a1, a1, (a2) -; RV32IA-NEXT: srl a0, a1, a0 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 +; RV32IA-NEXT: amoor.w.aqrl a0, a1, (a0) +; RV32IA-NEXT: srl a0, a0, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_or_i8_seq_cst: @@ -1826,13 +1826,13 @@ define i8 @atomicrmw_or_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_or_i8_seq_cst: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: amoor.w.aqrl a1, a1, (a2) -; RV64IA-NEXT: srlw a0, a1, a0 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 +; RV64IA-NEXT: amoor.w.aqrl a0, a1, (a0) +; RV64IA-NEXT: srlw a0, a0, a2 ; RV64IA-NEXT: ret %1 = atomicrmw or i8* %a, i8 %b seq_cst ret i8 %1 @@ -1851,13 +1851,13 @@ define i8 @atomicrmw_xor_i8_monotonic(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_xor_i8_monotonic: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: amoxor.w a1, a1, (a2) -; RV32IA-NEXT: srl a0, a1, a0 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 +; RV32IA-NEXT: amoxor.w a0, a1, (a0) +; RV32IA-NEXT: srl a0, a0, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xor_i8_monotonic: @@ -1872,13 +1872,13 @@ define i8 @atomicrmw_xor_i8_monotonic(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_xor_i8_monotonic: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: amoxor.w a1, a1, (a2) -; RV64IA-NEXT: srlw a0, a1, a0 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 +; RV64IA-NEXT: amoxor.w a0, a1, (a0) +; RV64IA-NEXT: srlw a0, a0, a2 ; RV64IA-NEXT: ret %1 = atomicrmw xor i8* %a, i8 %b monotonic ret i8 %1 @@ -1897,13 +1897,13 @@ define i8 @atomicrmw_xor_i8_acquire(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_xor_i8_acquire: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: amoxor.w.aq a1, a1, (a2) -; RV32IA-NEXT: srl a0, a1, a0 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 +; RV32IA-NEXT: amoxor.w.aq a0, a1, (a0) +; RV32IA-NEXT: srl a0, a0, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xor_i8_acquire: @@ -1918,13 +1918,13 @@ define i8 @atomicrmw_xor_i8_acquire(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_xor_i8_acquire: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: amoxor.w.aq a1, a1, (a2) -; RV64IA-NEXT: srlw a0, a1, a0 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 +; RV64IA-NEXT: amoxor.w.aq a0, a1, (a0) +; RV64IA-NEXT: srlw a0, a0, a2 ; RV64IA-NEXT: ret %1 = atomicrmw xor i8* %a, i8 %b acquire ret i8 %1 @@ -1943,13 +1943,13 @@ define i8 @atomicrmw_xor_i8_release(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_xor_i8_release: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: amoxor.w.rl a1, a1, (a2) -; RV32IA-NEXT: srl a0, a1, a0 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 +; RV32IA-NEXT: amoxor.w.rl a0, a1, (a0) +; RV32IA-NEXT: srl a0, a0, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xor_i8_release: @@ -1964,13 +1964,13 @@ define i8 @atomicrmw_xor_i8_release(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_xor_i8_release: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: amoxor.w.rl a1, a1, (a2) -; RV64IA-NEXT: srlw a0, a1, a0 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 +; RV64IA-NEXT: amoxor.w.rl a0, a1, (a0) +; RV64IA-NEXT: srlw a0, a0, a2 ; RV64IA-NEXT: ret %1 = atomicrmw xor i8* %a, i8 %b release ret i8 %1 @@ -1989,13 +1989,13 @@ define i8 @atomicrmw_xor_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_xor_i8_acq_rel: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: amoxor.w.aqrl a1, a1, (a2) -; RV32IA-NEXT: srl a0, a1, a0 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 +; RV32IA-NEXT: amoxor.w.aqrl a0, a1, (a0) +; RV32IA-NEXT: srl a0, a0, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xor_i8_acq_rel: @@ -2010,13 +2010,13 @@ define i8 @atomicrmw_xor_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_xor_i8_acq_rel: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: amoxor.w.aqrl a1, a1, (a2) -; RV64IA-NEXT: srlw a0, a1, a0 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 +; RV64IA-NEXT: amoxor.w.aqrl a0, a1, (a0) +; RV64IA-NEXT: srlw a0, a0, a2 ; RV64IA-NEXT: ret %1 = atomicrmw xor i8* %a, i8 %b acq_rel ret i8 %1 @@ -2035,13 +2035,13 @@ define i8 @atomicrmw_xor_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_xor_i8_seq_cst: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: amoxor.w.aqrl a1, a1, (a2) -; RV32IA-NEXT: srl a0, a1, a0 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 +; RV32IA-NEXT: amoxor.w.aqrl a0, a1, (a0) +; RV32IA-NEXT: srl a0, a0, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xor_i8_seq_cst: @@ -2056,13 +2056,13 @@ define i8 @atomicrmw_xor_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_xor_i8_seq_cst: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: amoxor.w.aqrl a1, a1, (a2) -; RV64IA-NEXT: srlw a0, a1, a0 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 +; RV64IA-NEXT: amoxor.w.aqrl a0, a1, (a0) +; RV64IA-NEXT: srlw a0, a0, a2 ; RV64IA-NEXT: ret %1 = atomicrmw xor i8* %a, i8 %b seq_cst ret i8 %1 @@ -2079,33 +2079,33 @@ define i8 @atomicrmw_max_i8_monotonic(i8 *%a, i8 %b) nounwind { ; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: lbu a1, 0(a0) -; RV32I-NEXT: slli a0, s2, 24 -; RV32I-NEXT: srai s0, a0, 24 +; RV32I-NEXT: lbu a0, 0(a0) +; RV32I-NEXT: slli a1, a1, 24 +; RV32I-NEXT: srai s0, a1, 24 ; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: j .LBB35_2 ; RV32I-NEXT: .LBB35_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB35_2 Depth=1 -; RV32I-NEXT: sb a1, 11(sp) +; RV32I-NEXT: sb a0, 11(sp) ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: call __atomic_compare_exchange_1 -; RV32I-NEXT: lb a1, 11(sp) -; RV32I-NEXT: bnez a0, .LBB35_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lb a0, 11(sp) +; RV32I-NEXT: bnez a1, .LBB35_4 ; RV32I-NEXT: .LBB35_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: slli a0, a1, 24 -; RV32I-NEXT: srai a0, a0, 24 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: blt s0, a0, .LBB35_1 +; RV32I-NEXT: slli a1, a0, 24 +; RV32I-NEXT: srai a1, a1, 24 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: blt s0, a1, .LBB35_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB35_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB35_1 ; RV32I-NEXT: .LBB35_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -2116,32 +2116,32 @@ define i8 @atomicrmw_max_i8_monotonic(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_max_i8_monotonic: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a7, a3, a0 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: addi a3, zero, 24 +; RV32IA-NEXT: sub a6, a3, a2 +; RV32IA-NEXT: addi a4, zero, 255 +; RV32IA-NEXT: sll a7, a4, a2 ; RV32IA-NEXT: slli a1, a1, 24 ; RV32IA-NEXT: srai a1, a1, 24 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: addi a4, zero, 24 -; RV32IA-NEXT: sub a4, a4, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB35_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a5, (a6) -; RV32IA-NEXT: and a3, a5, a7 -; RV32IA-NEXT: mv a2, a5 -; RV32IA-NEXT: sll a3, a3, a4 -; RV32IA-NEXT: sra a3, a3, a4 -; RV32IA-NEXT: bge a3, a1, .LBB35_3 +; RV32IA-NEXT: lr.w a5, (a0) +; RV32IA-NEXT: and a4, a5, a7 +; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sll a4, a4, a6 +; RV32IA-NEXT: sra a4, a4, a6 +; RV32IA-NEXT: bge a4, a1, .LBB35_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB35_1 Depth=1 -; RV32IA-NEXT: xor a2, a5, a1 -; RV32IA-NEXT: and a2, a2, a7 -; RV32IA-NEXT: xor a2, a5, a2 +; RV32IA-NEXT: xor a3, a5, a1 +; RV32IA-NEXT: and a3, a3, a7 +; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: .LBB35_3: # in Loop: Header=BB35_1 Depth=1 -; RV32IA-NEXT: sc.w a2, a2, (a6) -; RV32IA-NEXT: bnez a2, .LBB35_1 +; RV32IA-NEXT: sc.w a3, a3, (a0) +; RV32IA-NEXT: bnez a3, .LBB35_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a5, a0 +; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_max_i8_monotonic: @@ -2154,33 +2154,33 @@ define i8 @atomicrmw_max_i8_monotonic(i8 *%a, i8 %b) nounwind { ; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: lbu a1, 0(a0) -; RV64I-NEXT: slli a0, s2, 56 -; RV64I-NEXT: srai s0, a0, 56 +; RV64I-NEXT: lbu a0, 0(a0) +; RV64I-NEXT: slli a1, a1, 56 +; RV64I-NEXT: srai s0, a1, 56 ; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: j .LBB35_2 ; RV64I-NEXT: .LBB35_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB35_2 Depth=1 -; RV64I-NEXT: sb a1, 7(sp) +; RV64I-NEXT: sb a0, 7(sp) ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: call __atomic_compare_exchange_1 -; RV64I-NEXT: lb a1, 7(sp) -; RV64I-NEXT: bnez a0, .LBB35_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lb a0, 7(sp) +; RV64I-NEXT: bnez a1, .LBB35_4 ; RV64I-NEXT: .LBB35_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: slli a0, a1, 56 -; RV64I-NEXT: srai a0, a0, 56 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: blt s0, a0, .LBB35_1 +; RV64I-NEXT: slli a1, a0, 56 +; RV64I-NEXT: srai a1, a1, 56 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: blt s0, a1, .LBB35_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB35_2 Depth=1 ; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB35_1 ; RV64I-NEXT: .LBB35_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -2191,32 +2191,32 @@ define i8 @atomicrmw_max_i8_monotonic(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_max_i8_monotonic: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a7, a3, a0 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: addi a3, zero, 56 +; RV64IA-NEXT: sub a6, a3, a2 +; RV64IA-NEXT: addi a4, zero, 255 +; RV64IA-NEXT: sllw a7, a4, a2 ; RV64IA-NEXT: slli a1, a1, 56 ; RV64IA-NEXT: srai a1, a1, 56 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: addi a4, zero, 56 -; RV64IA-NEXT: sub a4, a4, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB35_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w a5, (a6) -; RV64IA-NEXT: and a3, a5, a7 -; RV64IA-NEXT: mv a2, a5 -; RV64IA-NEXT: sll a3, a3, a4 -; RV64IA-NEXT: sra a3, a3, a4 -; RV64IA-NEXT: bge a3, a1, .LBB35_3 +; RV64IA-NEXT: lr.w a5, (a0) +; RV64IA-NEXT: and a4, a5, a7 +; RV64IA-NEXT: mv a3, a5 +; RV64IA-NEXT: sll a4, a4, a6 +; RV64IA-NEXT: sra a4, a4, a6 +; RV64IA-NEXT: bge a4, a1, .LBB35_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB35_1 Depth=1 -; RV64IA-NEXT: xor a2, a5, a1 -; RV64IA-NEXT: and a2, a2, a7 -; RV64IA-NEXT: xor a2, a5, a2 +; RV64IA-NEXT: xor a3, a5, a1 +; RV64IA-NEXT: and a3, a3, a7 +; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: .LBB35_3: # in Loop: Header=BB35_1 Depth=1 -; RV64IA-NEXT: sc.w a2, a2, (a6) -; RV64IA-NEXT: bnez a2, .LBB35_1 +; RV64IA-NEXT: sc.w a3, a3, (a0) +; RV64IA-NEXT: bnez a3, .LBB35_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a5, a0 +; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: ret %1 = atomicrmw max i8* %a, i8 %b monotonic ret i8 %1 @@ -2233,33 +2233,33 @@ define i8 @atomicrmw_max_i8_acquire(i8 *%a, i8 %b) nounwind { ; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: lbu a1, 0(a0) -; RV32I-NEXT: slli a0, s2, 24 -; RV32I-NEXT: srai s0, a0, 24 +; RV32I-NEXT: lbu a0, 0(a0) +; RV32I-NEXT: slli a1, a1, 24 +; RV32I-NEXT: srai s0, a1, 24 ; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: j .LBB36_2 ; RV32I-NEXT: .LBB36_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB36_2 Depth=1 -; RV32I-NEXT: sb a1, 11(sp) -; RV32I-NEXT: addi a3, zero, 2 -; RV32I-NEXT: addi a4, zero, 2 +; RV32I-NEXT: sb a0, 11(sp) ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s3 +; RV32I-NEXT: addi a3, zero, 2 +; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: call __atomic_compare_exchange_1 -; RV32I-NEXT: lb a1, 11(sp) -; RV32I-NEXT: bnez a0, .LBB36_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lb a0, 11(sp) +; RV32I-NEXT: bnez a1, .LBB36_4 ; RV32I-NEXT: .LBB36_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: slli a0, a1, 24 -; RV32I-NEXT: srai a0, a0, 24 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: blt s0, a0, .LBB36_1 +; RV32I-NEXT: slli a1, a0, 24 +; RV32I-NEXT: srai a1, a1, 24 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: blt s0, a1, .LBB36_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB36_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB36_1 ; RV32I-NEXT: .LBB36_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -2270,32 +2270,32 @@ define i8 @atomicrmw_max_i8_acquire(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_max_i8_acquire: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a7, a3, a0 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: addi a3, zero, 24 +; RV32IA-NEXT: sub a6, a3, a2 +; RV32IA-NEXT: addi a4, zero, 255 +; RV32IA-NEXT: sll a7, a4, a2 ; RV32IA-NEXT: slli a1, a1, 24 ; RV32IA-NEXT: srai a1, a1, 24 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: addi a4, zero, 24 -; RV32IA-NEXT: sub a4, a4, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB36_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aq a5, (a6) -; RV32IA-NEXT: and a3, a5, a7 -; RV32IA-NEXT: mv a2, a5 -; RV32IA-NEXT: sll a3, a3, a4 -; RV32IA-NEXT: sra a3, a3, a4 -; RV32IA-NEXT: bge a3, a1, .LBB36_3 +; RV32IA-NEXT: lr.w.aq a5, (a0) +; RV32IA-NEXT: and a4, a5, a7 +; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sll a4, a4, a6 +; RV32IA-NEXT: sra a4, a4, a6 +; RV32IA-NEXT: bge a4, a1, .LBB36_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB36_1 Depth=1 -; RV32IA-NEXT: xor a2, a5, a1 -; RV32IA-NEXT: and a2, a2, a7 -; RV32IA-NEXT: xor a2, a5, a2 +; RV32IA-NEXT: xor a3, a5, a1 +; RV32IA-NEXT: and a3, a3, a7 +; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: .LBB36_3: # in Loop: Header=BB36_1 Depth=1 -; RV32IA-NEXT: sc.w a2, a2, (a6) -; RV32IA-NEXT: bnez a2, .LBB36_1 +; RV32IA-NEXT: sc.w a3, a3, (a0) +; RV32IA-NEXT: bnez a3, .LBB36_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a5, a0 +; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_max_i8_acquire: @@ -2308,33 +2308,33 @@ define i8 @atomicrmw_max_i8_acquire(i8 *%a, i8 %b) nounwind { ; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: lbu a1, 0(a0) -; RV64I-NEXT: slli a0, s2, 56 -; RV64I-NEXT: srai s0, a0, 56 +; RV64I-NEXT: lbu a0, 0(a0) +; RV64I-NEXT: slli a1, a1, 56 +; RV64I-NEXT: srai s0, a1, 56 ; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: j .LBB36_2 ; RV64I-NEXT: .LBB36_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB36_2 Depth=1 -; RV64I-NEXT: sb a1, 7(sp) -; RV64I-NEXT: addi a3, zero, 2 -; RV64I-NEXT: addi a4, zero, 2 +; RV64I-NEXT: sb a0, 7(sp) ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s3 +; RV64I-NEXT: addi a3, zero, 2 +; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: call __atomic_compare_exchange_1 -; RV64I-NEXT: lb a1, 7(sp) -; RV64I-NEXT: bnez a0, .LBB36_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lb a0, 7(sp) +; RV64I-NEXT: bnez a1, .LBB36_4 ; RV64I-NEXT: .LBB36_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: slli a0, a1, 56 -; RV64I-NEXT: srai a0, a0, 56 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: blt s0, a0, .LBB36_1 +; RV64I-NEXT: slli a1, a0, 56 +; RV64I-NEXT: srai a1, a1, 56 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: blt s0, a1, .LBB36_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB36_2 Depth=1 ; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB36_1 ; RV64I-NEXT: .LBB36_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -2345,32 +2345,32 @@ define i8 @atomicrmw_max_i8_acquire(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_max_i8_acquire: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a7, a3, a0 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: addi a3, zero, 56 +; RV64IA-NEXT: sub a6, a3, a2 +; RV64IA-NEXT: addi a4, zero, 255 +; RV64IA-NEXT: sllw a7, a4, a2 ; RV64IA-NEXT: slli a1, a1, 56 ; RV64IA-NEXT: srai a1, a1, 56 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: addi a4, zero, 56 -; RV64IA-NEXT: sub a4, a4, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB36_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aq a5, (a6) -; RV64IA-NEXT: and a3, a5, a7 -; RV64IA-NEXT: mv a2, a5 -; RV64IA-NEXT: sll a3, a3, a4 -; RV64IA-NEXT: sra a3, a3, a4 -; RV64IA-NEXT: bge a3, a1, .LBB36_3 +; RV64IA-NEXT: lr.w.aq a5, (a0) +; RV64IA-NEXT: and a4, a5, a7 +; RV64IA-NEXT: mv a3, a5 +; RV64IA-NEXT: sll a4, a4, a6 +; RV64IA-NEXT: sra a4, a4, a6 +; RV64IA-NEXT: bge a4, a1, .LBB36_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB36_1 Depth=1 -; RV64IA-NEXT: xor a2, a5, a1 -; RV64IA-NEXT: and a2, a2, a7 -; RV64IA-NEXT: xor a2, a5, a2 +; RV64IA-NEXT: xor a3, a5, a1 +; RV64IA-NEXT: and a3, a3, a7 +; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: .LBB36_3: # in Loop: Header=BB36_1 Depth=1 -; RV64IA-NEXT: sc.w a2, a2, (a6) -; RV64IA-NEXT: bnez a2, .LBB36_1 +; RV64IA-NEXT: sc.w a3, a3, (a0) +; RV64IA-NEXT: bnez a3, .LBB36_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a5, a0 +; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: ret %1 = atomicrmw max i8* %a, i8 %b acquire ret i8 %1 @@ -2387,33 +2387,33 @@ define i8 @atomicrmw_max_i8_release(i8 *%a, i8 %b) nounwind { ; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: lbu a1, 0(a0) -; RV32I-NEXT: slli a0, s2, 24 -; RV32I-NEXT: srai s0, a0, 24 +; RV32I-NEXT: lbu a0, 0(a0) +; RV32I-NEXT: slli a1, a1, 24 +; RV32I-NEXT: srai s0, a1, 24 ; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: j .LBB37_2 ; RV32I-NEXT: .LBB37_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB37_2 Depth=1 -; RV32I-NEXT: sb a1, 11(sp) -; RV32I-NEXT: addi a3, zero, 3 +; RV32I-NEXT: sb a0, 11(sp) ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s3 +; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: call __atomic_compare_exchange_1 -; RV32I-NEXT: lb a1, 11(sp) -; RV32I-NEXT: bnez a0, .LBB37_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lb a0, 11(sp) +; RV32I-NEXT: bnez a1, .LBB37_4 ; RV32I-NEXT: .LBB37_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: slli a0, a1, 24 -; RV32I-NEXT: srai a0, a0, 24 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: blt s0, a0, .LBB37_1 +; RV32I-NEXT: slli a1, a0, 24 +; RV32I-NEXT: srai a1, a1, 24 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: blt s0, a1, .LBB37_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB37_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB37_1 ; RV32I-NEXT: .LBB37_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -2424,32 +2424,32 @@ define i8 @atomicrmw_max_i8_release(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_max_i8_release: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a7, a3, a0 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: addi a3, zero, 24 +; RV32IA-NEXT: sub a6, a3, a2 +; RV32IA-NEXT: addi a4, zero, 255 +; RV32IA-NEXT: sll a7, a4, a2 ; RV32IA-NEXT: slli a1, a1, 24 ; RV32IA-NEXT: srai a1, a1, 24 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: addi a4, zero, 24 -; RV32IA-NEXT: sub a4, a4, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB37_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a5, (a6) -; RV32IA-NEXT: and a3, a5, a7 -; RV32IA-NEXT: mv a2, a5 -; RV32IA-NEXT: sll a3, a3, a4 -; RV32IA-NEXT: sra a3, a3, a4 -; RV32IA-NEXT: bge a3, a1, .LBB37_3 +; RV32IA-NEXT: lr.w a5, (a0) +; RV32IA-NEXT: and a4, a5, a7 +; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sll a4, a4, a6 +; RV32IA-NEXT: sra a4, a4, a6 +; RV32IA-NEXT: bge a4, a1, .LBB37_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB37_1 Depth=1 -; RV32IA-NEXT: xor a2, a5, a1 -; RV32IA-NEXT: and a2, a2, a7 -; RV32IA-NEXT: xor a2, a5, a2 +; RV32IA-NEXT: xor a3, a5, a1 +; RV32IA-NEXT: and a3, a3, a7 +; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: .LBB37_3: # in Loop: Header=BB37_1 Depth=1 -; RV32IA-NEXT: sc.w.rl a2, a2, (a6) -; RV32IA-NEXT: bnez a2, .LBB37_1 +; RV32IA-NEXT: sc.w.rl a3, a3, (a0) +; RV32IA-NEXT: bnez a3, .LBB37_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a5, a0 +; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_max_i8_release: @@ -2462,33 +2462,33 @@ define i8 @atomicrmw_max_i8_release(i8 *%a, i8 %b) nounwind { ; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: lbu a1, 0(a0) -; RV64I-NEXT: slli a0, s2, 56 -; RV64I-NEXT: srai s0, a0, 56 +; RV64I-NEXT: lbu a0, 0(a0) +; RV64I-NEXT: slli a1, a1, 56 +; RV64I-NEXT: srai s0, a1, 56 ; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: j .LBB37_2 ; RV64I-NEXT: .LBB37_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB37_2 Depth=1 -; RV64I-NEXT: sb a1, 7(sp) -; RV64I-NEXT: addi a3, zero, 3 +; RV64I-NEXT: sb a0, 7(sp) ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s3 +; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: call __atomic_compare_exchange_1 -; RV64I-NEXT: lb a1, 7(sp) -; RV64I-NEXT: bnez a0, .LBB37_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lb a0, 7(sp) +; RV64I-NEXT: bnez a1, .LBB37_4 ; RV64I-NEXT: .LBB37_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: slli a0, a1, 56 -; RV64I-NEXT: srai a0, a0, 56 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: blt s0, a0, .LBB37_1 +; RV64I-NEXT: slli a1, a0, 56 +; RV64I-NEXT: srai a1, a1, 56 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: blt s0, a1, .LBB37_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB37_2 Depth=1 ; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB37_1 ; RV64I-NEXT: .LBB37_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -2499,32 +2499,32 @@ define i8 @atomicrmw_max_i8_release(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_max_i8_release: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a7, a3, a0 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: addi a3, zero, 56 +; RV64IA-NEXT: sub a6, a3, a2 +; RV64IA-NEXT: addi a4, zero, 255 +; RV64IA-NEXT: sllw a7, a4, a2 ; RV64IA-NEXT: slli a1, a1, 56 ; RV64IA-NEXT: srai a1, a1, 56 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: addi a4, zero, 56 -; RV64IA-NEXT: sub a4, a4, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB37_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w a5, (a6) -; RV64IA-NEXT: and a3, a5, a7 -; RV64IA-NEXT: mv a2, a5 -; RV64IA-NEXT: sll a3, a3, a4 -; RV64IA-NEXT: sra a3, a3, a4 -; RV64IA-NEXT: bge a3, a1, .LBB37_3 +; RV64IA-NEXT: lr.w a5, (a0) +; RV64IA-NEXT: and a4, a5, a7 +; RV64IA-NEXT: mv a3, a5 +; RV64IA-NEXT: sll a4, a4, a6 +; RV64IA-NEXT: sra a4, a4, a6 +; RV64IA-NEXT: bge a4, a1, .LBB37_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB37_1 Depth=1 -; RV64IA-NEXT: xor a2, a5, a1 -; RV64IA-NEXT: and a2, a2, a7 -; RV64IA-NEXT: xor a2, a5, a2 +; RV64IA-NEXT: xor a3, a5, a1 +; RV64IA-NEXT: and a3, a3, a7 +; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: .LBB37_3: # in Loop: Header=BB37_1 Depth=1 -; RV64IA-NEXT: sc.w.rl a2, a2, (a6) -; RV64IA-NEXT: bnez a2, .LBB37_1 +; RV64IA-NEXT: sc.w.rl a3, a3, (a0) +; RV64IA-NEXT: bnez a3, .LBB37_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a5, a0 +; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: ret %1 = atomicrmw max i8* %a, i8 %b release ret i8 %1 @@ -2541,33 +2541,33 @@ define i8 @atomicrmw_max_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: lbu a1, 0(a0) -; RV32I-NEXT: slli a0, s2, 24 -; RV32I-NEXT: srai s0, a0, 24 +; RV32I-NEXT: lbu a0, 0(a0) +; RV32I-NEXT: slli a1, a1, 24 +; RV32I-NEXT: srai s0, a1, 24 ; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: j .LBB38_2 ; RV32I-NEXT: .LBB38_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB38_2 Depth=1 -; RV32I-NEXT: sb a1, 11(sp) -; RV32I-NEXT: addi a3, zero, 4 -; RV32I-NEXT: addi a4, zero, 2 +; RV32I-NEXT: sb a0, 11(sp) ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s3 +; RV32I-NEXT: addi a3, zero, 4 +; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: call __atomic_compare_exchange_1 -; RV32I-NEXT: lb a1, 11(sp) -; RV32I-NEXT: bnez a0, .LBB38_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lb a0, 11(sp) +; RV32I-NEXT: bnez a1, .LBB38_4 ; RV32I-NEXT: .LBB38_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: slli a0, a1, 24 -; RV32I-NEXT: srai a0, a0, 24 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: blt s0, a0, .LBB38_1 +; RV32I-NEXT: slli a1, a0, 24 +; RV32I-NEXT: srai a1, a1, 24 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: blt s0, a1, .LBB38_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB38_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB38_1 ; RV32I-NEXT: .LBB38_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -2578,32 +2578,32 @@ define i8 @atomicrmw_max_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_max_i8_acq_rel: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a7, a3, a0 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: addi a3, zero, 24 +; RV32IA-NEXT: sub a6, a3, a2 +; RV32IA-NEXT: addi a4, zero, 255 +; RV32IA-NEXT: sll a7, a4, a2 ; RV32IA-NEXT: slli a1, a1, 24 ; RV32IA-NEXT: srai a1, a1, 24 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: addi a4, zero, 24 -; RV32IA-NEXT: sub a4, a4, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB38_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aq a5, (a6) -; RV32IA-NEXT: and a3, a5, a7 -; RV32IA-NEXT: mv a2, a5 -; RV32IA-NEXT: sll a3, a3, a4 -; RV32IA-NEXT: sra a3, a3, a4 -; RV32IA-NEXT: bge a3, a1, .LBB38_3 +; RV32IA-NEXT: lr.w.aq a5, (a0) +; RV32IA-NEXT: and a4, a5, a7 +; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sll a4, a4, a6 +; RV32IA-NEXT: sra a4, a4, a6 +; RV32IA-NEXT: bge a4, a1, .LBB38_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB38_1 Depth=1 -; RV32IA-NEXT: xor a2, a5, a1 -; RV32IA-NEXT: and a2, a2, a7 -; RV32IA-NEXT: xor a2, a5, a2 +; RV32IA-NEXT: xor a3, a5, a1 +; RV32IA-NEXT: and a3, a3, a7 +; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: .LBB38_3: # in Loop: Header=BB38_1 Depth=1 -; RV32IA-NEXT: sc.w.rl a2, a2, (a6) -; RV32IA-NEXT: bnez a2, .LBB38_1 +; RV32IA-NEXT: sc.w.rl a3, a3, (a0) +; RV32IA-NEXT: bnez a3, .LBB38_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a5, a0 +; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_max_i8_acq_rel: @@ -2616,33 +2616,33 @@ define i8 @atomicrmw_max_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: lbu a1, 0(a0) -; RV64I-NEXT: slli a0, s2, 56 -; RV64I-NEXT: srai s0, a0, 56 +; RV64I-NEXT: lbu a0, 0(a0) +; RV64I-NEXT: slli a1, a1, 56 +; RV64I-NEXT: srai s0, a1, 56 ; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: j .LBB38_2 ; RV64I-NEXT: .LBB38_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB38_2 Depth=1 -; RV64I-NEXT: sb a1, 7(sp) -; RV64I-NEXT: addi a3, zero, 4 -; RV64I-NEXT: addi a4, zero, 2 +; RV64I-NEXT: sb a0, 7(sp) ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s3 +; RV64I-NEXT: addi a3, zero, 4 +; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: call __atomic_compare_exchange_1 -; RV64I-NEXT: lb a1, 7(sp) -; RV64I-NEXT: bnez a0, .LBB38_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lb a0, 7(sp) +; RV64I-NEXT: bnez a1, .LBB38_4 ; RV64I-NEXT: .LBB38_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: slli a0, a1, 56 -; RV64I-NEXT: srai a0, a0, 56 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: blt s0, a0, .LBB38_1 +; RV64I-NEXT: slli a1, a0, 56 +; RV64I-NEXT: srai a1, a1, 56 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: blt s0, a1, .LBB38_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB38_2 Depth=1 ; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB38_1 ; RV64I-NEXT: .LBB38_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -2653,32 +2653,32 @@ define i8 @atomicrmw_max_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_max_i8_acq_rel: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a7, a3, a0 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: addi a3, zero, 56 +; RV64IA-NEXT: sub a6, a3, a2 +; RV64IA-NEXT: addi a4, zero, 255 +; RV64IA-NEXT: sllw a7, a4, a2 ; RV64IA-NEXT: slli a1, a1, 56 ; RV64IA-NEXT: srai a1, a1, 56 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: addi a4, zero, 56 -; RV64IA-NEXT: sub a4, a4, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB38_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aq a5, (a6) -; RV64IA-NEXT: and a3, a5, a7 -; RV64IA-NEXT: mv a2, a5 -; RV64IA-NEXT: sll a3, a3, a4 -; RV64IA-NEXT: sra a3, a3, a4 -; RV64IA-NEXT: bge a3, a1, .LBB38_3 +; RV64IA-NEXT: lr.w.aq a5, (a0) +; RV64IA-NEXT: and a4, a5, a7 +; RV64IA-NEXT: mv a3, a5 +; RV64IA-NEXT: sll a4, a4, a6 +; RV64IA-NEXT: sra a4, a4, a6 +; RV64IA-NEXT: bge a4, a1, .LBB38_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB38_1 Depth=1 -; RV64IA-NEXT: xor a2, a5, a1 -; RV64IA-NEXT: and a2, a2, a7 -; RV64IA-NEXT: xor a2, a5, a2 +; RV64IA-NEXT: xor a3, a5, a1 +; RV64IA-NEXT: and a3, a3, a7 +; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: .LBB38_3: # in Loop: Header=BB38_1 Depth=1 -; RV64IA-NEXT: sc.w.rl a2, a2, (a6) -; RV64IA-NEXT: bnez a2, .LBB38_1 +; RV64IA-NEXT: sc.w.rl a3, a3, (a0) +; RV64IA-NEXT: bnez a3, .LBB38_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a5, a0 +; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: ret %1 = atomicrmw max i8* %a, i8 %b acq_rel ret i8 %1 @@ -2695,33 +2695,33 @@ define i8 @atomicrmw_max_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: lbu a1, 0(a0) -; RV32I-NEXT: slli a0, s2, 24 -; RV32I-NEXT: srai s0, a0, 24 +; RV32I-NEXT: lbu a0, 0(a0) +; RV32I-NEXT: slli a1, a1, 24 +; RV32I-NEXT: srai s0, a1, 24 ; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: j .LBB39_2 ; RV32I-NEXT: .LBB39_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB39_2 Depth=1 -; RV32I-NEXT: sb a1, 11(sp) -; RV32I-NEXT: addi a3, zero, 5 -; RV32I-NEXT: addi a4, zero, 5 +; RV32I-NEXT: sb a0, 11(sp) ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s3 +; RV32I-NEXT: addi a3, zero, 5 +; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: call __atomic_compare_exchange_1 -; RV32I-NEXT: lb a1, 11(sp) -; RV32I-NEXT: bnez a0, .LBB39_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lb a0, 11(sp) +; RV32I-NEXT: bnez a1, .LBB39_4 ; RV32I-NEXT: .LBB39_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: slli a0, a1, 24 -; RV32I-NEXT: srai a0, a0, 24 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: blt s0, a0, .LBB39_1 +; RV32I-NEXT: slli a1, a0, 24 +; RV32I-NEXT: srai a1, a1, 24 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: blt s0, a1, .LBB39_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB39_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB39_1 ; RV32I-NEXT: .LBB39_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -2732,32 +2732,32 @@ define i8 @atomicrmw_max_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_max_i8_seq_cst: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a7, a3, a0 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: addi a3, zero, 24 +; RV32IA-NEXT: sub a6, a3, a2 +; RV32IA-NEXT: addi a4, zero, 255 +; RV32IA-NEXT: sll a7, a4, a2 ; RV32IA-NEXT: slli a1, a1, 24 ; RV32IA-NEXT: srai a1, a1, 24 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: addi a4, zero, 24 -; RV32IA-NEXT: sub a4, a4, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB39_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aqrl a5, (a6) -; RV32IA-NEXT: and a3, a5, a7 -; RV32IA-NEXT: mv a2, a5 -; RV32IA-NEXT: sll a3, a3, a4 -; RV32IA-NEXT: sra a3, a3, a4 -; RV32IA-NEXT: bge a3, a1, .LBB39_3 +; RV32IA-NEXT: lr.w.aqrl a5, (a0) +; RV32IA-NEXT: and a4, a5, a7 +; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sll a4, a4, a6 +; RV32IA-NEXT: sra a4, a4, a6 +; RV32IA-NEXT: bge a4, a1, .LBB39_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB39_1 Depth=1 -; RV32IA-NEXT: xor a2, a5, a1 -; RV32IA-NEXT: and a2, a2, a7 -; RV32IA-NEXT: xor a2, a5, a2 +; RV32IA-NEXT: xor a3, a5, a1 +; RV32IA-NEXT: and a3, a3, a7 +; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: .LBB39_3: # in Loop: Header=BB39_1 Depth=1 -; RV32IA-NEXT: sc.w.aqrl a2, a2, (a6) -; RV32IA-NEXT: bnez a2, .LBB39_1 +; RV32IA-NEXT: sc.w.aqrl a3, a3, (a0) +; RV32IA-NEXT: bnez a3, .LBB39_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a5, a0 +; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_max_i8_seq_cst: @@ -2770,33 +2770,33 @@ define i8 @atomicrmw_max_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: lbu a1, 0(a0) -; RV64I-NEXT: slli a0, s2, 56 -; RV64I-NEXT: srai s0, a0, 56 +; RV64I-NEXT: lbu a0, 0(a0) +; RV64I-NEXT: slli a1, a1, 56 +; RV64I-NEXT: srai s0, a1, 56 ; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: j .LBB39_2 ; RV64I-NEXT: .LBB39_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB39_2 Depth=1 -; RV64I-NEXT: sb a1, 7(sp) -; RV64I-NEXT: addi a3, zero, 5 -; RV64I-NEXT: addi a4, zero, 5 +; RV64I-NEXT: sb a0, 7(sp) ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s3 +; RV64I-NEXT: addi a3, zero, 5 +; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: call __atomic_compare_exchange_1 -; RV64I-NEXT: lb a1, 7(sp) -; RV64I-NEXT: bnez a0, .LBB39_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lb a0, 7(sp) +; RV64I-NEXT: bnez a1, .LBB39_4 ; RV64I-NEXT: .LBB39_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: slli a0, a1, 56 -; RV64I-NEXT: srai a0, a0, 56 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: blt s0, a0, .LBB39_1 +; RV64I-NEXT: slli a1, a0, 56 +; RV64I-NEXT: srai a1, a1, 56 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: blt s0, a1, .LBB39_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB39_2 Depth=1 ; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB39_1 ; RV64I-NEXT: .LBB39_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -2807,32 +2807,32 @@ define i8 @atomicrmw_max_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_max_i8_seq_cst: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a7, a3, a0 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: addi a3, zero, 56 +; RV64IA-NEXT: sub a6, a3, a2 +; RV64IA-NEXT: addi a4, zero, 255 +; RV64IA-NEXT: sllw a7, a4, a2 ; RV64IA-NEXT: slli a1, a1, 56 ; RV64IA-NEXT: srai a1, a1, 56 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: addi a4, zero, 56 -; RV64IA-NEXT: sub a4, a4, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB39_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aqrl a5, (a6) -; RV64IA-NEXT: and a3, a5, a7 -; RV64IA-NEXT: mv a2, a5 -; RV64IA-NEXT: sll a3, a3, a4 -; RV64IA-NEXT: sra a3, a3, a4 -; RV64IA-NEXT: bge a3, a1, .LBB39_3 +; RV64IA-NEXT: lr.w.aqrl a5, (a0) +; RV64IA-NEXT: and a4, a5, a7 +; RV64IA-NEXT: mv a3, a5 +; RV64IA-NEXT: sll a4, a4, a6 +; RV64IA-NEXT: sra a4, a4, a6 +; RV64IA-NEXT: bge a4, a1, .LBB39_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB39_1 Depth=1 -; RV64IA-NEXT: xor a2, a5, a1 -; RV64IA-NEXT: and a2, a2, a7 -; RV64IA-NEXT: xor a2, a5, a2 +; RV64IA-NEXT: xor a3, a5, a1 +; RV64IA-NEXT: and a3, a3, a7 +; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: .LBB39_3: # in Loop: Header=BB39_1 Depth=1 -; RV64IA-NEXT: sc.w.aqrl a2, a2, (a6) -; RV64IA-NEXT: bnez a2, .LBB39_1 +; RV64IA-NEXT: sc.w.aqrl a3, a3, (a0) +; RV64IA-NEXT: bnez a3, .LBB39_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a5, a0 +; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: ret %1 = atomicrmw max i8* %a, i8 %b seq_cst ret i8 %1 @@ -2849,33 +2849,33 @@ define i8 @atomicrmw_min_i8_monotonic(i8 *%a, i8 %b) nounwind { ; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: lbu a1, 0(a0) -; RV32I-NEXT: slli a0, s2, 24 -; RV32I-NEXT: srai s0, a0, 24 +; RV32I-NEXT: lbu a0, 0(a0) +; RV32I-NEXT: slli a1, a1, 24 +; RV32I-NEXT: srai s0, a1, 24 ; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: j .LBB40_2 ; RV32I-NEXT: .LBB40_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB40_2 Depth=1 -; RV32I-NEXT: sb a1, 11(sp) +; RV32I-NEXT: sb a0, 11(sp) ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: call __atomic_compare_exchange_1 -; RV32I-NEXT: lb a1, 11(sp) -; RV32I-NEXT: bnez a0, .LBB40_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lb a0, 11(sp) +; RV32I-NEXT: bnez a1, .LBB40_4 ; RV32I-NEXT: .LBB40_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: slli a0, a1, 24 -; RV32I-NEXT: srai a0, a0, 24 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: bge s0, a0, .LBB40_1 +; RV32I-NEXT: slli a1, a0, 24 +; RV32I-NEXT: srai a1, a1, 24 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: bge s0, a1, .LBB40_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB40_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB40_1 ; RV32I-NEXT: .LBB40_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -2886,32 +2886,32 @@ define i8 @atomicrmw_min_i8_monotonic(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_min_i8_monotonic: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a7, a3, a0 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: addi a3, zero, 24 +; RV32IA-NEXT: sub a6, a3, a2 +; RV32IA-NEXT: addi a4, zero, 255 +; RV32IA-NEXT: sll a7, a4, a2 ; RV32IA-NEXT: slli a1, a1, 24 ; RV32IA-NEXT: srai a1, a1, 24 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: addi a4, zero, 24 -; RV32IA-NEXT: sub a4, a4, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB40_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a5, (a6) -; RV32IA-NEXT: and a3, a5, a7 -; RV32IA-NEXT: mv a2, a5 -; RV32IA-NEXT: sll a3, a3, a4 -; RV32IA-NEXT: sra a3, a3, a4 -; RV32IA-NEXT: bge a1, a3, .LBB40_3 +; RV32IA-NEXT: lr.w a5, (a0) +; RV32IA-NEXT: and a4, a5, a7 +; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sll a4, a4, a6 +; RV32IA-NEXT: sra a4, a4, a6 +; RV32IA-NEXT: bge a1, a4, .LBB40_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB40_1 Depth=1 -; RV32IA-NEXT: xor a2, a5, a1 -; RV32IA-NEXT: and a2, a2, a7 -; RV32IA-NEXT: xor a2, a5, a2 +; RV32IA-NEXT: xor a3, a5, a1 +; RV32IA-NEXT: and a3, a3, a7 +; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: .LBB40_3: # in Loop: Header=BB40_1 Depth=1 -; RV32IA-NEXT: sc.w a2, a2, (a6) -; RV32IA-NEXT: bnez a2, .LBB40_1 +; RV32IA-NEXT: sc.w a3, a3, (a0) +; RV32IA-NEXT: bnez a3, .LBB40_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a5, a0 +; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_min_i8_monotonic: @@ -2924,33 +2924,33 @@ define i8 @atomicrmw_min_i8_monotonic(i8 *%a, i8 %b) nounwind { ; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: lbu a1, 0(a0) -; RV64I-NEXT: slli a0, s2, 56 -; RV64I-NEXT: srai s0, a0, 56 +; RV64I-NEXT: lbu a0, 0(a0) +; RV64I-NEXT: slli a1, a1, 56 +; RV64I-NEXT: srai s0, a1, 56 ; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: j .LBB40_2 ; RV64I-NEXT: .LBB40_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB40_2 Depth=1 -; RV64I-NEXT: sb a1, 7(sp) +; RV64I-NEXT: sb a0, 7(sp) ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: call __atomic_compare_exchange_1 -; RV64I-NEXT: lb a1, 7(sp) -; RV64I-NEXT: bnez a0, .LBB40_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lb a0, 7(sp) +; RV64I-NEXT: bnez a1, .LBB40_4 ; RV64I-NEXT: .LBB40_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: slli a0, a1, 56 -; RV64I-NEXT: srai a0, a0, 56 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: bge s0, a0, .LBB40_1 +; RV64I-NEXT: slli a1, a0, 56 +; RV64I-NEXT: srai a1, a1, 56 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bge s0, a1, .LBB40_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB40_2 Depth=1 ; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB40_1 ; RV64I-NEXT: .LBB40_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -2961,32 +2961,32 @@ define i8 @atomicrmw_min_i8_monotonic(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_min_i8_monotonic: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a7, a3, a0 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: addi a3, zero, 56 +; RV64IA-NEXT: sub a6, a3, a2 +; RV64IA-NEXT: addi a4, zero, 255 +; RV64IA-NEXT: sllw a7, a4, a2 ; RV64IA-NEXT: slli a1, a1, 56 ; RV64IA-NEXT: srai a1, a1, 56 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: addi a4, zero, 56 -; RV64IA-NEXT: sub a4, a4, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB40_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w a5, (a6) -; RV64IA-NEXT: and a3, a5, a7 -; RV64IA-NEXT: mv a2, a5 -; RV64IA-NEXT: sll a3, a3, a4 -; RV64IA-NEXT: sra a3, a3, a4 -; RV64IA-NEXT: bge a1, a3, .LBB40_3 +; RV64IA-NEXT: lr.w a5, (a0) +; RV64IA-NEXT: and a4, a5, a7 +; RV64IA-NEXT: mv a3, a5 +; RV64IA-NEXT: sll a4, a4, a6 +; RV64IA-NEXT: sra a4, a4, a6 +; RV64IA-NEXT: bge a1, a4, .LBB40_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB40_1 Depth=1 -; RV64IA-NEXT: xor a2, a5, a1 -; RV64IA-NEXT: and a2, a2, a7 -; RV64IA-NEXT: xor a2, a5, a2 +; RV64IA-NEXT: xor a3, a5, a1 +; RV64IA-NEXT: and a3, a3, a7 +; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: .LBB40_3: # in Loop: Header=BB40_1 Depth=1 -; RV64IA-NEXT: sc.w a2, a2, (a6) -; RV64IA-NEXT: bnez a2, .LBB40_1 +; RV64IA-NEXT: sc.w a3, a3, (a0) +; RV64IA-NEXT: bnez a3, .LBB40_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a5, a0 +; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: ret %1 = atomicrmw min i8* %a, i8 %b monotonic ret i8 %1 @@ -3003,33 +3003,33 @@ define i8 @atomicrmw_min_i8_acquire(i8 *%a, i8 %b) nounwind { ; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: lbu a1, 0(a0) -; RV32I-NEXT: slli a0, s2, 24 -; RV32I-NEXT: srai s0, a0, 24 +; RV32I-NEXT: lbu a0, 0(a0) +; RV32I-NEXT: slli a1, a1, 24 +; RV32I-NEXT: srai s0, a1, 24 ; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: j .LBB41_2 ; RV32I-NEXT: .LBB41_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB41_2 Depth=1 -; RV32I-NEXT: sb a1, 11(sp) -; RV32I-NEXT: addi a3, zero, 2 -; RV32I-NEXT: addi a4, zero, 2 +; RV32I-NEXT: sb a0, 11(sp) ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s3 +; RV32I-NEXT: addi a3, zero, 2 +; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: call __atomic_compare_exchange_1 -; RV32I-NEXT: lb a1, 11(sp) -; RV32I-NEXT: bnez a0, .LBB41_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lb a0, 11(sp) +; RV32I-NEXT: bnez a1, .LBB41_4 ; RV32I-NEXT: .LBB41_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: slli a0, a1, 24 -; RV32I-NEXT: srai a0, a0, 24 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: bge s0, a0, .LBB41_1 +; RV32I-NEXT: slli a1, a0, 24 +; RV32I-NEXT: srai a1, a1, 24 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: bge s0, a1, .LBB41_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB41_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB41_1 ; RV32I-NEXT: .LBB41_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -3040,32 +3040,32 @@ define i8 @atomicrmw_min_i8_acquire(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_min_i8_acquire: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a7, a3, a0 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: addi a3, zero, 24 +; RV32IA-NEXT: sub a6, a3, a2 +; RV32IA-NEXT: addi a4, zero, 255 +; RV32IA-NEXT: sll a7, a4, a2 ; RV32IA-NEXT: slli a1, a1, 24 ; RV32IA-NEXT: srai a1, a1, 24 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: addi a4, zero, 24 -; RV32IA-NEXT: sub a4, a4, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB41_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aq a5, (a6) -; RV32IA-NEXT: and a3, a5, a7 -; RV32IA-NEXT: mv a2, a5 -; RV32IA-NEXT: sll a3, a3, a4 -; RV32IA-NEXT: sra a3, a3, a4 -; RV32IA-NEXT: bge a1, a3, .LBB41_3 +; RV32IA-NEXT: lr.w.aq a5, (a0) +; RV32IA-NEXT: and a4, a5, a7 +; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sll a4, a4, a6 +; RV32IA-NEXT: sra a4, a4, a6 +; RV32IA-NEXT: bge a1, a4, .LBB41_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB41_1 Depth=1 -; RV32IA-NEXT: xor a2, a5, a1 -; RV32IA-NEXT: and a2, a2, a7 -; RV32IA-NEXT: xor a2, a5, a2 +; RV32IA-NEXT: xor a3, a5, a1 +; RV32IA-NEXT: and a3, a3, a7 +; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: .LBB41_3: # in Loop: Header=BB41_1 Depth=1 -; RV32IA-NEXT: sc.w a2, a2, (a6) -; RV32IA-NEXT: bnez a2, .LBB41_1 +; RV32IA-NEXT: sc.w a3, a3, (a0) +; RV32IA-NEXT: bnez a3, .LBB41_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a5, a0 +; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_min_i8_acquire: @@ -3078,33 +3078,33 @@ define i8 @atomicrmw_min_i8_acquire(i8 *%a, i8 %b) nounwind { ; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: lbu a1, 0(a0) -; RV64I-NEXT: slli a0, s2, 56 -; RV64I-NEXT: srai s0, a0, 56 +; RV64I-NEXT: lbu a0, 0(a0) +; RV64I-NEXT: slli a1, a1, 56 +; RV64I-NEXT: srai s0, a1, 56 ; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: j .LBB41_2 ; RV64I-NEXT: .LBB41_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB41_2 Depth=1 -; RV64I-NEXT: sb a1, 7(sp) -; RV64I-NEXT: addi a3, zero, 2 -; RV64I-NEXT: addi a4, zero, 2 +; RV64I-NEXT: sb a0, 7(sp) ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s3 +; RV64I-NEXT: addi a3, zero, 2 +; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: call __atomic_compare_exchange_1 -; RV64I-NEXT: lb a1, 7(sp) -; RV64I-NEXT: bnez a0, .LBB41_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lb a0, 7(sp) +; RV64I-NEXT: bnez a1, .LBB41_4 ; RV64I-NEXT: .LBB41_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: slli a0, a1, 56 -; RV64I-NEXT: srai a0, a0, 56 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: bge s0, a0, .LBB41_1 +; RV64I-NEXT: slli a1, a0, 56 +; RV64I-NEXT: srai a1, a1, 56 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bge s0, a1, .LBB41_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB41_2 Depth=1 ; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB41_1 ; RV64I-NEXT: .LBB41_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -3115,32 +3115,32 @@ define i8 @atomicrmw_min_i8_acquire(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_min_i8_acquire: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a7, a3, a0 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: addi a3, zero, 56 +; RV64IA-NEXT: sub a6, a3, a2 +; RV64IA-NEXT: addi a4, zero, 255 +; RV64IA-NEXT: sllw a7, a4, a2 ; RV64IA-NEXT: slli a1, a1, 56 ; RV64IA-NEXT: srai a1, a1, 56 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: addi a4, zero, 56 -; RV64IA-NEXT: sub a4, a4, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB41_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aq a5, (a6) -; RV64IA-NEXT: and a3, a5, a7 -; RV64IA-NEXT: mv a2, a5 -; RV64IA-NEXT: sll a3, a3, a4 -; RV64IA-NEXT: sra a3, a3, a4 -; RV64IA-NEXT: bge a1, a3, .LBB41_3 +; RV64IA-NEXT: lr.w.aq a5, (a0) +; RV64IA-NEXT: and a4, a5, a7 +; RV64IA-NEXT: mv a3, a5 +; RV64IA-NEXT: sll a4, a4, a6 +; RV64IA-NEXT: sra a4, a4, a6 +; RV64IA-NEXT: bge a1, a4, .LBB41_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB41_1 Depth=1 -; RV64IA-NEXT: xor a2, a5, a1 -; RV64IA-NEXT: and a2, a2, a7 -; RV64IA-NEXT: xor a2, a5, a2 +; RV64IA-NEXT: xor a3, a5, a1 +; RV64IA-NEXT: and a3, a3, a7 +; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: .LBB41_3: # in Loop: Header=BB41_1 Depth=1 -; RV64IA-NEXT: sc.w a2, a2, (a6) -; RV64IA-NEXT: bnez a2, .LBB41_1 +; RV64IA-NEXT: sc.w a3, a3, (a0) +; RV64IA-NEXT: bnez a3, .LBB41_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a5, a0 +; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: ret %1 = atomicrmw min i8* %a, i8 %b acquire ret i8 %1 @@ -3157,33 +3157,33 @@ define i8 @atomicrmw_min_i8_release(i8 *%a, i8 %b) nounwind { ; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: lbu a1, 0(a0) -; RV32I-NEXT: slli a0, s2, 24 -; RV32I-NEXT: srai s0, a0, 24 +; RV32I-NEXT: lbu a0, 0(a0) +; RV32I-NEXT: slli a1, a1, 24 +; RV32I-NEXT: srai s0, a1, 24 ; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: j .LBB42_2 ; RV32I-NEXT: .LBB42_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB42_2 Depth=1 -; RV32I-NEXT: sb a1, 11(sp) -; RV32I-NEXT: addi a3, zero, 3 +; RV32I-NEXT: sb a0, 11(sp) ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s3 +; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: call __atomic_compare_exchange_1 -; RV32I-NEXT: lb a1, 11(sp) -; RV32I-NEXT: bnez a0, .LBB42_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lb a0, 11(sp) +; RV32I-NEXT: bnez a1, .LBB42_4 ; RV32I-NEXT: .LBB42_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: slli a0, a1, 24 -; RV32I-NEXT: srai a0, a0, 24 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: bge s0, a0, .LBB42_1 +; RV32I-NEXT: slli a1, a0, 24 +; RV32I-NEXT: srai a1, a1, 24 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: bge s0, a1, .LBB42_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB42_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB42_1 ; RV32I-NEXT: .LBB42_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -3194,32 +3194,32 @@ define i8 @atomicrmw_min_i8_release(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_min_i8_release: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a7, a3, a0 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: addi a3, zero, 24 +; RV32IA-NEXT: sub a6, a3, a2 +; RV32IA-NEXT: addi a4, zero, 255 +; RV32IA-NEXT: sll a7, a4, a2 ; RV32IA-NEXT: slli a1, a1, 24 ; RV32IA-NEXT: srai a1, a1, 24 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: addi a4, zero, 24 -; RV32IA-NEXT: sub a4, a4, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB42_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a5, (a6) -; RV32IA-NEXT: and a3, a5, a7 -; RV32IA-NEXT: mv a2, a5 -; RV32IA-NEXT: sll a3, a3, a4 -; RV32IA-NEXT: sra a3, a3, a4 -; RV32IA-NEXT: bge a1, a3, .LBB42_3 +; RV32IA-NEXT: lr.w a5, (a0) +; RV32IA-NEXT: and a4, a5, a7 +; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sll a4, a4, a6 +; RV32IA-NEXT: sra a4, a4, a6 +; RV32IA-NEXT: bge a1, a4, .LBB42_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB42_1 Depth=1 -; RV32IA-NEXT: xor a2, a5, a1 -; RV32IA-NEXT: and a2, a2, a7 -; RV32IA-NEXT: xor a2, a5, a2 +; RV32IA-NEXT: xor a3, a5, a1 +; RV32IA-NEXT: and a3, a3, a7 +; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: .LBB42_3: # in Loop: Header=BB42_1 Depth=1 -; RV32IA-NEXT: sc.w.rl a2, a2, (a6) -; RV32IA-NEXT: bnez a2, .LBB42_1 +; RV32IA-NEXT: sc.w.rl a3, a3, (a0) +; RV32IA-NEXT: bnez a3, .LBB42_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a5, a0 +; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_min_i8_release: @@ -3232,33 +3232,33 @@ define i8 @atomicrmw_min_i8_release(i8 *%a, i8 %b) nounwind { ; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: lbu a1, 0(a0) -; RV64I-NEXT: slli a0, s2, 56 -; RV64I-NEXT: srai s0, a0, 56 +; RV64I-NEXT: lbu a0, 0(a0) +; RV64I-NEXT: slli a1, a1, 56 +; RV64I-NEXT: srai s0, a1, 56 ; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: j .LBB42_2 ; RV64I-NEXT: .LBB42_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB42_2 Depth=1 -; RV64I-NEXT: sb a1, 7(sp) -; RV64I-NEXT: addi a3, zero, 3 +; RV64I-NEXT: sb a0, 7(sp) ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s3 +; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: call __atomic_compare_exchange_1 -; RV64I-NEXT: lb a1, 7(sp) -; RV64I-NEXT: bnez a0, .LBB42_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lb a0, 7(sp) +; RV64I-NEXT: bnez a1, .LBB42_4 ; RV64I-NEXT: .LBB42_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: slli a0, a1, 56 -; RV64I-NEXT: srai a0, a0, 56 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: bge s0, a0, .LBB42_1 +; RV64I-NEXT: slli a1, a0, 56 +; RV64I-NEXT: srai a1, a1, 56 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bge s0, a1, .LBB42_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB42_2 Depth=1 ; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB42_1 ; RV64I-NEXT: .LBB42_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -3269,32 +3269,32 @@ define i8 @atomicrmw_min_i8_release(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_min_i8_release: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a7, a3, a0 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: addi a3, zero, 56 +; RV64IA-NEXT: sub a6, a3, a2 +; RV64IA-NEXT: addi a4, zero, 255 +; RV64IA-NEXT: sllw a7, a4, a2 ; RV64IA-NEXT: slli a1, a1, 56 ; RV64IA-NEXT: srai a1, a1, 56 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: addi a4, zero, 56 -; RV64IA-NEXT: sub a4, a4, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB42_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w a5, (a6) -; RV64IA-NEXT: and a3, a5, a7 -; RV64IA-NEXT: mv a2, a5 -; RV64IA-NEXT: sll a3, a3, a4 -; RV64IA-NEXT: sra a3, a3, a4 -; RV64IA-NEXT: bge a1, a3, .LBB42_3 +; RV64IA-NEXT: lr.w a5, (a0) +; RV64IA-NEXT: and a4, a5, a7 +; RV64IA-NEXT: mv a3, a5 +; RV64IA-NEXT: sll a4, a4, a6 +; RV64IA-NEXT: sra a4, a4, a6 +; RV64IA-NEXT: bge a1, a4, .LBB42_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB42_1 Depth=1 -; RV64IA-NEXT: xor a2, a5, a1 -; RV64IA-NEXT: and a2, a2, a7 -; RV64IA-NEXT: xor a2, a5, a2 +; RV64IA-NEXT: xor a3, a5, a1 +; RV64IA-NEXT: and a3, a3, a7 +; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: .LBB42_3: # in Loop: Header=BB42_1 Depth=1 -; RV64IA-NEXT: sc.w.rl a2, a2, (a6) -; RV64IA-NEXT: bnez a2, .LBB42_1 +; RV64IA-NEXT: sc.w.rl a3, a3, (a0) +; RV64IA-NEXT: bnez a3, .LBB42_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a5, a0 +; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: ret %1 = atomicrmw min i8* %a, i8 %b release ret i8 %1 @@ -3311,33 +3311,33 @@ define i8 @atomicrmw_min_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: lbu a1, 0(a0) -; RV32I-NEXT: slli a0, s2, 24 -; RV32I-NEXT: srai s0, a0, 24 +; RV32I-NEXT: lbu a0, 0(a0) +; RV32I-NEXT: slli a1, a1, 24 +; RV32I-NEXT: srai s0, a1, 24 ; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: j .LBB43_2 ; RV32I-NEXT: .LBB43_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB43_2 Depth=1 -; RV32I-NEXT: sb a1, 11(sp) -; RV32I-NEXT: addi a3, zero, 4 -; RV32I-NEXT: addi a4, zero, 2 +; RV32I-NEXT: sb a0, 11(sp) ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s3 +; RV32I-NEXT: addi a3, zero, 4 +; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: call __atomic_compare_exchange_1 -; RV32I-NEXT: lb a1, 11(sp) -; RV32I-NEXT: bnez a0, .LBB43_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lb a0, 11(sp) +; RV32I-NEXT: bnez a1, .LBB43_4 ; RV32I-NEXT: .LBB43_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: slli a0, a1, 24 -; RV32I-NEXT: srai a0, a0, 24 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: bge s0, a0, .LBB43_1 +; RV32I-NEXT: slli a1, a0, 24 +; RV32I-NEXT: srai a1, a1, 24 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: bge s0, a1, .LBB43_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB43_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB43_1 ; RV32I-NEXT: .LBB43_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -3348,32 +3348,32 @@ define i8 @atomicrmw_min_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_min_i8_acq_rel: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a7, a3, a0 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: addi a3, zero, 24 +; RV32IA-NEXT: sub a6, a3, a2 +; RV32IA-NEXT: addi a4, zero, 255 +; RV32IA-NEXT: sll a7, a4, a2 ; RV32IA-NEXT: slli a1, a1, 24 ; RV32IA-NEXT: srai a1, a1, 24 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: addi a4, zero, 24 -; RV32IA-NEXT: sub a4, a4, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB43_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aq a5, (a6) -; RV32IA-NEXT: and a3, a5, a7 -; RV32IA-NEXT: mv a2, a5 -; RV32IA-NEXT: sll a3, a3, a4 -; RV32IA-NEXT: sra a3, a3, a4 -; RV32IA-NEXT: bge a1, a3, .LBB43_3 +; RV32IA-NEXT: lr.w.aq a5, (a0) +; RV32IA-NEXT: and a4, a5, a7 +; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sll a4, a4, a6 +; RV32IA-NEXT: sra a4, a4, a6 +; RV32IA-NEXT: bge a1, a4, .LBB43_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB43_1 Depth=1 -; RV32IA-NEXT: xor a2, a5, a1 -; RV32IA-NEXT: and a2, a2, a7 -; RV32IA-NEXT: xor a2, a5, a2 +; RV32IA-NEXT: xor a3, a5, a1 +; RV32IA-NEXT: and a3, a3, a7 +; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: .LBB43_3: # in Loop: Header=BB43_1 Depth=1 -; RV32IA-NEXT: sc.w.rl a2, a2, (a6) -; RV32IA-NEXT: bnez a2, .LBB43_1 +; RV32IA-NEXT: sc.w.rl a3, a3, (a0) +; RV32IA-NEXT: bnez a3, .LBB43_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a5, a0 +; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_min_i8_acq_rel: @@ -3386,33 +3386,33 @@ define i8 @atomicrmw_min_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: lbu a1, 0(a0) -; RV64I-NEXT: slli a0, s2, 56 -; RV64I-NEXT: srai s0, a0, 56 +; RV64I-NEXT: lbu a0, 0(a0) +; RV64I-NEXT: slli a1, a1, 56 +; RV64I-NEXT: srai s0, a1, 56 ; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: j .LBB43_2 ; RV64I-NEXT: .LBB43_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB43_2 Depth=1 -; RV64I-NEXT: sb a1, 7(sp) -; RV64I-NEXT: addi a3, zero, 4 -; RV64I-NEXT: addi a4, zero, 2 +; RV64I-NEXT: sb a0, 7(sp) ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s3 +; RV64I-NEXT: addi a3, zero, 4 +; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: call __atomic_compare_exchange_1 -; RV64I-NEXT: lb a1, 7(sp) -; RV64I-NEXT: bnez a0, .LBB43_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lb a0, 7(sp) +; RV64I-NEXT: bnez a1, .LBB43_4 ; RV64I-NEXT: .LBB43_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: slli a0, a1, 56 -; RV64I-NEXT: srai a0, a0, 56 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: bge s0, a0, .LBB43_1 +; RV64I-NEXT: slli a1, a0, 56 +; RV64I-NEXT: srai a1, a1, 56 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bge s0, a1, .LBB43_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB43_2 Depth=1 ; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB43_1 ; RV64I-NEXT: .LBB43_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -3423,32 +3423,32 @@ define i8 @atomicrmw_min_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_min_i8_acq_rel: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a7, a3, a0 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: addi a3, zero, 56 +; RV64IA-NEXT: sub a6, a3, a2 +; RV64IA-NEXT: addi a4, zero, 255 +; RV64IA-NEXT: sllw a7, a4, a2 ; RV64IA-NEXT: slli a1, a1, 56 ; RV64IA-NEXT: srai a1, a1, 56 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: addi a4, zero, 56 -; RV64IA-NEXT: sub a4, a4, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB43_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aq a5, (a6) -; RV64IA-NEXT: and a3, a5, a7 -; RV64IA-NEXT: mv a2, a5 -; RV64IA-NEXT: sll a3, a3, a4 -; RV64IA-NEXT: sra a3, a3, a4 -; RV64IA-NEXT: bge a1, a3, .LBB43_3 +; RV64IA-NEXT: lr.w.aq a5, (a0) +; RV64IA-NEXT: and a4, a5, a7 +; RV64IA-NEXT: mv a3, a5 +; RV64IA-NEXT: sll a4, a4, a6 +; RV64IA-NEXT: sra a4, a4, a6 +; RV64IA-NEXT: bge a1, a4, .LBB43_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB43_1 Depth=1 -; RV64IA-NEXT: xor a2, a5, a1 -; RV64IA-NEXT: and a2, a2, a7 -; RV64IA-NEXT: xor a2, a5, a2 +; RV64IA-NEXT: xor a3, a5, a1 +; RV64IA-NEXT: and a3, a3, a7 +; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: .LBB43_3: # in Loop: Header=BB43_1 Depth=1 -; RV64IA-NEXT: sc.w.rl a2, a2, (a6) -; RV64IA-NEXT: bnez a2, .LBB43_1 +; RV64IA-NEXT: sc.w.rl a3, a3, (a0) +; RV64IA-NEXT: bnez a3, .LBB43_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a5, a0 +; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: ret %1 = atomicrmw min i8* %a, i8 %b acq_rel ret i8 %1 @@ -3465,33 +3465,33 @@ define i8 @atomicrmw_min_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: lbu a1, 0(a0) -; RV32I-NEXT: slli a0, s2, 24 -; RV32I-NEXT: srai s0, a0, 24 +; RV32I-NEXT: lbu a0, 0(a0) +; RV32I-NEXT: slli a1, a1, 24 +; RV32I-NEXT: srai s0, a1, 24 ; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: j .LBB44_2 ; RV32I-NEXT: .LBB44_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1 -; RV32I-NEXT: sb a1, 11(sp) -; RV32I-NEXT: addi a3, zero, 5 -; RV32I-NEXT: addi a4, zero, 5 +; RV32I-NEXT: sb a0, 11(sp) ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s3 +; RV32I-NEXT: addi a3, zero, 5 +; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: call __atomic_compare_exchange_1 -; RV32I-NEXT: lb a1, 11(sp) -; RV32I-NEXT: bnez a0, .LBB44_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lb a0, 11(sp) +; RV32I-NEXT: bnez a1, .LBB44_4 ; RV32I-NEXT: .LBB44_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: slli a0, a1, 24 -; RV32I-NEXT: srai a0, a0, 24 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: bge s0, a0, .LBB44_1 +; RV32I-NEXT: slli a1, a0, 24 +; RV32I-NEXT: srai a1, a1, 24 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: bge s0, a1, .LBB44_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB44_1 ; RV32I-NEXT: .LBB44_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -3502,32 +3502,32 @@ define i8 @atomicrmw_min_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_min_i8_seq_cst: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a7, a3, a0 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: addi a3, zero, 24 +; RV32IA-NEXT: sub a6, a3, a2 +; RV32IA-NEXT: addi a4, zero, 255 +; RV32IA-NEXT: sll a7, a4, a2 ; RV32IA-NEXT: slli a1, a1, 24 ; RV32IA-NEXT: srai a1, a1, 24 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: addi a4, zero, 24 -; RV32IA-NEXT: sub a4, a4, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB44_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aqrl a5, (a6) -; RV32IA-NEXT: and a3, a5, a7 -; RV32IA-NEXT: mv a2, a5 -; RV32IA-NEXT: sll a3, a3, a4 -; RV32IA-NEXT: sra a3, a3, a4 -; RV32IA-NEXT: bge a1, a3, .LBB44_3 +; RV32IA-NEXT: lr.w.aqrl a5, (a0) +; RV32IA-NEXT: and a4, a5, a7 +; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sll a4, a4, a6 +; RV32IA-NEXT: sra a4, a4, a6 +; RV32IA-NEXT: bge a1, a4, .LBB44_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB44_1 Depth=1 -; RV32IA-NEXT: xor a2, a5, a1 -; RV32IA-NEXT: and a2, a2, a7 -; RV32IA-NEXT: xor a2, a5, a2 +; RV32IA-NEXT: xor a3, a5, a1 +; RV32IA-NEXT: and a3, a3, a7 +; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: .LBB44_3: # in Loop: Header=BB44_1 Depth=1 -; RV32IA-NEXT: sc.w.aqrl a2, a2, (a6) -; RV32IA-NEXT: bnez a2, .LBB44_1 +; RV32IA-NEXT: sc.w.aqrl a3, a3, (a0) +; RV32IA-NEXT: bnez a3, .LBB44_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a5, a0 +; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_min_i8_seq_cst: @@ -3540,33 +3540,33 @@ define i8 @atomicrmw_min_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: lbu a1, 0(a0) -; RV64I-NEXT: slli a0, s2, 56 -; RV64I-NEXT: srai s0, a0, 56 +; RV64I-NEXT: lbu a0, 0(a0) +; RV64I-NEXT: slli a1, a1, 56 +; RV64I-NEXT: srai s0, a1, 56 ; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: j .LBB44_2 ; RV64I-NEXT: .LBB44_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB44_2 Depth=1 -; RV64I-NEXT: sb a1, 7(sp) -; RV64I-NEXT: addi a3, zero, 5 -; RV64I-NEXT: addi a4, zero, 5 +; RV64I-NEXT: sb a0, 7(sp) ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s3 +; RV64I-NEXT: addi a3, zero, 5 +; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: call __atomic_compare_exchange_1 -; RV64I-NEXT: lb a1, 7(sp) -; RV64I-NEXT: bnez a0, .LBB44_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lb a0, 7(sp) +; RV64I-NEXT: bnez a1, .LBB44_4 ; RV64I-NEXT: .LBB44_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: slli a0, a1, 56 -; RV64I-NEXT: srai a0, a0, 56 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: bge s0, a0, .LBB44_1 +; RV64I-NEXT: slli a1, a0, 56 +; RV64I-NEXT: srai a1, a1, 56 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bge s0, a1, .LBB44_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB44_2 Depth=1 ; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB44_1 ; RV64I-NEXT: .LBB44_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -3577,32 +3577,32 @@ define i8 @atomicrmw_min_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_min_i8_seq_cst: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a7, a3, a0 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: addi a3, zero, 56 +; RV64IA-NEXT: sub a6, a3, a2 +; RV64IA-NEXT: addi a4, zero, 255 +; RV64IA-NEXT: sllw a7, a4, a2 ; RV64IA-NEXT: slli a1, a1, 56 ; RV64IA-NEXT: srai a1, a1, 56 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: addi a4, zero, 56 -; RV64IA-NEXT: sub a4, a4, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB44_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aqrl a5, (a6) -; RV64IA-NEXT: and a3, a5, a7 -; RV64IA-NEXT: mv a2, a5 -; RV64IA-NEXT: sll a3, a3, a4 -; RV64IA-NEXT: sra a3, a3, a4 -; RV64IA-NEXT: bge a1, a3, .LBB44_3 +; RV64IA-NEXT: lr.w.aqrl a5, (a0) +; RV64IA-NEXT: and a4, a5, a7 +; RV64IA-NEXT: mv a3, a5 +; RV64IA-NEXT: sll a4, a4, a6 +; RV64IA-NEXT: sra a4, a4, a6 +; RV64IA-NEXT: bge a1, a4, .LBB44_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB44_1 Depth=1 -; RV64IA-NEXT: xor a2, a5, a1 -; RV64IA-NEXT: and a2, a2, a7 -; RV64IA-NEXT: xor a2, a5, a2 +; RV64IA-NEXT: xor a3, a5, a1 +; RV64IA-NEXT: and a3, a3, a7 +; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: .LBB44_3: # in Loop: Header=BB44_1 Depth=1 -; RV64IA-NEXT: sc.w.aqrl a2, a2, (a6) -; RV64IA-NEXT: bnez a2, .LBB44_1 +; RV64IA-NEXT: sc.w.aqrl a3, a3, (a0) +; RV64IA-NEXT: bnez a3, .LBB44_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a5, a0 +; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: ret %1 = atomicrmw min i8* %a, i8 %b seq_cst ret i8 %1 @@ -3617,33 +3617,33 @@ define i8 @atomicrmw_umax_i8_monotonic(i8 *%a, i8 %b) nounwind { ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s3, 12(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lbu a3, 0(a0) -; RV32I-NEXT: mv s3, a1 -; RV32I-NEXT: andi s1, a1, 255 -; RV32I-NEXT: addi s2, sp, 11 +; RV32I-NEXT: mv s2, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lbu a0, 0(a0) +; RV32I-NEXT: andi s0, a1, 255 +; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: j .LBB45_2 ; RV32I-NEXT: .LBB45_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB45_2 Depth=1 -; RV32I-NEXT: sb a3, 11(sp) -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: mv a1, s2 +; RV32I-NEXT: sb a0, 11(sp) +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: call __atomic_compare_exchange_1 -; RV32I-NEXT: lb a3, 11(sp) -; RV32I-NEXT: bnez a0, .LBB45_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lb a0, 11(sp) +; RV32I-NEXT: bnez a1, .LBB45_4 ; RV32I-NEXT: .LBB45_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: andi a0, a3, 255 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bltu s1, a0, .LBB45_1 +; RV32I-NEXT: andi a1, a0, 255 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: bltu s0, a1, .LBB45_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB45_2 Depth=1 -; RV32I-NEXT: mv a2, s3 +; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB45_1 ; RV32I-NEXT: .LBB45_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -3654,27 +3654,27 @@ define i8 @atomicrmw_umax_i8_monotonic(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_umax_i8_monotonic: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a3, a3, a0 +; RV32IA-NEXT: sll a6, a3, a2 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB45_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a4, (a6) -; RV32IA-NEXT: and a2, a4, a3 +; RV32IA-NEXT: lr.w a4, (a0) +; RV32IA-NEXT: and a3, a4, a6 ; RV32IA-NEXT: mv a5, a4 -; RV32IA-NEXT: bgeu a2, a1, .LBB45_3 +; RV32IA-NEXT: bgeu a3, a1, .LBB45_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB45_1 Depth=1 ; RV32IA-NEXT: xor a5, a4, a1 -; RV32IA-NEXT: and a5, a5, a3 +; RV32IA-NEXT: and a5, a5, a6 ; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: .LBB45_3: # in Loop: Header=BB45_1 Depth=1 -; RV32IA-NEXT: sc.w a5, a5, (a6) +; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB45_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a4, a0 +; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umax_i8_monotonic: @@ -3685,33 +3685,33 @@ define i8 @atomicrmw_umax_i8_monotonic(i8 *%a, i8 %b) nounwind { ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s3, 8(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: lbu a3, 0(a0) -; RV64I-NEXT: mv s3, a1 -; RV64I-NEXT: andi s1, a1, 255 -; RV64I-NEXT: addi s2, sp, 7 +; RV64I-NEXT: mv s2, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: lbu a0, 0(a0) +; RV64I-NEXT: andi s0, a1, 255 +; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: j .LBB45_2 ; RV64I-NEXT: .LBB45_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB45_2 Depth=1 -; RV64I-NEXT: sb a3, 7(sp) -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 +; RV64I-NEXT: sb a0, 7(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: call __atomic_compare_exchange_1 -; RV64I-NEXT: lb a3, 7(sp) -; RV64I-NEXT: bnez a0, .LBB45_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lb a0, 7(sp) +; RV64I-NEXT: bnez a1, .LBB45_4 ; RV64I-NEXT: .LBB45_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: andi a0, a3, 255 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bltu s1, a0, .LBB45_1 +; RV64I-NEXT: andi a1, a0, 255 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bltu s0, a1, .LBB45_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB45_2 Depth=1 -; RV64I-NEXT: mv a2, s3 +; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB45_1 ; RV64I-NEXT: .LBB45_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -3722,27 +3722,27 @@ define i8 @atomicrmw_umax_i8_monotonic(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_umax_i8_monotonic: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a3, a3, a0 +; RV64IA-NEXT: sllw a6, a3, a2 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB45_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w a4, (a6) -; RV64IA-NEXT: and a2, a4, a3 +; RV64IA-NEXT: lr.w a4, (a0) +; RV64IA-NEXT: and a3, a4, a6 ; RV64IA-NEXT: mv a5, a4 -; RV64IA-NEXT: bgeu a2, a1, .LBB45_3 +; RV64IA-NEXT: bgeu a3, a1, .LBB45_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB45_1 Depth=1 ; RV64IA-NEXT: xor a5, a4, a1 -; RV64IA-NEXT: and a5, a5, a3 +; RV64IA-NEXT: and a5, a5, a6 ; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: .LBB45_3: # in Loop: Header=BB45_1 Depth=1 -; RV64IA-NEXT: sc.w a5, a5, (a6) +; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB45_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a4, a0 +; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: ret %1 = atomicrmw umax i8* %a, i8 %b monotonic ret i8 %1 @@ -3757,33 +3757,33 @@ define i8 @atomicrmw_umax_i8_acquire(i8 *%a, i8 %b) nounwind { ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s3, 12(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lbu a3, 0(a0) -; RV32I-NEXT: mv s3, a1 -; RV32I-NEXT: andi s1, a1, 255 -; RV32I-NEXT: addi s2, sp, 11 +; RV32I-NEXT: mv s2, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lbu a0, 0(a0) +; RV32I-NEXT: andi s0, a1, 255 +; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: j .LBB46_2 ; RV32I-NEXT: .LBB46_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1 -; RV32I-NEXT: sb a3, 11(sp) +; RV32I-NEXT: sb a0, 11(sp) +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a4, zero, 2 -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: call __atomic_compare_exchange_1 -; RV32I-NEXT: lb a3, 11(sp) -; RV32I-NEXT: bnez a0, .LBB46_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lb a0, 11(sp) +; RV32I-NEXT: bnez a1, .LBB46_4 ; RV32I-NEXT: .LBB46_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: andi a0, a3, 255 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bltu s1, a0, .LBB46_1 +; RV32I-NEXT: andi a1, a0, 255 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: bltu s0, a1, .LBB46_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1 -; RV32I-NEXT: mv a2, s3 +; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB46_1 ; RV32I-NEXT: .LBB46_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -3794,27 +3794,27 @@ define i8 @atomicrmw_umax_i8_acquire(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_umax_i8_acquire: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a3, a3, a0 +; RV32IA-NEXT: sll a6, a3, a2 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aq a4, (a6) -; RV32IA-NEXT: and a2, a4, a3 +; RV32IA-NEXT: lr.w.aq a4, (a0) +; RV32IA-NEXT: and a3, a4, a6 ; RV32IA-NEXT: mv a5, a4 -; RV32IA-NEXT: bgeu a2, a1, .LBB46_3 +; RV32IA-NEXT: bgeu a3, a1, .LBB46_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB46_1 Depth=1 ; RV32IA-NEXT: xor a5, a4, a1 -; RV32IA-NEXT: and a5, a5, a3 +; RV32IA-NEXT: and a5, a5, a6 ; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: .LBB46_3: # in Loop: Header=BB46_1 Depth=1 -; RV32IA-NEXT: sc.w a5, a5, (a6) +; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB46_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a4, a0 +; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umax_i8_acquire: @@ -3825,33 +3825,33 @@ define i8 @atomicrmw_umax_i8_acquire(i8 *%a, i8 %b) nounwind { ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s3, 8(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: lbu a3, 0(a0) -; RV64I-NEXT: mv s3, a1 -; RV64I-NEXT: andi s1, a1, 255 -; RV64I-NEXT: addi s2, sp, 7 +; RV64I-NEXT: mv s2, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: lbu a0, 0(a0) +; RV64I-NEXT: andi s0, a1, 255 +; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: j .LBB46_2 ; RV64I-NEXT: .LBB46_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB46_2 Depth=1 -; RV64I-NEXT: sb a3, 7(sp) +; RV64I-NEXT: sb a0, 7(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a4, zero, 2 -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: call __atomic_compare_exchange_1 -; RV64I-NEXT: lb a3, 7(sp) -; RV64I-NEXT: bnez a0, .LBB46_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lb a0, 7(sp) +; RV64I-NEXT: bnez a1, .LBB46_4 ; RV64I-NEXT: .LBB46_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: andi a0, a3, 255 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bltu s1, a0, .LBB46_1 +; RV64I-NEXT: andi a1, a0, 255 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bltu s0, a1, .LBB46_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB46_2 Depth=1 -; RV64I-NEXT: mv a2, s3 +; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB46_1 ; RV64I-NEXT: .LBB46_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -3862,27 +3862,27 @@ define i8 @atomicrmw_umax_i8_acquire(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_umax_i8_acquire: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a3, a3, a0 +; RV64IA-NEXT: sllw a6, a3, a2 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aq a4, (a6) -; RV64IA-NEXT: and a2, a4, a3 +; RV64IA-NEXT: lr.w.aq a4, (a0) +; RV64IA-NEXT: and a3, a4, a6 ; RV64IA-NEXT: mv a5, a4 -; RV64IA-NEXT: bgeu a2, a1, .LBB46_3 +; RV64IA-NEXT: bgeu a3, a1, .LBB46_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB46_1 Depth=1 ; RV64IA-NEXT: xor a5, a4, a1 -; RV64IA-NEXT: and a5, a5, a3 +; RV64IA-NEXT: and a5, a5, a6 ; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: .LBB46_3: # in Loop: Header=BB46_1 Depth=1 -; RV64IA-NEXT: sc.w a5, a5, (a6) +; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB46_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a4, a0 +; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: ret %1 = atomicrmw umax i8* %a, i8 %b acquire ret i8 %1 @@ -3897,33 +3897,33 @@ define i8 @atomicrmw_umax_i8_release(i8 *%a, i8 %b) nounwind { ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s3, 12(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lbu a3, 0(a0) -; RV32I-NEXT: mv s3, a1 -; RV32I-NEXT: andi s1, a1, 255 -; RV32I-NEXT: addi s2, sp, 11 +; RV32I-NEXT: mv s2, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lbu a0, 0(a0) +; RV32I-NEXT: andi s0, a1, 255 +; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: j .LBB47_2 ; RV32I-NEXT: .LBB47_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB47_2 Depth=1 -; RV32I-NEXT: sb a3, 11(sp) +; RV32I-NEXT: sb a0, 11(sp) +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: addi a3, zero, 3 -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: call __atomic_compare_exchange_1 -; RV32I-NEXT: lb a3, 11(sp) -; RV32I-NEXT: bnez a0, .LBB47_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lb a0, 11(sp) +; RV32I-NEXT: bnez a1, .LBB47_4 ; RV32I-NEXT: .LBB47_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: andi a0, a3, 255 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bltu s1, a0, .LBB47_1 +; RV32I-NEXT: andi a1, a0, 255 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: bltu s0, a1, .LBB47_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB47_2 Depth=1 -; RV32I-NEXT: mv a2, s3 +; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB47_1 ; RV32I-NEXT: .LBB47_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -3934,27 +3934,27 @@ define i8 @atomicrmw_umax_i8_release(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_umax_i8_release: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a3, a3, a0 +; RV32IA-NEXT: sll a6, a3, a2 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a4, (a6) -; RV32IA-NEXT: and a2, a4, a3 +; RV32IA-NEXT: lr.w a4, (a0) +; RV32IA-NEXT: and a3, a4, a6 ; RV32IA-NEXT: mv a5, a4 -; RV32IA-NEXT: bgeu a2, a1, .LBB47_3 +; RV32IA-NEXT: bgeu a3, a1, .LBB47_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB47_1 Depth=1 ; RV32IA-NEXT: xor a5, a4, a1 -; RV32IA-NEXT: and a5, a5, a3 +; RV32IA-NEXT: and a5, a5, a6 ; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: .LBB47_3: # in Loop: Header=BB47_1 Depth=1 -; RV32IA-NEXT: sc.w.rl a5, a5, (a6) +; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB47_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a4, a0 +; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umax_i8_release: @@ -3965,33 +3965,33 @@ define i8 @atomicrmw_umax_i8_release(i8 *%a, i8 %b) nounwind { ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s3, 8(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: lbu a3, 0(a0) -; RV64I-NEXT: mv s3, a1 -; RV64I-NEXT: andi s1, a1, 255 -; RV64I-NEXT: addi s2, sp, 7 +; RV64I-NEXT: mv s2, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: lbu a0, 0(a0) +; RV64I-NEXT: andi s0, a1, 255 +; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: j .LBB47_2 ; RV64I-NEXT: .LBB47_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB47_2 Depth=1 -; RV64I-NEXT: sb a3, 7(sp) +; RV64I-NEXT: sb a0, 7(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: addi a3, zero, 3 -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: call __atomic_compare_exchange_1 -; RV64I-NEXT: lb a3, 7(sp) -; RV64I-NEXT: bnez a0, .LBB47_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lb a0, 7(sp) +; RV64I-NEXT: bnez a1, .LBB47_4 ; RV64I-NEXT: .LBB47_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: andi a0, a3, 255 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bltu s1, a0, .LBB47_1 +; RV64I-NEXT: andi a1, a0, 255 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bltu s0, a1, .LBB47_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB47_2 Depth=1 -; RV64I-NEXT: mv a2, s3 +; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB47_1 ; RV64I-NEXT: .LBB47_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -4002,27 +4002,27 @@ define i8 @atomicrmw_umax_i8_release(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_umax_i8_release: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a3, a3, a0 +; RV64IA-NEXT: sllw a6, a3, a2 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w a4, (a6) -; RV64IA-NEXT: and a2, a4, a3 +; RV64IA-NEXT: lr.w a4, (a0) +; RV64IA-NEXT: and a3, a4, a6 ; RV64IA-NEXT: mv a5, a4 -; RV64IA-NEXT: bgeu a2, a1, .LBB47_3 +; RV64IA-NEXT: bgeu a3, a1, .LBB47_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB47_1 Depth=1 ; RV64IA-NEXT: xor a5, a4, a1 -; RV64IA-NEXT: and a5, a5, a3 +; RV64IA-NEXT: and a5, a5, a6 ; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: .LBB47_3: # in Loop: Header=BB47_1 Depth=1 -; RV64IA-NEXT: sc.w.rl a5, a5, (a6) +; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB47_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a4, a0 +; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: ret %1 = atomicrmw umax i8* %a, i8 %b release ret i8 %1 @@ -4037,33 +4037,33 @@ define i8 @atomicrmw_umax_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s3, 12(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lbu a3, 0(a0) -; RV32I-NEXT: mv s3, a1 -; RV32I-NEXT: andi s1, a1, 255 -; RV32I-NEXT: addi s2, sp, 11 +; RV32I-NEXT: mv s2, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lbu a0, 0(a0) +; RV32I-NEXT: andi s0, a1, 255 +; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: j .LBB48_2 ; RV32I-NEXT: .LBB48_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB48_2 Depth=1 -; RV32I-NEXT: sb a3, 11(sp) +; RV32I-NEXT: sb a0, 11(sp) +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a4, zero, 2 -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: call __atomic_compare_exchange_1 -; RV32I-NEXT: lb a3, 11(sp) -; RV32I-NEXT: bnez a0, .LBB48_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lb a0, 11(sp) +; RV32I-NEXT: bnez a1, .LBB48_4 ; RV32I-NEXT: .LBB48_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: andi a0, a3, 255 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bltu s1, a0, .LBB48_1 +; RV32I-NEXT: andi a1, a0, 255 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: bltu s0, a1, .LBB48_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB48_2 Depth=1 -; RV32I-NEXT: mv a2, s3 +; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB48_1 ; RV32I-NEXT: .LBB48_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -4074,27 +4074,27 @@ define i8 @atomicrmw_umax_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_umax_i8_acq_rel: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a3, a3, a0 +; RV32IA-NEXT: sll a6, a3, a2 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aq a4, (a6) -; RV32IA-NEXT: and a2, a4, a3 +; RV32IA-NEXT: lr.w.aq a4, (a0) +; RV32IA-NEXT: and a3, a4, a6 ; RV32IA-NEXT: mv a5, a4 -; RV32IA-NEXT: bgeu a2, a1, .LBB48_3 +; RV32IA-NEXT: bgeu a3, a1, .LBB48_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB48_1 Depth=1 ; RV32IA-NEXT: xor a5, a4, a1 -; RV32IA-NEXT: and a5, a5, a3 +; RV32IA-NEXT: and a5, a5, a6 ; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: .LBB48_3: # in Loop: Header=BB48_1 Depth=1 -; RV32IA-NEXT: sc.w.rl a5, a5, (a6) +; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB48_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a4, a0 +; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umax_i8_acq_rel: @@ -4105,33 +4105,33 @@ define i8 @atomicrmw_umax_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s3, 8(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: lbu a3, 0(a0) -; RV64I-NEXT: mv s3, a1 -; RV64I-NEXT: andi s1, a1, 255 -; RV64I-NEXT: addi s2, sp, 7 +; RV64I-NEXT: mv s2, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: lbu a0, 0(a0) +; RV64I-NEXT: andi s0, a1, 255 +; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: j .LBB48_2 ; RV64I-NEXT: .LBB48_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB48_2 Depth=1 -; RV64I-NEXT: sb a3, 7(sp) +; RV64I-NEXT: sb a0, 7(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a4, zero, 2 -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: call __atomic_compare_exchange_1 -; RV64I-NEXT: lb a3, 7(sp) -; RV64I-NEXT: bnez a0, .LBB48_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lb a0, 7(sp) +; RV64I-NEXT: bnez a1, .LBB48_4 ; RV64I-NEXT: .LBB48_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: andi a0, a3, 255 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bltu s1, a0, .LBB48_1 +; RV64I-NEXT: andi a1, a0, 255 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bltu s0, a1, .LBB48_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB48_2 Depth=1 -; RV64I-NEXT: mv a2, s3 +; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB48_1 ; RV64I-NEXT: .LBB48_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -4142,27 +4142,27 @@ define i8 @atomicrmw_umax_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_umax_i8_acq_rel: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a3, a3, a0 +; RV64IA-NEXT: sllw a6, a3, a2 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aq a4, (a6) -; RV64IA-NEXT: and a2, a4, a3 +; RV64IA-NEXT: lr.w.aq a4, (a0) +; RV64IA-NEXT: and a3, a4, a6 ; RV64IA-NEXT: mv a5, a4 -; RV64IA-NEXT: bgeu a2, a1, .LBB48_3 +; RV64IA-NEXT: bgeu a3, a1, .LBB48_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB48_1 Depth=1 ; RV64IA-NEXT: xor a5, a4, a1 -; RV64IA-NEXT: and a5, a5, a3 +; RV64IA-NEXT: and a5, a5, a6 ; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: .LBB48_3: # in Loop: Header=BB48_1 Depth=1 -; RV64IA-NEXT: sc.w.rl a5, a5, (a6) +; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB48_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a4, a0 +; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: ret %1 = atomicrmw umax i8* %a, i8 %b acq_rel ret i8 %1 @@ -4177,33 +4177,33 @@ define i8 @atomicrmw_umax_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s3, 12(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lbu a3, 0(a0) -; RV32I-NEXT: mv s3, a1 -; RV32I-NEXT: andi s1, a1, 255 -; RV32I-NEXT: addi s2, sp, 11 +; RV32I-NEXT: mv s2, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lbu a0, 0(a0) +; RV32I-NEXT: andi s0, a1, 255 +; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: j .LBB49_2 ; RV32I-NEXT: .LBB49_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB49_2 Depth=1 -; RV32I-NEXT: sb a3, 11(sp) +; RV32I-NEXT: sb a0, 11(sp) +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a4, zero, 5 -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: call __atomic_compare_exchange_1 -; RV32I-NEXT: lb a3, 11(sp) -; RV32I-NEXT: bnez a0, .LBB49_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lb a0, 11(sp) +; RV32I-NEXT: bnez a1, .LBB49_4 ; RV32I-NEXT: .LBB49_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: andi a0, a3, 255 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bltu s1, a0, .LBB49_1 +; RV32I-NEXT: andi a1, a0, 255 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: bltu s0, a1, .LBB49_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB49_2 Depth=1 -; RV32I-NEXT: mv a2, s3 +; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB49_1 ; RV32I-NEXT: .LBB49_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -4214,27 +4214,27 @@ define i8 @atomicrmw_umax_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_umax_i8_seq_cst: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a3, a3, a0 +; RV32IA-NEXT: sll a6, a3, a2 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB49_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aqrl a4, (a6) -; RV32IA-NEXT: and a2, a4, a3 +; RV32IA-NEXT: lr.w.aqrl a4, (a0) +; RV32IA-NEXT: and a3, a4, a6 ; RV32IA-NEXT: mv a5, a4 -; RV32IA-NEXT: bgeu a2, a1, .LBB49_3 +; RV32IA-NEXT: bgeu a3, a1, .LBB49_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB49_1 Depth=1 ; RV32IA-NEXT: xor a5, a4, a1 -; RV32IA-NEXT: and a5, a5, a3 +; RV32IA-NEXT: and a5, a5, a6 ; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: .LBB49_3: # in Loop: Header=BB49_1 Depth=1 -; RV32IA-NEXT: sc.w.aqrl a5, a5, (a6) +; RV32IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB49_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a4, a0 +; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umax_i8_seq_cst: @@ -4245,33 +4245,33 @@ define i8 @atomicrmw_umax_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s3, 8(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: lbu a3, 0(a0) -; RV64I-NEXT: mv s3, a1 -; RV64I-NEXT: andi s1, a1, 255 -; RV64I-NEXT: addi s2, sp, 7 +; RV64I-NEXT: mv s2, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: lbu a0, 0(a0) +; RV64I-NEXT: andi s0, a1, 255 +; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: j .LBB49_2 ; RV64I-NEXT: .LBB49_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB49_2 Depth=1 -; RV64I-NEXT: sb a3, 7(sp) +; RV64I-NEXT: sb a0, 7(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a4, zero, 5 -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: call __atomic_compare_exchange_1 -; RV64I-NEXT: lb a3, 7(sp) -; RV64I-NEXT: bnez a0, .LBB49_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lb a0, 7(sp) +; RV64I-NEXT: bnez a1, .LBB49_4 ; RV64I-NEXT: .LBB49_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: andi a0, a3, 255 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bltu s1, a0, .LBB49_1 +; RV64I-NEXT: andi a1, a0, 255 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bltu s0, a1, .LBB49_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB49_2 Depth=1 -; RV64I-NEXT: mv a2, s3 +; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB49_1 ; RV64I-NEXT: .LBB49_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -4282,27 +4282,27 @@ define i8 @atomicrmw_umax_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_umax_i8_seq_cst: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a3, a3, a0 +; RV64IA-NEXT: sllw a6, a3, a2 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB49_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aqrl a4, (a6) -; RV64IA-NEXT: and a2, a4, a3 +; RV64IA-NEXT: lr.w.aqrl a4, (a0) +; RV64IA-NEXT: and a3, a4, a6 ; RV64IA-NEXT: mv a5, a4 -; RV64IA-NEXT: bgeu a2, a1, .LBB49_3 +; RV64IA-NEXT: bgeu a3, a1, .LBB49_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB49_1 Depth=1 ; RV64IA-NEXT: xor a5, a4, a1 -; RV64IA-NEXT: and a5, a5, a3 +; RV64IA-NEXT: and a5, a5, a6 ; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: .LBB49_3: # in Loop: Header=BB49_1 Depth=1 -; RV64IA-NEXT: sc.w.aqrl a5, a5, (a6) +; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB49_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a4, a0 +; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: ret %1 = atomicrmw umax i8* %a, i8 %b seq_cst ret i8 %1 @@ -4317,33 +4317,33 @@ define i8 @atomicrmw_umin_i8_monotonic(i8 *%a, i8 %b) nounwind { ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s3, 12(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lbu a3, 0(a0) -; RV32I-NEXT: mv s3, a1 -; RV32I-NEXT: andi s1, a1, 255 -; RV32I-NEXT: addi s2, sp, 11 +; RV32I-NEXT: mv s2, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lbu a0, 0(a0) +; RV32I-NEXT: andi s0, a1, 255 +; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: j .LBB50_2 ; RV32I-NEXT: .LBB50_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB50_2 Depth=1 -; RV32I-NEXT: sb a3, 11(sp) -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: mv a1, s2 +; RV32I-NEXT: sb a0, 11(sp) +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: call __atomic_compare_exchange_1 -; RV32I-NEXT: lb a3, 11(sp) -; RV32I-NEXT: bnez a0, .LBB50_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lb a0, 11(sp) +; RV32I-NEXT: bnez a1, .LBB50_4 ; RV32I-NEXT: .LBB50_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: andi a0, a3, 255 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s1, a0, .LBB50_1 +; RV32I-NEXT: andi a1, a0, 255 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: bgeu s0, a1, .LBB50_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB50_2 Depth=1 -; RV32I-NEXT: mv a2, s3 +; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB50_1 ; RV32I-NEXT: .LBB50_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -4354,27 +4354,27 @@ define i8 @atomicrmw_umin_i8_monotonic(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_umin_i8_monotonic: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a3, a3, a0 +; RV32IA-NEXT: sll a6, a3, a2 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB50_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a4, (a6) -; RV32IA-NEXT: and a2, a4, a3 +; RV32IA-NEXT: lr.w a4, (a0) +; RV32IA-NEXT: and a3, a4, a6 ; RV32IA-NEXT: mv a5, a4 -; RV32IA-NEXT: bgeu a1, a2, .LBB50_3 +; RV32IA-NEXT: bgeu a1, a3, .LBB50_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB50_1 Depth=1 ; RV32IA-NEXT: xor a5, a4, a1 -; RV32IA-NEXT: and a5, a5, a3 +; RV32IA-NEXT: and a5, a5, a6 ; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: .LBB50_3: # in Loop: Header=BB50_1 Depth=1 -; RV32IA-NEXT: sc.w a5, a5, (a6) +; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB50_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a4, a0 +; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umin_i8_monotonic: @@ -4385,33 +4385,33 @@ define i8 @atomicrmw_umin_i8_monotonic(i8 *%a, i8 %b) nounwind { ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s3, 8(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: lbu a3, 0(a0) -; RV64I-NEXT: mv s3, a1 -; RV64I-NEXT: andi s1, a1, 255 -; RV64I-NEXT: addi s2, sp, 7 +; RV64I-NEXT: mv s2, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: lbu a0, 0(a0) +; RV64I-NEXT: andi s0, a1, 255 +; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: j .LBB50_2 ; RV64I-NEXT: .LBB50_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB50_2 Depth=1 -; RV64I-NEXT: sb a3, 7(sp) -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 +; RV64I-NEXT: sb a0, 7(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: call __atomic_compare_exchange_1 -; RV64I-NEXT: lb a3, 7(sp) -; RV64I-NEXT: bnez a0, .LBB50_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lb a0, 7(sp) +; RV64I-NEXT: bnez a1, .LBB50_4 ; RV64I-NEXT: .LBB50_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: andi a0, a3, 255 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s1, a0, .LBB50_1 +; RV64I-NEXT: andi a1, a0, 255 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bgeu s0, a1, .LBB50_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB50_2 Depth=1 -; RV64I-NEXT: mv a2, s3 +; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB50_1 ; RV64I-NEXT: .LBB50_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -4422,27 +4422,27 @@ define i8 @atomicrmw_umin_i8_monotonic(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_umin_i8_monotonic: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a3, a3, a0 +; RV64IA-NEXT: sllw a6, a3, a2 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB50_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w a4, (a6) -; RV64IA-NEXT: and a2, a4, a3 +; RV64IA-NEXT: lr.w a4, (a0) +; RV64IA-NEXT: and a3, a4, a6 ; RV64IA-NEXT: mv a5, a4 -; RV64IA-NEXT: bgeu a1, a2, .LBB50_3 +; RV64IA-NEXT: bgeu a1, a3, .LBB50_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB50_1 Depth=1 ; RV64IA-NEXT: xor a5, a4, a1 -; RV64IA-NEXT: and a5, a5, a3 +; RV64IA-NEXT: and a5, a5, a6 ; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: .LBB50_3: # in Loop: Header=BB50_1 Depth=1 -; RV64IA-NEXT: sc.w a5, a5, (a6) +; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB50_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a4, a0 +; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: ret %1 = atomicrmw umin i8* %a, i8 %b monotonic ret i8 %1 @@ -4457,33 +4457,33 @@ define i8 @atomicrmw_umin_i8_acquire(i8 *%a, i8 %b) nounwind { ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s3, 12(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lbu a3, 0(a0) -; RV32I-NEXT: mv s3, a1 -; RV32I-NEXT: andi s1, a1, 255 -; RV32I-NEXT: addi s2, sp, 11 +; RV32I-NEXT: mv s2, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lbu a0, 0(a0) +; RV32I-NEXT: andi s0, a1, 255 +; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: j .LBB51_2 ; RV32I-NEXT: .LBB51_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB51_2 Depth=1 -; RV32I-NEXT: sb a3, 11(sp) +; RV32I-NEXT: sb a0, 11(sp) +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a4, zero, 2 -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: call __atomic_compare_exchange_1 -; RV32I-NEXT: lb a3, 11(sp) -; RV32I-NEXT: bnez a0, .LBB51_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lb a0, 11(sp) +; RV32I-NEXT: bnez a1, .LBB51_4 ; RV32I-NEXT: .LBB51_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: andi a0, a3, 255 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s1, a0, .LBB51_1 +; RV32I-NEXT: andi a1, a0, 255 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: bgeu s0, a1, .LBB51_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB51_2 Depth=1 -; RV32I-NEXT: mv a2, s3 +; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB51_1 ; RV32I-NEXT: .LBB51_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -4494,27 +4494,27 @@ define i8 @atomicrmw_umin_i8_acquire(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_umin_i8_acquire: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a3, a3, a0 +; RV32IA-NEXT: sll a6, a3, a2 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aq a4, (a6) -; RV32IA-NEXT: and a2, a4, a3 +; RV32IA-NEXT: lr.w.aq a4, (a0) +; RV32IA-NEXT: and a3, a4, a6 ; RV32IA-NEXT: mv a5, a4 -; RV32IA-NEXT: bgeu a1, a2, .LBB51_3 +; RV32IA-NEXT: bgeu a1, a3, .LBB51_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB51_1 Depth=1 ; RV32IA-NEXT: xor a5, a4, a1 -; RV32IA-NEXT: and a5, a5, a3 +; RV32IA-NEXT: and a5, a5, a6 ; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: .LBB51_3: # in Loop: Header=BB51_1 Depth=1 -; RV32IA-NEXT: sc.w a5, a5, (a6) +; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB51_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a4, a0 +; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umin_i8_acquire: @@ -4525,33 +4525,33 @@ define i8 @atomicrmw_umin_i8_acquire(i8 *%a, i8 %b) nounwind { ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s3, 8(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: lbu a3, 0(a0) -; RV64I-NEXT: mv s3, a1 -; RV64I-NEXT: andi s1, a1, 255 -; RV64I-NEXT: addi s2, sp, 7 +; RV64I-NEXT: mv s2, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: lbu a0, 0(a0) +; RV64I-NEXT: andi s0, a1, 255 +; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: j .LBB51_2 ; RV64I-NEXT: .LBB51_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB51_2 Depth=1 -; RV64I-NEXT: sb a3, 7(sp) +; RV64I-NEXT: sb a0, 7(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a4, zero, 2 -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: call __atomic_compare_exchange_1 -; RV64I-NEXT: lb a3, 7(sp) -; RV64I-NEXT: bnez a0, .LBB51_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lb a0, 7(sp) +; RV64I-NEXT: bnez a1, .LBB51_4 ; RV64I-NEXT: .LBB51_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: andi a0, a3, 255 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s1, a0, .LBB51_1 +; RV64I-NEXT: andi a1, a0, 255 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bgeu s0, a1, .LBB51_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB51_2 Depth=1 -; RV64I-NEXT: mv a2, s3 +; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB51_1 ; RV64I-NEXT: .LBB51_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -4562,27 +4562,27 @@ define i8 @atomicrmw_umin_i8_acquire(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_umin_i8_acquire: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a3, a3, a0 +; RV64IA-NEXT: sllw a6, a3, a2 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aq a4, (a6) -; RV64IA-NEXT: and a2, a4, a3 +; RV64IA-NEXT: lr.w.aq a4, (a0) +; RV64IA-NEXT: and a3, a4, a6 ; RV64IA-NEXT: mv a5, a4 -; RV64IA-NEXT: bgeu a1, a2, .LBB51_3 +; RV64IA-NEXT: bgeu a1, a3, .LBB51_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB51_1 Depth=1 ; RV64IA-NEXT: xor a5, a4, a1 -; RV64IA-NEXT: and a5, a5, a3 +; RV64IA-NEXT: and a5, a5, a6 ; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: .LBB51_3: # in Loop: Header=BB51_1 Depth=1 -; RV64IA-NEXT: sc.w a5, a5, (a6) +; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB51_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a4, a0 +; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: ret %1 = atomicrmw umin i8* %a, i8 %b acquire ret i8 %1 @@ -4597,33 +4597,33 @@ define i8 @atomicrmw_umin_i8_release(i8 *%a, i8 %b) nounwind { ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s3, 12(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lbu a3, 0(a0) -; RV32I-NEXT: mv s3, a1 -; RV32I-NEXT: andi s1, a1, 255 -; RV32I-NEXT: addi s2, sp, 11 +; RV32I-NEXT: mv s2, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lbu a0, 0(a0) +; RV32I-NEXT: andi s0, a1, 255 +; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: j .LBB52_2 ; RV32I-NEXT: .LBB52_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB52_2 Depth=1 -; RV32I-NEXT: sb a3, 11(sp) +; RV32I-NEXT: sb a0, 11(sp) +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: addi a3, zero, 3 -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: call __atomic_compare_exchange_1 -; RV32I-NEXT: lb a3, 11(sp) -; RV32I-NEXT: bnez a0, .LBB52_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lb a0, 11(sp) +; RV32I-NEXT: bnez a1, .LBB52_4 ; RV32I-NEXT: .LBB52_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: andi a0, a3, 255 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s1, a0, .LBB52_1 +; RV32I-NEXT: andi a1, a0, 255 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: bgeu s0, a1, .LBB52_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB52_2 Depth=1 -; RV32I-NEXT: mv a2, s3 +; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB52_1 ; RV32I-NEXT: .LBB52_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -4634,27 +4634,27 @@ define i8 @atomicrmw_umin_i8_release(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_umin_i8_release: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a3, a3, a0 +; RV32IA-NEXT: sll a6, a3, a2 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a4, (a6) -; RV32IA-NEXT: and a2, a4, a3 +; RV32IA-NEXT: lr.w a4, (a0) +; RV32IA-NEXT: and a3, a4, a6 ; RV32IA-NEXT: mv a5, a4 -; RV32IA-NEXT: bgeu a1, a2, .LBB52_3 +; RV32IA-NEXT: bgeu a1, a3, .LBB52_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB52_1 Depth=1 ; RV32IA-NEXT: xor a5, a4, a1 -; RV32IA-NEXT: and a5, a5, a3 +; RV32IA-NEXT: and a5, a5, a6 ; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: .LBB52_3: # in Loop: Header=BB52_1 Depth=1 -; RV32IA-NEXT: sc.w.rl a5, a5, (a6) +; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB52_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a4, a0 +; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umin_i8_release: @@ -4665,33 +4665,33 @@ define i8 @atomicrmw_umin_i8_release(i8 *%a, i8 %b) nounwind { ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s3, 8(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: lbu a3, 0(a0) -; RV64I-NEXT: mv s3, a1 -; RV64I-NEXT: andi s1, a1, 255 -; RV64I-NEXT: addi s2, sp, 7 +; RV64I-NEXT: mv s2, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: lbu a0, 0(a0) +; RV64I-NEXT: andi s0, a1, 255 +; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: j .LBB52_2 ; RV64I-NEXT: .LBB52_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB52_2 Depth=1 -; RV64I-NEXT: sb a3, 7(sp) +; RV64I-NEXT: sb a0, 7(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: addi a3, zero, 3 -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: call __atomic_compare_exchange_1 -; RV64I-NEXT: lb a3, 7(sp) -; RV64I-NEXT: bnez a0, .LBB52_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lb a0, 7(sp) +; RV64I-NEXT: bnez a1, .LBB52_4 ; RV64I-NEXT: .LBB52_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: andi a0, a3, 255 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s1, a0, .LBB52_1 +; RV64I-NEXT: andi a1, a0, 255 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bgeu s0, a1, .LBB52_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB52_2 Depth=1 -; RV64I-NEXT: mv a2, s3 +; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB52_1 ; RV64I-NEXT: .LBB52_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -4702,27 +4702,27 @@ define i8 @atomicrmw_umin_i8_release(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_umin_i8_release: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a3, a3, a0 +; RV64IA-NEXT: sllw a6, a3, a2 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w a4, (a6) -; RV64IA-NEXT: and a2, a4, a3 +; RV64IA-NEXT: lr.w a4, (a0) +; RV64IA-NEXT: and a3, a4, a6 ; RV64IA-NEXT: mv a5, a4 -; RV64IA-NEXT: bgeu a1, a2, .LBB52_3 +; RV64IA-NEXT: bgeu a1, a3, .LBB52_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB52_1 Depth=1 ; RV64IA-NEXT: xor a5, a4, a1 -; RV64IA-NEXT: and a5, a5, a3 +; RV64IA-NEXT: and a5, a5, a6 ; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: .LBB52_3: # in Loop: Header=BB52_1 Depth=1 -; RV64IA-NEXT: sc.w.rl a5, a5, (a6) +; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB52_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a4, a0 +; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: ret %1 = atomicrmw umin i8* %a, i8 %b release ret i8 %1 @@ -4737,33 +4737,33 @@ define i8 @atomicrmw_umin_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s3, 12(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lbu a3, 0(a0) -; RV32I-NEXT: mv s3, a1 -; RV32I-NEXT: andi s1, a1, 255 -; RV32I-NEXT: addi s2, sp, 11 +; RV32I-NEXT: mv s2, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lbu a0, 0(a0) +; RV32I-NEXT: andi s0, a1, 255 +; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: j .LBB53_2 ; RV32I-NEXT: .LBB53_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB53_2 Depth=1 -; RV32I-NEXT: sb a3, 11(sp) +; RV32I-NEXT: sb a0, 11(sp) +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a4, zero, 2 -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: call __atomic_compare_exchange_1 -; RV32I-NEXT: lb a3, 11(sp) -; RV32I-NEXT: bnez a0, .LBB53_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lb a0, 11(sp) +; RV32I-NEXT: bnez a1, .LBB53_4 ; RV32I-NEXT: .LBB53_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: andi a0, a3, 255 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s1, a0, .LBB53_1 +; RV32I-NEXT: andi a1, a0, 255 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: bgeu s0, a1, .LBB53_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB53_2 Depth=1 -; RV32I-NEXT: mv a2, s3 +; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB53_1 ; RV32I-NEXT: .LBB53_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -4774,27 +4774,27 @@ define i8 @atomicrmw_umin_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_umin_i8_acq_rel: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a3, a3, a0 +; RV32IA-NEXT: sll a6, a3, a2 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aq a4, (a6) -; RV32IA-NEXT: and a2, a4, a3 +; RV32IA-NEXT: lr.w.aq a4, (a0) +; RV32IA-NEXT: and a3, a4, a6 ; RV32IA-NEXT: mv a5, a4 -; RV32IA-NEXT: bgeu a1, a2, .LBB53_3 +; RV32IA-NEXT: bgeu a1, a3, .LBB53_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB53_1 Depth=1 ; RV32IA-NEXT: xor a5, a4, a1 -; RV32IA-NEXT: and a5, a5, a3 +; RV32IA-NEXT: and a5, a5, a6 ; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: .LBB53_3: # in Loop: Header=BB53_1 Depth=1 -; RV32IA-NEXT: sc.w.rl a5, a5, (a6) +; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB53_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a4, a0 +; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umin_i8_acq_rel: @@ -4805,33 +4805,33 @@ define i8 @atomicrmw_umin_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s3, 8(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: lbu a3, 0(a0) -; RV64I-NEXT: mv s3, a1 -; RV64I-NEXT: andi s1, a1, 255 -; RV64I-NEXT: addi s2, sp, 7 +; RV64I-NEXT: mv s2, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: lbu a0, 0(a0) +; RV64I-NEXT: andi s0, a1, 255 +; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: j .LBB53_2 ; RV64I-NEXT: .LBB53_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB53_2 Depth=1 -; RV64I-NEXT: sb a3, 7(sp) +; RV64I-NEXT: sb a0, 7(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a4, zero, 2 -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: call __atomic_compare_exchange_1 -; RV64I-NEXT: lb a3, 7(sp) -; RV64I-NEXT: bnez a0, .LBB53_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lb a0, 7(sp) +; RV64I-NEXT: bnez a1, .LBB53_4 ; RV64I-NEXT: .LBB53_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: andi a0, a3, 255 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s1, a0, .LBB53_1 +; RV64I-NEXT: andi a1, a0, 255 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bgeu s0, a1, .LBB53_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB53_2 Depth=1 -; RV64I-NEXT: mv a2, s3 +; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB53_1 ; RV64I-NEXT: .LBB53_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -4842,27 +4842,27 @@ define i8 @atomicrmw_umin_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_umin_i8_acq_rel: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a3, a3, a0 +; RV64IA-NEXT: sllw a6, a3, a2 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aq a4, (a6) -; RV64IA-NEXT: and a2, a4, a3 +; RV64IA-NEXT: lr.w.aq a4, (a0) +; RV64IA-NEXT: and a3, a4, a6 ; RV64IA-NEXT: mv a5, a4 -; RV64IA-NEXT: bgeu a1, a2, .LBB53_3 +; RV64IA-NEXT: bgeu a1, a3, .LBB53_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB53_1 Depth=1 ; RV64IA-NEXT: xor a5, a4, a1 -; RV64IA-NEXT: and a5, a5, a3 +; RV64IA-NEXT: and a5, a5, a6 ; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: .LBB53_3: # in Loop: Header=BB53_1 Depth=1 -; RV64IA-NEXT: sc.w.rl a5, a5, (a6) +; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB53_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a4, a0 +; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: ret %1 = atomicrmw umin i8* %a, i8 %b acq_rel ret i8 %1 @@ -4877,33 +4877,33 @@ define i8 @atomicrmw_umin_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s3, 12(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lbu a3, 0(a0) -; RV32I-NEXT: mv s3, a1 -; RV32I-NEXT: andi s1, a1, 255 -; RV32I-NEXT: addi s2, sp, 11 +; RV32I-NEXT: mv s2, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lbu a0, 0(a0) +; RV32I-NEXT: andi s0, a1, 255 +; RV32I-NEXT: addi s3, sp, 11 ; RV32I-NEXT: j .LBB54_2 ; RV32I-NEXT: .LBB54_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB54_2 Depth=1 -; RV32I-NEXT: sb a3, 11(sp) +; RV32I-NEXT: sb a0, 11(sp) +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a4, zero, 5 -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: call __atomic_compare_exchange_1 -; RV32I-NEXT: lb a3, 11(sp) -; RV32I-NEXT: bnez a0, .LBB54_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lb a0, 11(sp) +; RV32I-NEXT: bnez a1, .LBB54_4 ; RV32I-NEXT: .LBB54_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: andi a0, a3, 255 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s1, a0, .LBB54_1 +; RV32I-NEXT: andi a1, a0, 255 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: bgeu s0, a1, .LBB54_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB54_2 Depth=1 -; RV32I-NEXT: mv a2, s3 +; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB54_1 ; RV32I-NEXT: .LBB54_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -4914,27 +4914,27 @@ define i8 @atomicrmw_umin_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_umin_i8_seq_cst: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 ; RV32IA-NEXT: addi a3, zero, 255 -; RV32IA-NEXT: sll a3, a3, a0 +; RV32IA-NEXT: sll a6, a3, a2 ; RV32IA-NEXT: andi a1, a1, 255 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB54_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aqrl a4, (a6) -; RV32IA-NEXT: and a2, a4, a3 +; RV32IA-NEXT: lr.w.aqrl a4, (a0) +; RV32IA-NEXT: and a3, a4, a6 ; RV32IA-NEXT: mv a5, a4 -; RV32IA-NEXT: bgeu a1, a2, .LBB54_3 +; RV32IA-NEXT: bgeu a1, a3, .LBB54_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB54_1 Depth=1 ; RV32IA-NEXT: xor a5, a4, a1 -; RV32IA-NEXT: and a5, a5, a3 +; RV32IA-NEXT: and a5, a5, a6 ; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: .LBB54_3: # in Loop: Header=BB54_1 Depth=1 -; RV32IA-NEXT: sc.w.aqrl a5, a5, (a6) +; RV32IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB54_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a4, a0 +; RV32IA-NEXT: srl a0, a4, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umin_i8_seq_cst: @@ -4945,33 +4945,33 @@ define i8 @atomicrmw_umin_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s3, 8(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: lbu a3, 0(a0) -; RV64I-NEXT: mv s3, a1 -; RV64I-NEXT: andi s1, a1, 255 -; RV64I-NEXT: addi s2, sp, 7 +; RV64I-NEXT: mv s2, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: lbu a0, 0(a0) +; RV64I-NEXT: andi s0, a1, 255 +; RV64I-NEXT: addi s3, sp, 7 ; RV64I-NEXT: j .LBB54_2 ; RV64I-NEXT: .LBB54_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB54_2 Depth=1 -; RV64I-NEXT: sb a3, 7(sp) +; RV64I-NEXT: sb a0, 7(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a4, zero, 5 -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: call __atomic_compare_exchange_1 -; RV64I-NEXT: lb a3, 7(sp) -; RV64I-NEXT: bnez a0, .LBB54_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lb a0, 7(sp) +; RV64I-NEXT: bnez a1, .LBB54_4 ; RV64I-NEXT: .LBB54_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: andi a0, a3, 255 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s1, a0, .LBB54_1 +; RV64I-NEXT: andi a1, a0, 255 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bgeu s0, a1, .LBB54_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB54_2 Depth=1 -; RV64I-NEXT: mv a2, s3 +; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB54_1 ; RV64I-NEXT: .LBB54_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -4982,27 +4982,27 @@ define i8 @atomicrmw_umin_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_umin_i8_seq_cst: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 ; RV64IA-NEXT: addi a3, zero, 255 -; RV64IA-NEXT: sllw a3, a3, a0 +; RV64IA-NEXT: sllw a6, a3, a2 ; RV64IA-NEXT: andi a1, a1, 255 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB54_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aqrl a4, (a6) -; RV64IA-NEXT: and a2, a4, a3 +; RV64IA-NEXT: lr.w.aqrl a4, (a0) +; RV64IA-NEXT: and a3, a4, a6 ; RV64IA-NEXT: mv a5, a4 -; RV64IA-NEXT: bgeu a1, a2, .LBB54_3 +; RV64IA-NEXT: bgeu a1, a3, .LBB54_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB54_1 Depth=1 ; RV64IA-NEXT: xor a5, a4, a1 -; RV64IA-NEXT: and a5, a5, a3 +; RV64IA-NEXT: and a5, a5, a6 ; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: .LBB54_3: # in Loop: Header=BB54_1 Depth=1 -; RV64IA-NEXT: sc.w.aqrl a5, a5, (a6) +; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB54_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a4, a0 +; RV64IA-NEXT: srlw a0, a4, a2 ; RV64IA-NEXT: ret %1 = atomicrmw umin i8* %a, i8 %b seq_cst ret i8 %1 @@ -5021,24 +5021,24 @@ define i16 @atomicrmw_xchg_i16_monotonic(i16* %a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_xchg_i16_monotonic: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a3, a0, 3 +; RV32IA-NEXT: andi a3, a3, 24 +; RV32IA-NEXT: sll a2, a2, a3 +; RV32IA-NEXT: sll a1, a1, a3 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB55_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a3, (a2) +; RV32IA-NEXT: lr.w a4, (a0) ; RV32IA-NEXT: add a5, zero, a1 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: sc.w a5, a5, (a2) +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: and a5, a5, a2 +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB55_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a3, a0 +; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_i16_monotonic: @@ -5053,24 +5053,24 @@ define i16 @atomicrmw_xchg_i16_monotonic(i16* %a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_xchg_i16_monotonic: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a4, a3, a0 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a3, a0, 3 +; RV64IA-NEXT: andi a3, a3, 24 +; RV64IA-NEXT: sllw a2, a2, a3 +; RV64IA-NEXT: sllw a1, a1, a3 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB55_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w a3, (a2) +; RV64IA-NEXT: lr.w a4, (a0) ; RV64IA-NEXT: add a5, zero, a1 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: and a5, a5, a4 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: sc.w a5, a5, (a2) +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: and a5, a5, a2 +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB55_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a3, a0 +; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: ret %1 = atomicrmw xchg i16* %a, i16 %b monotonic ret i16 %1 @@ -5089,24 +5089,24 @@ define i16 @atomicrmw_xchg_i16_acquire(i16* %a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_xchg_i16_acquire: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a3, a0, 3 +; RV32IA-NEXT: andi a3, a3, 24 +; RV32IA-NEXT: sll a2, a2, a3 +; RV32IA-NEXT: sll a1, a1, a3 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB56_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aq a3, (a2) +; RV32IA-NEXT: lr.w.aq a4, (a0) ; RV32IA-NEXT: add a5, zero, a1 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: sc.w a5, a5, (a2) +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: and a5, a5, a2 +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB56_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a3, a0 +; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_i16_acquire: @@ -5121,24 +5121,24 @@ define i16 @atomicrmw_xchg_i16_acquire(i16* %a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_xchg_i16_acquire: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a4, a3, a0 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a3, a0, 3 +; RV64IA-NEXT: andi a3, a3, 24 +; RV64IA-NEXT: sllw a2, a2, a3 +; RV64IA-NEXT: sllw a1, a1, a3 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB56_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aq a3, (a2) +; RV64IA-NEXT: lr.w.aq a4, (a0) ; RV64IA-NEXT: add a5, zero, a1 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: and a5, a5, a4 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: sc.w a5, a5, (a2) +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: and a5, a5, a2 +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB56_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a3, a0 +; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: ret %1 = atomicrmw xchg i16* %a, i16 %b acquire ret i16 %1 @@ -5157,24 +5157,24 @@ define i16 @atomicrmw_xchg_i16_release(i16* %a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_xchg_i16_release: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a3, a0, 3 +; RV32IA-NEXT: andi a3, a3, 24 +; RV32IA-NEXT: sll a2, a2, a3 +; RV32IA-NEXT: sll a1, a1, a3 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB57_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a3, (a2) +; RV32IA-NEXT: lr.w a4, (a0) ; RV32IA-NEXT: add a5, zero, a1 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: and a5, a5, a2 +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB57_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a3, a0 +; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_i16_release: @@ -5189,24 +5189,24 @@ define i16 @atomicrmw_xchg_i16_release(i16* %a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_xchg_i16_release: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a4, a3, a0 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a3, a0, 3 +; RV64IA-NEXT: andi a3, a3, 24 +; RV64IA-NEXT: sllw a2, a2, a3 +; RV64IA-NEXT: sllw a1, a1, a3 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB57_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w a3, (a2) +; RV64IA-NEXT: lr.w a4, (a0) ; RV64IA-NEXT: add a5, zero, a1 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: and a5, a5, a4 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: sc.w.rl a5, a5, (a2) +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: and a5, a5, a2 +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB57_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a3, a0 +; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: ret %1 = atomicrmw xchg i16* %a, i16 %b release ret i16 %1 @@ -5225,24 +5225,24 @@ define i16 @atomicrmw_xchg_i16_acq_rel(i16* %a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_xchg_i16_acq_rel: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a3, a0, 3 +; RV32IA-NEXT: andi a3, a3, 24 +; RV32IA-NEXT: sll a2, a2, a3 +; RV32IA-NEXT: sll a1, a1, a3 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB58_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aq a3, (a2) +; RV32IA-NEXT: lr.w.aq a4, (a0) ; RV32IA-NEXT: add a5, zero, a1 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: and a5, a5, a2 +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB58_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a3, a0 +; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_i16_acq_rel: @@ -5257,24 +5257,24 @@ define i16 @atomicrmw_xchg_i16_acq_rel(i16* %a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_xchg_i16_acq_rel: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a4, a3, a0 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a3, a0, 3 +; RV64IA-NEXT: andi a3, a3, 24 +; RV64IA-NEXT: sllw a2, a2, a3 +; RV64IA-NEXT: sllw a1, a1, a3 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB58_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aq a3, (a2) +; RV64IA-NEXT: lr.w.aq a4, (a0) ; RV64IA-NEXT: add a5, zero, a1 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: and a5, a5, a4 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: sc.w.rl a5, a5, (a2) +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: and a5, a5, a2 +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB58_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a3, a0 +; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: ret %1 = atomicrmw xchg i16* %a, i16 %b acq_rel ret i16 %1 @@ -5293,24 +5293,24 @@ define i16 @atomicrmw_xchg_i16_seq_cst(i16* %a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_xchg_i16_seq_cst: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a3, a0, 3 +; RV32IA-NEXT: andi a3, a3, 24 +; RV32IA-NEXT: sll a2, a2, a3 +; RV32IA-NEXT: sll a1, a1, a3 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB59_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aqrl a3, (a2) +; RV32IA-NEXT: lr.w.aqrl a4, (a0) ; RV32IA-NEXT: add a5, zero, a1 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: sc.w.aqrl a5, a5, (a2) +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: and a5, a5, a2 +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB59_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a3, a0 +; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_i16_seq_cst: @@ -5325,24 +5325,24 @@ define i16 @atomicrmw_xchg_i16_seq_cst(i16* %a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_xchg_i16_seq_cst: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a4, a3, a0 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a3, a0, 3 +; RV64IA-NEXT: andi a3, a3, 24 +; RV64IA-NEXT: sllw a2, a2, a3 +; RV64IA-NEXT: sllw a1, a1, a3 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB59_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aqrl a3, (a2) +; RV64IA-NEXT: lr.w.aqrl a4, (a0) ; RV64IA-NEXT: add a5, zero, a1 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: and a5, a5, a4 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: sc.w.aqrl a5, a5, (a2) +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: and a5, a5, a2 +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB59_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a3, a0 +; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: ret %1 = atomicrmw xchg i16* %a, i16 %b seq_cst ret i16 %1 @@ -5361,24 +5361,24 @@ define i16 @atomicrmw_add_i16_monotonic(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_add_i16_monotonic: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a3, a0, 3 +; RV32IA-NEXT: andi a3, a3, 24 +; RV32IA-NEXT: sll a2, a2, a3 +; RV32IA-NEXT: sll a1, a1, a3 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB60_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a3, (a2) -; RV32IA-NEXT: add a5, a3, a1 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: sc.w a5, a5, (a2) +; RV32IA-NEXT: lr.w a4, (a0) +; RV32IA-NEXT: add a5, a4, a1 +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: and a5, a5, a2 +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB60_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a3, a0 +; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_add_i16_monotonic: @@ -5393,24 +5393,24 @@ define i16 @atomicrmw_add_i16_monotonic(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_add_i16_monotonic: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a4, a3, a0 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a3, a0, 3 +; RV64IA-NEXT: andi a3, a3, 24 +; RV64IA-NEXT: sllw a2, a2, a3 +; RV64IA-NEXT: sllw a1, a1, a3 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB60_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w a3, (a2) -; RV64IA-NEXT: add a5, a3, a1 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: and a5, a5, a4 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: sc.w a5, a5, (a2) +; RV64IA-NEXT: lr.w a4, (a0) +; RV64IA-NEXT: add a5, a4, a1 +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: and a5, a5, a2 +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB60_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a3, a0 +; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: ret %1 = atomicrmw add i16* %a, i16 %b monotonic ret i16 %1 @@ -5429,24 +5429,24 @@ define i16 @atomicrmw_add_i16_acquire(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_add_i16_acquire: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a3, a0, 3 +; RV32IA-NEXT: andi a3, a3, 24 +; RV32IA-NEXT: sll a2, a2, a3 +; RV32IA-NEXT: sll a1, a1, a3 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB61_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aq a3, (a2) -; RV32IA-NEXT: add a5, a3, a1 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: sc.w a5, a5, (a2) +; RV32IA-NEXT: lr.w.aq a4, (a0) +; RV32IA-NEXT: add a5, a4, a1 +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: and a5, a5, a2 +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB61_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a3, a0 +; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_add_i16_acquire: @@ -5461,24 +5461,24 @@ define i16 @atomicrmw_add_i16_acquire(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_add_i16_acquire: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a4, a3, a0 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a3, a0, 3 +; RV64IA-NEXT: andi a3, a3, 24 +; RV64IA-NEXT: sllw a2, a2, a3 +; RV64IA-NEXT: sllw a1, a1, a3 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB61_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aq a3, (a2) -; RV64IA-NEXT: add a5, a3, a1 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: and a5, a5, a4 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: sc.w a5, a5, (a2) +; RV64IA-NEXT: lr.w.aq a4, (a0) +; RV64IA-NEXT: add a5, a4, a1 +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: and a5, a5, a2 +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB61_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a3, a0 +; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: ret %1 = atomicrmw add i16* %a, i16 %b acquire ret i16 %1 @@ -5497,24 +5497,24 @@ define i16 @atomicrmw_add_i16_release(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_add_i16_release: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a3, a0, 3 +; RV32IA-NEXT: andi a3, a3, 24 +; RV32IA-NEXT: sll a2, a2, a3 +; RV32IA-NEXT: sll a1, a1, a3 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB62_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a3, (a2) -; RV32IA-NEXT: add a5, a3, a1 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-NEXT: lr.w a4, (a0) +; RV32IA-NEXT: add a5, a4, a1 +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: and a5, a5, a2 +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB62_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a3, a0 +; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_add_i16_release: @@ -5529,24 +5529,24 @@ define i16 @atomicrmw_add_i16_release(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_add_i16_release: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a4, a3, a0 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a3, a0, 3 +; RV64IA-NEXT: andi a3, a3, 24 +; RV64IA-NEXT: sllw a2, a2, a3 +; RV64IA-NEXT: sllw a1, a1, a3 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB62_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w a3, (a2) -; RV64IA-NEXT: add a5, a3, a1 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: and a5, a5, a4 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: sc.w.rl a5, a5, (a2) +; RV64IA-NEXT: lr.w a4, (a0) +; RV64IA-NEXT: add a5, a4, a1 +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: and a5, a5, a2 +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB62_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a3, a0 +; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: ret %1 = atomicrmw add i16* %a, i16 %b release ret i16 %1 @@ -5565,24 +5565,24 @@ define i16 @atomicrmw_add_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_add_i16_acq_rel: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a3, a0, 3 +; RV32IA-NEXT: andi a3, a3, 24 +; RV32IA-NEXT: sll a2, a2, a3 +; RV32IA-NEXT: sll a1, a1, a3 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB63_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aq a3, (a2) -; RV32IA-NEXT: add a5, a3, a1 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-NEXT: lr.w.aq a4, (a0) +; RV32IA-NEXT: add a5, a4, a1 +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: and a5, a5, a2 +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB63_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a3, a0 +; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_add_i16_acq_rel: @@ -5597,24 +5597,24 @@ define i16 @atomicrmw_add_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_add_i16_acq_rel: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a4, a3, a0 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a3, a0, 3 +; RV64IA-NEXT: andi a3, a3, 24 +; RV64IA-NEXT: sllw a2, a2, a3 +; RV64IA-NEXT: sllw a1, a1, a3 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB63_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aq a3, (a2) -; RV64IA-NEXT: add a5, a3, a1 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: and a5, a5, a4 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: sc.w.rl a5, a5, (a2) +; RV64IA-NEXT: lr.w.aq a4, (a0) +; RV64IA-NEXT: add a5, a4, a1 +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: and a5, a5, a2 +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB63_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a3, a0 +; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: ret %1 = atomicrmw add i16* %a, i16 %b acq_rel ret i16 %1 @@ -5633,24 +5633,24 @@ define i16 @atomicrmw_add_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_add_i16_seq_cst: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a3, a0, 3 +; RV32IA-NEXT: andi a3, a3, 24 +; RV32IA-NEXT: sll a2, a2, a3 +; RV32IA-NEXT: sll a1, a1, a3 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB64_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aqrl a3, (a2) -; RV32IA-NEXT: add a5, a3, a1 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: sc.w.aqrl a5, a5, (a2) +; RV32IA-NEXT: lr.w.aqrl a4, (a0) +; RV32IA-NEXT: add a5, a4, a1 +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: and a5, a5, a2 +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB64_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a3, a0 +; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_add_i16_seq_cst: @@ -5665,24 +5665,24 @@ define i16 @atomicrmw_add_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_add_i16_seq_cst: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a4, a3, a0 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a3, a0, 3 +; RV64IA-NEXT: andi a3, a3, 24 +; RV64IA-NEXT: sllw a2, a2, a3 +; RV64IA-NEXT: sllw a1, a1, a3 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB64_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aqrl a3, (a2) -; RV64IA-NEXT: add a5, a3, a1 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: and a5, a5, a4 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: sc.w.aqrl a5, a5, (a2) +; RV64IA-NEXT: lr.w.aqrl a4, (a0) +; RV64IA-NEXT: add a5, a4, a1 +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: and a5, a5, a2 +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB64_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a3, a0 +; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: ret %1 = atomicrmw add i16* %a, i16 %b seq_cst ret i16 %1 @@ -5701,24 +5701,24 @@ define i16 @atomicrmw_sub_i16_monotonic(i16* %a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_sub_i16_monotonic: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a3, a0, 3 +; RV32IA-NEXT: andi a3, a3, 24 +; RV32IA-NEXT: sll a2, a2, a3 +; RV32IA-NEXT: sll a1, a1, a3 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB65_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a3, (a2) -; RV32IA-NEXT: sub a5, a3, a1 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: sc.w a5, a5, (a2) +; RV32IA-NEXT: lr.w a4, (a0) +; RV32IA-NEXT: sub a5, a4, a1 +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: and a5, a5, a2 +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB65_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a3, a0 +; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_sub_i16_monotonic: @@ -5733,24 +5733,24 @@ define i16 @atomicrmw_sub_i16_monotonic(i16* %a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_sub_i16_monotonic: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a4, a3, a0 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a3, a0, 3 +; RV64IA-NEXT: andi a3, a3, 24 +; RV64IA-NEXT: sllw a2, a2, a3 +; RV64IA-NEXT: sllw a1, a1, a3 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB65_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w a3, (a2) -; RV64IA-NEXT: sub a5, a3, a1 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: and a5, a5, a4 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: sc.w a5, a5, (a2) +; RV64IA-NEXT: lr.w a4, (a0) +; RV64IA-NEXT: sub a5, a4, a1 +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: and a5, a5, a2 +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB65_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a3, a0 +; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: ret %1 = atomicrmw sub i16* %a, i16 %b monotonic ret i16 %1 @@ -5769,24 +5769,24 @@ define i16 @atomicrmw_sub_i16_acquire(i16* %a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_sub_i16_acquire: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a3, a0, 3 +; RV32IA-NEXT: andi a3, a3, 24 +; RV32IA-NEXT: sll a2, a2, a3 +; RV32IA-NEXT: sll a1, a1, a3 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB66_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aq a3, (a2) -; RV32IA-NEXT: sub a5, a3, a1 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: sc.w a5, a5, (a2) +; RV32IA-NEXT: lr.w.aq a4, (a0) +; RV32IA-NEXT: sub a5, a4, a1 +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: and a5, a5, a2 +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB66_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a3, a0 +; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_sub_i16_acquire: @@ -5801,24 +5801,24 @@ define i16 @atomicrmw_sub_i16_acquire(i16* %a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_sub_i16_acquire: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a4, a3, a0 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a3, a0, 3 +; RV64IA-NEXT: andi a3, a3, 24 +; RV64IA-NEXT: sllw a2, a2, a3 +; RV64IA-NEXT: sllw a1, a1, a3 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB66_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aq a3, (a2) -; RV64IA-NEXT: sub a5, a3, a1 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: and a5, a5, a4 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: sc.w a5, a5, (a2) +; RV64IA-NEXT: lr.w.aq a4, (a0) +; RV64IA-NEXT: sub a5, a4, a1 +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: and a5, a5, a2 +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB66_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a3, a0 +; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: ret %1 = atomicrmw sub i16* %a, i16 %b acquire ret i16 %1 @@ -5837,24 +5837,24 @@ define i16 @atomicrmw_sub_i16_release(i16* %a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_sub_i16_release: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a3, a0, 3 +; RV32IA-NEXT: andi a3, a3, 24 +; RV32IA-NEXT: sll a2, a2, a3 +; RV32IA-NEXT: sll a1, a1, a3 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB67_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a3, (a2) -; RV32IA-NEXT: sub a5, a3, a1 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-NEXT: lr.w a4, (a0) +; RV32IA-NEXT: sub a5, a4, a1 +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: and a5, a5, a2 +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB67_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a3, a0 +; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_sub_i16_release: @@ -5869,24 +5869,24 @@ define i16 @atomicrmw_sub_i16_release(i16* %a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_sub_i16_release: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a4, a3, a0 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a3, a0, 3 +; RV64IA-NEXT: andi a3, a3, 24 +; RV64IA-NEXT: sllw a2, a2, a3 +; RV64IA-NEXT: sllw a1, a1, a3 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB67_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w a3, (a2) -; RV64IA-NEXT: sub a5, a3, a1 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: and a5, a5, a4 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: sc.w.rl a5, a5, (a2) +; RV64IA-NEXT: lr.w a4, (a0) +; RV64IA-NEXT: sub a5, a4, a1 +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: and a5, a5, a2 +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB67_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a3, a0 +; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: ret %1 = atomicrmw sub i16* %a, i16 %b release ret i16 %1 @@ -5905,24 +5905,24 @@ define i16 @atomicrmw_sub_i16_acq_rel(i16* %a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_sub_i16_acq_rel: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a3, a0, 3 +; RV32IA-NEXT: andi a3, a3, 24 +; RV32IA-NEXT: sll a2, a2, a3 +; RV32IA-NEXT: sll a1, a1, a3 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB68_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aq a3, (a2) -; RV32IA-NEXT: sub a5, a3, a1 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-NEXT: lr.w.aq a4, (a0) +; RV32IA-NEXT: sub a5, a4, a1 +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: and a5, a5, a2 +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB68_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a3, a0 +; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_sub_i16_acq_rel: @@ -5937,24 +5937,24 @@ define i16 @atomicrmw_sub_i16_acq_rel(i16* %a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_sub_i16_acq_rel: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a4, a3, a0 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a3, a0, 3 +; RV64IA-NEXT: andi a3, a3, 24 +; RV64IA-NEXT: sllw a2, a2, a3 +; RV64IA-NEXT: sllw a1, a1, a3 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB68_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aq a3, (a2) -; RV64IA-NEXT: sub a5, a3, a1 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: and a5, a5, a4 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: sc.w.rl a5, a5, (a2) +; RV64IA-NEXT: lr.w.aq a4, (a0) +; RV64IA-NEXT: sub a5, a4, a1 +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: and a5, a5, a2 +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB68_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a3, a0 +; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: ret %1 = atomicrmw sub i16* %a, i16 %b acq_rel ret i16 %1 @@ -5973,24 +5973,24 @@ define i16 @atomicrmw_sub_i16_seq_cst(i16* %a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_sub_i16_seq_cst: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a3, a0, 3 +; RV32IA-NEXT: andi a3, a3, 24 +; RV32IA-NEXT: sll a2, a2, a3 +; RV32IA-NEXT: sll a1, a1, a3 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB69_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aqrl a3, (a2) -; RV32IA-NEXT: sub a5, a3, a1 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: sc.w.aqrl a5, a5, (a2) +; RV32IA-NEXT: lr.w.aqrl a4, (a0) +; RV32IA-NEXT: sub a5, a4, a1 +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: and a5, a5, a2 +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB69_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a3, a0 +; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_sub_i16_seq_cst: @@ -6005,24 +6005,24 @@ define i16 @atomicrmw_sub_i16_seq_cst(i16* %a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_sub_i16_seq_cst: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a4, a3, a0 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a3, a0, 3 +; RV64IA-NEXT: andi a3, a3, 24 +; RV64IA-NEXT: sllw a2, a2, a3 +; RV64IA-NEXT: sllw a1, a1, a3 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB69_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aqrl a3, (a2) -; RV64IA-NEXT: sub a5, a3, a1 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: and a5, a5, a4 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: sc.w.aqrl a5, a5, (a2) +; RV64IA-NEXT: lr.w.aqrl a4, (a0) +; RV64IA-NEXT: sub a5, a4, a1 +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: and a5, a5, a2 +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB69_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a3, a0 +; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: ret %1 = atomicrmw sub i16* %a, i16 %b seq_cst ret i16 %1 @@ -6041,18 +6041,18 @@ define i16 @atomicrmw_and_i16_monotonic(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_and_i16_monotonic: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: not a4, a4 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: or a1, a4, a1 -; RV32IA-NEXT: amoand.w a1, a1, (a2) -; RV32IA-NEXT: srl a0, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a3, a0, 3 +; RV32IA-NEXT: andi a3, a3, 24 +; RV32IA-NEXT: sll a1, a1, a3 +; RV32IA-NEXT: sll a2, a2, a3 +; RV32IA-NEXT: not a2, a2 +; RV32IA-NEXT: or a1, a2, a1 +; RV32IA-NEXT: andi a0, a0, -4 +; RV32IA-NEXT: amoand.w a0, a1, (a0) +; RV32IA-NEXT: srl a0, a0, a3 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_and_i16_monotonic: @@ -6067,18 +6067,18 @@ define i16 @atomicrmw_and_i16_monotonic(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_and_i16_monotonic: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a4, a3, a0 -; RV64IA-NEXT: not a4, a4 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: or a1, a4, a1 -; RV64IA-NEXT: amoand.w a1, a1, (a2) -; RV64IA-NEXT: srlw a0, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a3, a0, 3 +; RV64IA-NEXT: andi a3, a3, 24 +; RV64IA-NEXT: sllw a1, a1, a3 +; RV64IA-NEXT: sllw a2, a2, a3 +; RV64IA-NEXT: not a2, a2 +; RV64IA-NEXT: or a1, a2, a1 +; RV64IA-NEXT: andi a0, a0, -4 +; RV64IA-NEXT: amoand.w a0, a1, (a0) +; RV64IA-NEXT: srlw a0, a0, a3 ; RV64IA-NEXT: ret %1 = atomicrmw and i16* %a, i16 %b monotonic ret i16 %1 @@ -6097,18 +6097,18 @@ define i16 @atomicrmw_and_i16_acquire(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_and_i16_acquire: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: not a4, a4 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: or a1, a4, a1 -; RV32IA-NEXT: amoand.w.aq a1, a1, (a2) -; RV32IA-NEXT: srl a0, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a3, a0, 3 +; RV32IA-NEXT: andi a3, a3, 24 +; RV32IA-NEXT: sll a1, a1, a3 +; RV32IA-NEXT: sll a2, a2, a3 +; RV32IA-NEXT: not a2, a2 +; RV32IA-NEXT: or a1, a2, a1 +; RV32IA-NEXT: andi a0, a0, -4 +; RV32IA-NEXT: amoand.w.aq a0, a1, (a0) +; RV32IA-NEXT: srl a0, a0, a3 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_and_i16_acquire: @@ -6123,18 +6123,18 @@ define i16 @atomicrmw_and_i16_acquire(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_and_i16_acquire: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a4, a3, a0 -; RV64IA-NEXT: not a4, a4 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: or a1, a4, a1 -; RV64IA-NEXT: amoand.w.aq a1, a1, (a2) -; RV64IA-NEXT: srlw a0, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a3, a0, 3 +; RV64IA-NEXT: andi a3, a3, 24 +; RV64IA-NEXT: sllw a1, a1, a3 +; RV64IA-NEXT: sllw a2, a2, a3 +; RV64IA-NEXT: not a2, a2 +; RV64IA-NEXT: or a1, a2, a1 +; RV64IA-NEXT: andi a0, a0, -4 +; RV64IA-NEXT: amoand.w.aq a0, a1, (a0) +; RV64IA-NEXT: srlw a0, a0, a3 ; RV64IA-NEXT: ret %1 = atomicrmw and i16* %a, i16 %b acquire ret i16 %1 @@ -6153,18 +6153,18 @@ define i16 @atomicrmw_and_i16_release(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_and_i16_release: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: not a4, a4 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: or a1, a4, a1 -; RV32IA-NEXT: amoand.w.rl a1, a1, (a2) -; RV32IA-NEXT: srl a0, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a3, a0, 3 +; RV32IA-NEXT: andi a3, a3, 24 +; RV32IA-NEXT: sll a1, a1, a3 +; RV32IA-NEXT: sll a2, a2, a3 +; RV32IA-NEXT: not a2, a2 +; RV32IA-NEXT: or a1, a2, a1 +; RV32IA-NEXT: andi a0, a0, -4 +; RV32IA-NEXT: amoand.w.rl a0, a1, (a0) +; RV32IA-NEXT: srl a0, a0, a3 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_and_i16_release: @@ -6179,18 +6179,18 @@ define i16 @atomicrmw_and_i16_release(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_and_i16_release: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a4, a3, a0 -; RV64IA-NEXT: not a4, a4 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: or a1, a4, a1 -; RV64IA-NEXT: amoand.w.rl a1, a1, (a2) -; RV64IA-NEXT: srlw a0, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a3, a0, 3 +; RV64IA-NEXT: andi a3, a3, 24 +; RV64IA-NEXT: sllw a1, a1, a3 +; RV64IA-NEXT: sllw a2, a2, a3 +; RV64IA-NEXT: not a2, a2 +; RV64IA-NEXT: or a1, a2, a1 +; RV64IA-NEXT: andi a0, a0, -4 +; RV64IA-NEXT: amoand.w.rl a0, a1, (a0) +; RV64IA-NEXT: srlw a0, a0, a3 ; RV64IA-NEXT: ret %1 = atomicrmw and i16* %a, i16 %b release ret i16 %1 @@ -6209,18 +6209,18 @@ define i16 @atomicrmw_and_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_and_i16_acq_rel: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: not a4, a4 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: or a1, a4, a1 -; RV32IA-NEXT: amoand.w.aqrl a1, a1, (a2) -; RV32IA-NEXT: srl a0, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a3, a0, 3 +; RV32IA-NEXT: andi a3, a3, 24 +; RV32IA-NEXT: sll a1, a1, a3 +; RV32IA-NEXT: sll a2, a2, a3 +; RV32IA-NEXT: not a2, a2 +; RV32IA-NEXT: or a1, a2, a1 +; RV32IA-NEXT: andi a0, a0, -4 +; RV32IA-NEXT: amoand.w.aqrl a0, a1, (a0) +; RV32IA-NEXT: srl a0, a0, a3 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_and_i16_acq_rel: @@ -6235,18 +6235,18 @@ define i16 @atomicrmw_and_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_and_i16_acq_rel: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a4, a3, a0 -; RV64IA-NEXT: not a4, a4 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: or a1, a4, a1 -; RV64IA-NEXT: amoand.w.aqrl a1, a1, (a2) -; RV64IA-NEXT: srlw a0, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a3, a0, 3 +; RV64IA-NEXT: andi a3, a3, 24 +; RV64IA-NEXT: sllw a1, a1, a3 +; RV64IA-NEXT: sllw a2, a2, a3 +; RV64IA-NEXT: not a2, a2 +; RV64IA-NEXT: or a1, a2, a1 +; RV64IA-NEXT: andi a0, a0, -4 +; RV64IA-NEXT: amoand.w.aqrl a0, a1, (a0) +; RV64IA-NEXT: srlw a0, a0, a3 ; RV64IA-NEXT: ret %1 = atomicrmw and i16* %a, i16 %b acq_rel ret i16 %1 @@ -6265,18 +6265,18 @@ define i16 @atomicrmw_and_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_and_i16_seq_cst: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: not a4, a4 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: or a1, a4, a1 -; RV32IA-NEXT: amoand.w.aqrl a1, a1, (a2) -; RV32IA-NEXT: srl a0, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a3, a0, 3 +; RV32IA-NEXT: andi a3, a3, 24 +; RV32IA-NEXT: sll a1, a1, a3 +; RV32IA-NEXT: sll a2, a2, a3 +; RV32IA-NEXT: not a2, a2 +; RV32IA-NEXT: or a1, a2, a1 +; RV32IA-NEXT: andi a0, a0, -4 +; RV32IA-NEXT: amoand.w.aqrl a0, a1, (a0) +; RV32IA-NEXT: srl a0, a0, a3 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_and_i16_seq_cst: @@ -6291,18 +6291,18 @@ define i16 @atomicrmw_and_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_and_i16_seq_cst: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a4, a3, a0 -; RV64IA-NEXT: not a4, a4 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: or a1, a4, a1 -; RV64IA-NEXT: amoand.w.aqrl a1, a1, (a2) -; RV64IA-NEXT: srlw a0, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a3, a0, 3 +; RV64IA-NEXT: andi a3, a3, 24 +; RV64IA-NEXT: sllw a1, a1, a3 +; RV64IA-NEXT: sllw a2, a2, a3 +; RV64IA-NEXT: not a2, a2 +; RV64IA-NEXT: or a1, a2, a1 +; RV64IA-NEXT: andi a0, a0, -4 +; RV64IA-NEXT: amoand.w.aqrl a0, a1, (a0) +; RV64IA-NEXT: srlw a0, a0, a3 ; RV64IA-NEXT: ret %1 = atomicrmw and i16* %a, i16 %b seq_cst ret i16 %1 @@ -6321,25 +6321,25 @@ define i16 @atomicrmw_nand_i16_monotonic(i16* %a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_nand_i16_monotonic: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a3, a0, 3 +; RV32IA-NEXT: andi a3, a3, 24 +; RV32IA-NEXT: sll a2, a2, a3 +; RV32IA-NEXT: sll a1, a1, a3 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB75_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a3, (a2) -; RV32IA-NEXT: and a5, a3, a1 +; RV32IA-NEXT: lr.w a4, (a0) +; RV32IA-NEXT: and a5, a4, a1 ; RV32IA-NEXT: not a5, a5 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: sc.w a5, a5, (a2) +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: and a5, a5, a2 +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB75_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a3, a0 +; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_nand_i16_monotonic: @@ -6354,25 +6354,25 @@ define i16 @atomicrmw_nand_i16_monotonic(i16* %a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_nand_i16_monotonic: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a4, a3, a0 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a3, a0, 3 +; RV64IA-NEXT: andi a3, a3, 24 +; RV64IA-NEXT: sllw a2, a2, a3 +; RV64IA-NEXT: sllw a1, a1, a3 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB75_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w a3, (a2) -; RV64IA-NEXT: and a5, a3, a1 +; RV64IA-NEXT: lr.w a4, (a0) +; RV64IA-NEXT: and a5, a4, a1 ; RV64IA-NEXT: not a5, a5 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: and a5, a5, a4 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: sc.w a5, a5, (a2) +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: and a5, a5, a2 +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB75_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a3, a0 +; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: ret %1 = atomicrmw nand i16* %a, i16 %b monotonic ret i16 %1 @@ -6391,25 +6391,25 @@ define i16 @atomicrmw_nand_i16_acquire(i16* %a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_nand_i16_acquire: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a3, a0, 3 +; RV32IA-NEXT: andi a3, a3, 24 +; RV32IA-NEXT: sll a2, a2, a3 +; RV32IA-NEXT: sll a1, a1, a3 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB76_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aq a3, (a2) -; RV32IA-NEXT: and a5, a3, a1 +; RV32IA-NEXT: lr.w.aq a4, (a0) +; RV32IA-NEXT: and a5, a4, a1 ; RV32IA-NEXT: not a5, a5 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: sc.w a5, a5, (a2) +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: and a5, a5, a2 +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB76_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a3, a0 +; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_nand_i16_acquire: @@ -6424,25 +6424,25 @@ define i16 @atomicrmw_nand_i16_acquire(i16* %a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_nand_i16_acquire: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a4, a3, a0 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a3, a0, 3 +; RV64IA-NEXT: andi a3, a3, 24 +; RV64IA-NEXT: sllw a2, a2, a3 +; RV64IA-NEXT: sllw a1, a1, a3 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB76_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aq a3, (a2) -; RV64IA-NEXT: and a5, a3, a1 +; RV64IA-NEXT: lr.w.aq a4, (a0) +; RV64IA-NEXT: and a5, a4, a1 ; RV64IA-NEXT: not a5, a5 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: and a5, a5, a4 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: sc.w a5, a5, (a2) +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: and a5, a5, a2 +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB76_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a3, a0 +; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: ret %1 = atomicrmw nand i16* %a, i16 %b acquire ret i16 %1 @@ -6461,25 +6461,25 @@ define i16 @atomicrmw_nand_i16_release(i16* %a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_nand_i16_release: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a3, a0, 3 +; RV32IA-NEXT: andi a3, a3, 24 +; RV32IA-NEXT: sll a2, a2, a3 +; RV32IA-NEXT: sll a1, a1, a3 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB77_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a3, (a2) -; RV32IA-NEXT: and a5, a3, a1 +; RV32IA-NEXT: lr.w a4, (a0) +; RV32IA-NEXT: and a5, a4, a1 ; RV32IA-NEXT: not a5, a5 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: and a5, a5, a2 +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB77_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a3, a0 +; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_nand_i16_release: @@ -6494,25 +6494,25 @@ define i16 @atomicrmw_nand_i16_release(i16* %a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_nand_i16_release: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a4, a3, a0 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a3, a0, 3 +; RV64IA-NEXT: andi a3, a3, 24 +; RV64IA-NEXT: sllw a2, a2, a3 +; RV64IA-NEXT: sllw a1, a1, a3 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB77_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w a3, (a2) -; RV64IA-NEXT: and a5, a3, a1 +; RV64IA-NEXT: lr.w a4, (a0) +; RV64IA-NEXT: and a5, a4, a1 ; RV64IA-NEXT: not a5, a5 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: and a5, a5, a4 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: sc.w.rl a5, a5, (a2) +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: and a5, a5, a2 +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB77_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a3, a0 +; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: ret %1 = atomicrmw nand i16* %a, i16 %b release ret i16 %1 @@ -6531,25 +6531,25 @@ define i16 @atomicrmw_nand_i16_acq_rel(i16* %a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_nand_i16_acq_rel: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a3, a0, 3 +; RV32IA-NEXT: andi a3, a3, 24 +; RV32IA-NEXT: sll a2, a2, a3 +; RV32IA-NEXT: sll a1, a1, a3 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB78_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aq a3, (a2) -; RV32IA-NEXT: and a5, a3, a1 +; RV32IA-NEXT: lr.w.aq a4, (a0) +; RV32IA-NEXT: and a5, a4, a1 ; RV32IA-NEXT: not a5, a5 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: and a5, a5, a2 +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB78_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a3, a0 +; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_nand_i16_acq_rel: @@ -6564,25 +6564,25 @@ define i16 @atomicrmw_nand_i16_acq_rel(i16* %a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_nand_i16_acq_rel: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a4, a3, a0 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a3, a0, 3 +; RV64IA-NEXT: andi a3, a3, 24 +; RV64IA-NEXT: sllw a2, a2, a3 +; RV64IA-NEXT: sllw a1, a1, a3 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB78_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aq a3, (a2) -; RV64IA-NEXT: and a5, a3, a1 +; RV64IA-NEXT: lr.w.aq a4, (a0) +; RV64IA-NEXT: and a5, a4, a1 ; RV64IA-NEXT: not a5, a5 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: and a5, a5, a4 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: sc.w.rl a5, a5, (a2) +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: and a5, a5, a2 +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB78_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a3, a0 +; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: ret %1 = atomicrmw nand i16* %a, i16 %b acq_rel ret i16 %1 @@ -6601,25 +6601,25 @@ define i16 @atomicrmw_nand_i16_seq_cst(i16* %a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_nand_i16_seq_cst: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a3, a0, 3 +; RV32IA-NEXT: andi a3, a3, 24 +; RV32IA-NEXT: sll a2, a2, a3 +; RV32IA-NEXT: sll a1, a1, a3 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB79_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aqrl a3, (a2) -; RV32IA-NEXT: and a5, a3, a1 +; RV32IA-NEXT: lr.w.aqrl a4, (a0) +; RV32IA-NEXT: and a5, a4, a1 ; RV32IA-NEXT: not a5, a5 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: sc.w.aqrl a5, a5, (a2) +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: and a5, a5, a2 +; RV32IA-NEXT: xor a5, a4, a5 +; RV32IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB79_1 ; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a3, a0 +; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_nand_i16_seq_cst: @@ -6634,25 +6634,25 @@ define i16 @atomicrmw_nand_i16_seq_cst(i16* %a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_nand_i16_seq_cst: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a4, a3, a0 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a3, a0, 3 +; RV64IA-NEXT: andi a3, a3, 24 +; RV64IA-NEXT: sllw a2, a2, a3 +; RV64IA-NEXT: sllw a1, a1, a3 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB79_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aqrl a3, (a2) -; RV64IA-NEXT: and a5, a3, a1 +; RV64IA-NEXT: lr.w.aqrl a4, (a0) +; RV64IA-NEXT: and a5, a4, a1 ; RV64IA-NEXT: not a5, a5 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: and a5, a5, a4 -; RV64IA-NEXT: xor a5, a3, a5 -; RV64IA-NEXT: sc.w.aqrl a5, a5, (a2) +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: and a5, a5, a2 +; RV64IA-NEXT: xor a5, a4, a5 +; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB79_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: srlw a0, a3, a0 +; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: ret %1 = atomicrmw nand i16* %a, i16 %b seq_cst ret i16 %1 @@ -6671,15 +6671,15 @@ define i16 @atomicrmw_or_i16_monotonic(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_or_i16_monotonic: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: amoor.w a1, a1, (a2) -; RV32IA-NEXT: srl a0, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 +; RV32IA-NEXT: amoor.w a0, a1, (a0) +; RV32IA-NEXT: srl a0, a0, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_or_i16_monotonic: @@ -6694,15 +6694,15 @@ define i16 @atomicrmw_or_i16_monotonic(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_or_i16_monotonic: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: amoor.w a1, a1, (a2) -; RV64IA-NEXT: srlw a0, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 +; RV64IA-NEXT: amoor.w a0, a1, (a0) +; RV64IA-NEXT: srlw a0, a0, a2 ; RV64IA-NEXT: ret %1 = atomicrmw or i16* %a, i16 %b monotonic ret i16 %1 @@ -6721,15 +6721,15 @@ define i16 @atomicrmw_or_i16_acquire(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_or_i16_acquire: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: amoor.w.aq a1, a1, (a2) -; RV32IA-NEXT: srl a0, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 +; RV32IA-NEXT: amoor.w.aq a0, a1, (a0) +; RV32IA-NEXT: srl a0, a0, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_or_i16_acquire: @@ -6744,15 +6744,15 @@ define i16 @atomicrmw_or_i16_acquire(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_or_i16_acquire: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: amoor.w.aq a1, a1, (a2) -; RV64IA-NEXT: srlw a0, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 +; RV64IA-NEXT: amoor.w.aq a0, a1, (a0) +; RV64IA-NEXT: srlw a0, a0, a2 ; RV64IA-NEXT: ret %1 = atomicrmw or i16* %a, i16 %b acquire ret i16 %1 @@ -6771,15 +6771,15 @@ define i16 @atomicrmw_or_i16_release(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_or_i16_release: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: amoor.w.rl a1, a1, (a2) -; RV32IA-NEXT: srl a0, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 +; RV32IA-NEXT: amoor.w.rl a0, a1, (a0) +; RV32IA-NEXT: srl a0, a0, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_or_i16_release: @@ -6794,15 +6794,15 @@ define i16 @atomicrmw_or_i16_release(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_or_i16_release: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: amoor.w.rl a1, a1, (a2) -; RV64IA-NEXT: srlw a0, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 +; RV64IA-NEXT: amoor.w.rl a0, a1, (a0) +; RV64IA-NEXT: srlw a0, a0, a2 ; RV64IA-NEXT: ret %1 = atomicrmw or i16* %a, i16 %b release ret i16 %1 @@ -6821,15 +6821,15 @@ define i16 @atomicrmw_or_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_or_i16_acq_rel: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: amoor.w.aqrl a1, a1, (a2) -; RV32IA-NEXT: srl a0, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 +; RV32IA-NEXT: amoor.w.aqrl a0, a1, (a0) +; RV32IA-NEXT: srl a0, a0, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_or_i16_acq_rel: @@ -6844,15 +6844,15 @@ define i16 @atomicrmw_or_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_or_i16_acq_rel: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: amoor.w.aqrl a1, a1, (a2) -; RV64IA-NEXT: srlw a0, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 +; RV64IA-NEXT: amoor.w.aqrl a0, a1, (a0) +; RV64IA-NEXT: srlw a0, a0, a2 ; RV64IA-NEXT: ret %1 = atomicrmw or i16* %a, i16 %b acq_rel ret i16 %1 @@ -6871,15 +6871,15 @@ define i16 @atomicrmw_or_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_or_i16_seq_cst: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: amoor.w.aqrl a1, a1, (a2) -; RV32IA-NEXT: srl a0, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 +; RV32IA-NEXT: amoor.w.aqrl a0, a1, (a0) +; RV32IA-NEXT: srl a0, a0, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_or_i16_seq_cst: @@ -6894,15 +6894,15 @@ define i16 @atomicrmw_or_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_or_i16_seq_cst: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: amoor.w.aqrl a1, a1, (a2) -; RV64IA-NEXT: srlw a0, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 +; RV64IA-NEXT: amoor.w.aqrl a0, a1, (a0) +; RV64IA-NEXT: srlw a0, a0, a2 ; RV64IA-NEXT: ret %1 = atomicrmw or i16* %a, i16 %b seq_cst ret i16 %1 @@ -6921,15 +6921,15 @@ define i16 @atomicrmw_xor_i16_monotonic(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_xor_i16_monotonic: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: amoxor.w a1, a1, (a2) -; RV32IA-NEXT: srl a0, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 +; RV32IA-NEXT: amoxor.w a0, a1, (a0) +; RV32IA-NEXT: srl a0, a0, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xor_i16_monotonic: @@ -6944,15 +6944,15 @@ define i16 @atomicrmw_xor_i16_monotonic(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_xor_i16_monotonic: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: amoxor.w a1, a1, (a2) -; RV64IA-NEXT: srlw a0, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 +; RV64IA-NEXT: amoxor.w a0, a1, (a0) +; RV64IA-NEXT: srlw a0, a0, a2 ; RV64IA-NEXT: ret %1 = atomicrmw xor i16* %a, i16 %b monotonic ret i16 %1 @@ -6971,15 +6971,15 @@ define i16 @atomicrmw_xor_i16_acquire(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_xor_i16_acquire: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: amoxor.w.aq a1, a1, (a2) -; RV32IA-NEXT: srl a0, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 +; RV32IA-NEXT: amoxor.w.aq a0, a1, (a0) +; RV32IA-NEXT: srl a0, a0, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xor_i16_acquire: @@ -6994,15 +6994,15 @@ define i16 @atomicrmw_xor_i16_acquire(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_xor_i16_acquire: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: amoxor.w.aq a1, a1, (a2) -; RV64IA-NEXT: srlw a0, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 +; RV64IA-NEXT: amoxor.w.aq a0, a1, (a0) +; RV64IA-NEXT: srlw a0, a0, a2 ; RV64IA-NEXT: ret %1 = atomicrmw xor i16* %a, i16 %b acquire ret i16 %1 @@ -7021,15 +7021,15 @@ define i16 @atomicrmw_xor_i16_release(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_xor_i16_release: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: amoxor.w.rl a1, a1, (a2) -; RV32IA-NEXT: srl a0, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 +; RV32IA-NEXT: amoxor.w.rl a0, a1, (a0) +; RV32IA-NEXT: srl a0, a0, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xor_i16_release: @@ -7044,15 +7044,15 @@ define i16 @atomicrmw_xor_i16_release(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_xor_i16_release: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: amoxor.w.rl a1, a1, (a2) -; RV64IA-NEXT: srlw a0, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 +; RV64IA-NEXT: amoxor.w.rl a0, a1, (a0) +; RV64IA-NEXT: srlw a0, a0, a2 ; RV64IA-NEXT: ret %1 = atomicrmw xor i16* %a, i16 %b release ret i16 %1 @@ -7071,15 +7071,15 @@ define i16 @atomicrmw_xor_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_xor_i16_acq_rel: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: amoxor.w.aqrl a1, a1, (a2) -; RV32IA-NEXT: srl a0, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 +; RV32IA-NEXT: amoxor.w.aqrl a0, a1, (a0) +; RV32IA-NEXT: srl a0, a0, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xor_i16_acq_rel: @@ -7094,15 +7094,15 @@ define i16 @atomicrmw_xor_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_xor_i16_acq_rel: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: amoxor.w.aqrl a1, a1, (a2) -; RV64IA-NEXT: srlw a0, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 +; RV64IA-NEXT: amoxor.w.aqrl a0, a1, (a0) +; RV64IA-NEXT: srlw a0, a0, a2 ; RV64IA-NEXT: ret %1 = atomicrmw xor i16* %a, i16 %b acq_rel ret i16 %1 @@ -7121,15 +7121,15 @@ define i16 @atomicrmw_xor_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_xor_i16_seq_cst: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: amoxor.w.aqrl a1, a1, (a2) -; RV32IA-NEXT: srl a0, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 +; RV32IA-NEXT: amoxor.w.aqrl a0, a1, (a0) +; RV32IA-NEXT: srl a0, a0, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xor_i16_seq_cst: @@ -7144,15 +7144,15 @@ define i16 @atomicrmw_xor_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_xor_i16_seq_cst: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a2, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: amoxor.w.aqrl a1, a1, (a2) -; RV64IA-NEXT: srlw a0, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 +; RV64IA-NEXT: amoxor.w.aqrl a0, a1, (a0) +; RV64IA-NEXT: srlw a0, a0, a2 ; RV64IA-NEXT: ret %1 = atomicrmw xor i16* %a, i16 %b seq_cst ret i16 %1 @@ -7169,33 +7169,33 @@ define i16 @atomicrmw_max_i16_monotonic(i16 *%a, i16 %b) nounwind { ; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: lhu a1, 0(a0) -; RV32I-NEXT: slli a0, s2, 16 -; RV32I-NEXT: srai s0, a0, 16 +; RV32I-NEXT: lhu a0, 0(a0) +; RV32I-NEXT: slli a1, a1, 16 +; RV32I-NEXT: srai s0, a1, 16 ; RV32I-NEXT: addi s3, sp, 10 ; RV32I-NEXT: j .LBB90_2 ; RV32I-NEXT: .LBB90_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB90_2 Depth=1 -; RV32I-NEXT: sh a1, 10(sp) +; RV32I-NEXT: sh a0, 10(sp) ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: call __atomic_compare_exchange_2 -; RV32I-NEXT: lh a1, 10(sp) -; RV32I-NEXT: bnez a0, .LBB90_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lh a0, 10(sp) +; RV32I-NEXT: bnez a1, .LBB90_4 ; RV32I-NEXT: .LBB90_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: slli a0, a1, 16 -; RV32I-NEXT: srai a0, a0, 16 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: blt s0, a0, .LBB90_1 +; RV32I-NEXT: slli a1, a0, 16 +; RV32I-NEXT: srai a1, a1, 16 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: blt s0, a1, .LBB90_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB90_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB90_1 ; RV32I-NEXT: .LBB90_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -7206,33 +7206,33 @@ define i16 @atomicrmw_max_i16_monotonic(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_max_i16_monotonic: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a7, a3, a0 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: addi a3, zero, 16 +; RV32IA-NEXT: sub a6, a3, a2 +; RV32IA-NEXT: lui a4, 16 +; RV32IA-NEXT: addi a4, a4, -1 +; RV32IA-NEXT: sll a7, a4, a2 ; RV32IA-NEXT: slli a1, a1, 16 ; RV32IA-NEXT: srai a1, a1, 16 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: addi a4, zero, 16 -; RV32IA-NEXT: sub a4, a4, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB90_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a5, (a6) -; RV32IA-NEXT: and a3, a5, a7 -; RV32IA-NEXT: mv a2, a5 -; RV32IA-NEXT: sll a3, a3, a4 -; RV32IA-NEXT: sra a3, a3, a4 -; RV32IA-NEXT: bge a3, a1, .LBB90_3 +; RV32IA-NEXT: lr.w a5, (a0) +; RV32IA-NEXT: and a4, a5, a7 +; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sll a4, a4, a6 +; RV32IA-NEXT: sra a4, a4, a6 +; RV32IA-NEXT: bge a4, a1, .LBB90_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB90_1 Depth=1 -; RV32IA-NEXT: xor a2, a5, a1 -; RV32IA-NEXT: and a2, a2, a7 -; RV32IA-NEXT: xor a2, a5, a2 +; RV32IA-NEXT: xor a3, a5, a1 +; RV32IA-NEXT: and a3, a3, a7 +; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: .LBB90_3: # in Loop: Header=BB90_1 Depth=1 -; RV32IA-NEXT: sc.w a2, a2, (a6) -; RV32IA-NEXT: bnez a2, .LBB90_1 +; RV32IA-NEXT: sc.w a3, a3, (a0) +; RV32IA-NEXT: bnez a3, .LBB90_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a5, a0 +; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_max_i16_monotonic: @@ -7245,33 +7245,33 @@ define i16 @atomicrmw_max_i16_monotonic(i16 *%a, i16 %b) nounwind { ; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: lhu a1, 0(a0) -; RV64I-NEXT: slli a0, s2, 48 -; RV64I-NEXT: srai s0, a0, 48 +; RV64I-NEXT: lhu a0, 0(a0) +; RV64I-NEXT: slli a1, a1, 48 +; RV64I-NEXT: srai s0, a1, 48 ; RV64I-NEXT: addi s3, sp, 6 ; RV64I-NEXT: j .LBB90_2 ; RV64I-NEXT: .LBB90_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB90_2 Depth=1 -; RV64I-NEXT: sh a1, 6(sp) +; RV64I-NEXT: sh a0, 6(sp) ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: call __atomic_compare_exchange_2 -; RV64I-NEXT: lh a1, 6(sp) -; RV64I-NEXT: bnez a0, .LBB90_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lh a0, 6(sp) +; RV64I-NEXT: bnez a1, .LBB90_4 ; RV64I-NEXT: .LBB90_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: slli a0, a1, 48 -; RV64I-NEXT: srai a0, a0, 48 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: blt s0, a0, .LBB90_1 +; RV64I-NEXT: slli a1, a0, 48 +; RV64I-NEXT: srai a1, a1, 48 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: blt s0, a1, .LBB90_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB90_2 Depth=1 ; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB90_1 ; RV64I-NEXT: .LBB90_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -7282,33 +7282,33 @@ define i16 @atomicrmw_max_i16_monotonic(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_max_i16_monotonic: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a7, a3, a0 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: addi a3, zero, 48 +; RV64IA-NEXT: sub a6, a3, a2 +; RV64IA-NEXT: lui a4, 16 +; RV64IA-NEXT: addiw a4, a4, -1 +; RV64IA-NEXT: sllw a7, a4, a2 ; RV64IA-NEXT: slli a1, a1, 48 ; RV64IA-NEXT: srai a1, a1, 48 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: addi a4, zero, 48 -; RV64IA-NEXT: sub a4, a4, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB90_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w a5, (a6) -; RV64IA-NEXT: and a3, a5, a7 -; RV64IA-NEXT: mv a2, a5 -; RV64IA-NEXT: sll a3, a3, a4 -; RV64IA-NEXT: sra a3, a3, a4 -; RV64IA-NEXT: bge a3, a1, .LBB90_3 +; RV64IA-NEXT: lr.w a5, (a0) +; RV64IA-NEXT: and a4, a5, a7 +; RV64IA-NEXT: mv a3, a5 +; RV64IA-NEXT: sll a4, a4, a6 +; RV64IA-NEXT: sra a4, a4, a6 +; RV64IA-NEXT: bge a4, a1, .LBB90_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB90_1 Depth=1 -; RV64IA-NEXT: xor a2, a5, a1 -; RV64IA-NEXT: and a2, a2, a7 -; RV64IA-NEXT: xor a2, a5, a2 +; RV64IA-NEXT: xor a3, a5, a1 +; RV64IA-NEXT: and a3, a3, a7 +; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: .LBB90_3: # in Loop: Header=BB90_1 Depth=1 -; RV64IA-NEXT: sc.w a2, a2, (a6) -; RV64IA-NEXT: bnez a2, .LBB90_1 +; RV64IA-NEXT: sc.w a3, a3, (a0) +; RV64IA-NEXT: bnez a3, .LBB90_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a5, a0 +; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: ret %1 = atomicrmw max i16* %a, i16 %b monotonic ret i16 %1 @@ -7325,33 +7325,33 @@ define i16 @atomicrmw_max_i16_acquire(i16 *%a, i16 %b) nounwind { ; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: lhu a1, 0(a0) -; RV32I-NEXT: slli a0, s2, 16 -; RV32I-NEXT: srai s0, a0, 16 +; RV32I-NEXT: lhu a0, 0(a0) +; RV32I-NEXT: slli a1, a1, 16 +; RV32I-NEXT: srai s0, a1, 16 ; RV32I-NEXT: addi s3, sp, 10 ; RV32I-NEXT: j .LBB91_2 ; RV32I-NEXT: .LBB91_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB91_2 Depth=1 -; RV32I-NEXT: sh a1, 10(sp) -; RV32I-NEXT: addi a3, zero, 2 -; RV32I-NEXT: addi a4, zero, 2 +; RV32I-NEXT: sh a0, 10(sp) ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s3 +; RV32I-NEXT: addi a3, zero, 2 +; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: call __atomic_compare_exchange_2 -; RV32I-NEXT: lh a1, 10(sp) -; RV32I-NEXT: bnez a0, .LBB91_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lh a0, 10(sp) +; RV32I-NEXT: bnez a1, .LBB91_4 ; RV32I-NEXT: .LBB91_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: slli a0, a1, 16 -; RV32I-NEXT: srai a0, a0, 16 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: blt s0, a0, .LBB91_1 +; RV32I-NEXT: slli a1, a0, 16 +; RV32I-NEXT: srai a1, a1, 16 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: blt s0, a1, .LBB91_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB91_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB91_1 ; RV32I-NEXT: .LBB91_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -7362,33 +7362,33 @@ define i16 @atomicrmw_max_i16_acquire(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_max_i16_acquire: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a7, a3, a0 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: addi a3, zero, 16 +; RV32IA-NEXT: sub a6, a3, a2 +; RV32IA-NEXT: lui a4, 16 +; RV32IA-NEXT: addi a4, a4, -1 +; RV32IA-NEXT: sll a7, a4, a2 ; RV32IA-NEXT: slli a1, a1, 16 ; RV32IA-NEXT: srai a1, a1, 16 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: addi a4, zero, 16 -; RV32IA-NEXT: sub a4, a4, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB91_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aq a5, (a6) -; RV32IA-NEXT: and a3, a5, a7 -; RV32IA-NEXT: mv a2, a5 -; RV32IA-NEXT: sll a3, a3, a4 -; RV32IA-NEXT: sra a3, a3, a4 -; RV32IA-NEXT: bge a3, a1, .LBB91_3 +; RV32IA-NEXT: lr.w.aq a5, (a0) +; RV32IA-NEXT: and a4, a5, a7 +; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sll a4, a4, a6 +; RV32IA-NEXT: sra a4, a4, a6 +; RV32IA-NEXT: bge a4, a1, .LBB91_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB91_1 Depth=1 -; RV32IA-NEXT: xor a2, a5, a1 -; RV32IA-NEXT: and a2, a2, a7 -; RV32IA-NEXT: xor a2, a5, a2 +; RV32IA-NEXT: xor a3, a5, a1 +; RV32IA-NEXT: and a3, a3, a7 +; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: .LBB91_3: # in Loop: Header=BB91_1 Depth=1 -; RV32IA-NEXT: sc.w a2, a2, (a6) -; RV32IA-NEXT: bnez a2, .LBB91_1 +; RV32IA-NEXT: sc.w a3, a3, (a0) +; RV32IA-NEXT: bnez a3, .LBB91_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a5, a0 +; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_max_i16_acquire: @@ -7401,33 +7401,33 @@ define i16 @atomicrmw_max_i16_acquire(i16 *%a, i16 %b) nounwind { ; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: lhu a1, 0(a0) -; RV64I-NEXT: slli a0, s2, 48 -; RV64I-NEXT: srai s0, a0, 48 +; RV64I-NEXT: lhu a0, 0(a0) +; RV64I-NEXT: slli a1, a1, 48 +; RV64I-NEXT: srai s0, a1, 48 ; RV64I-NEXT: addi s3, sp, 6 ; RV64I-NEXT: j .LBB91_2 ; RV64I-NEXT: .LBB91_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB91_2 Depth=1 -; RV64I-NEXT: sh a1, 6(sp) -; RV64I-NEXT: addi a3, zero, 2 -; RV64I-NEXT: addi a4, zero, 2 +; RV64I-NEXT: sh a0, 6(sp) ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s3 +; RV64I-NEXT: addi a3, zero, 2 +; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: call __atomic_compare_exchange_2 -; RV64I-NEXT: lh a1, 6(sp) -; RV64I-NEXT: bnez a0, .LBB91_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lh a0, 6(sp) +; RV64I-NEXT: bnez a1, .LBB91_4 ; RV64I-NEXT: .LBB91_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: slli a0, a1, 48 -; RV64I-NEXT: srai a0, a0, 48 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: blt s0, a0, .LBB91_1 +; RV64I-NEXT: slli a1, a0, 48 +; RV64I-NEXT: srai a1, a1, 48 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: blt s0, a1, .LBB91_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB91_2 Depth=1 ; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB91_1 ; RV64I-NEXT: .LBB91_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -7438,33 +7438,33 @@ define i16 @atomicrmw_max_i16_acquire(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_max_i16_acquire: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a7, a3, a0 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: addi a3, zero, 48 +; RV64IA-NEXT: sub a6, a3, a2 +; RV64IA-NEXT: lui a4, 16 +; RV64IA-NEXT: addiw a4, a4, -1 +; RV64IA-NEXT: sllw a7, a4, a2 ; RV64IA-NEXT: slli a1, a1, 48 ; RV64IA-NEXT: srai a1, a1, 48 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: addi a4, zero, 48 -; RV64IA-NEXT: sub a4, a4, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB91_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aq a5, (a6) -; RV64IA-NEXT: and a3, a5, a7 -; RV64IA-NEXT: mv a2, a5 -; RV64IA-NEXT: sll a3, a3, a4 -; RV64IA-NEXT: sra a3, a3, a4 -; RV64IA-NEXT: bge a3, a1, .LBB91_3 +; RV64IA-NEXT: lr.w.aq a5, (a0) +; RV64IA-NEXT: and a4, a5, a7 +; RV64IA-NEXT: mv a3, a5 +; RV64IA-NEXT: sll a4, a4, a6 +; RV64IA-NEXT: sra a4, a4, a6 +; RV64IA-NEXT: bge a4, a1, .LBB91_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB91_1 Depth=1 -; RV64IA-NEXT: xor a2, a5, a1 -; RV64IA-NEXT: and a2, a2, a7 -; RV64IA-NEXT: xor a2, a5, a2 +; RV64IA-NEXT: xor a3, a5, a1 +; RV64IA-NEXT: and a3, a3, a7 +; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: .LBB91_3: # in Loop: Header=BB91_1 Depth=1 -; RV64IA-NEXT: sc.w a2, a2, (a6) -; RV64IA-NEXT: bnez a2, .LBB91_1 +; RV64IA-NEXT: sc.w a3, a3, (a0) +; RV64IA-NEXT: bnez a3, .LBB91_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a5, a0 +; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: ret %1 = atomicrmw max i16* %a, i16 %b acquire ret i16 %1 @@ -7481,33 +7481,33 @@ define i16 @atomicrmw_max_i16_release(i16 *%a, i16 %b) nounwind { ; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: lhu a1, 0(a0) -; RV32I-NEXT: slli a0, s2, 16 -; RV32I-NEXT: srai s0, a0, 16 +; RV32I-NEXT: lhu a0, 0(a0) +; RV32I-NEXT: slli a1, a1, 16 +; RV32I-NEXT: srai s0, a1, 16 ; RV32I-NEXT: addi s3, sp, 10 ; RV32I-NEXT: j .LBB92_2 ; RV32I-NEXT: .LBB92_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB92_2 Depth=1 -; RV32I-NEXT: sh a1, 10(sp) -; RV32I-NEXT: addi a3, zero, 3 +; RV32I-NEXT: sh a0, 10(sp) ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s3 +; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: call __atomic_compare_exchange_2 -; RV32I-NEXT: lh a1, 10(sp) -; RV32I-NEXT: bnez a0, .LBB92_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lh a0, 10(sp) +; RV32I-NEXT: bnez a1, .LBB92_4 ; RV32I-NEXT: .LBB92_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: slli a0, a1, 16 -; RV32I-NEXT: srai a0, a0, 16 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: blt s0, a0, .LBB92_1 +; RV32I-NEXT: slli a1, a0, 16 +; RV32I-NEXT: srai a1, a1, 16 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: blt s0, a1, .LBB92_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB92_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB92_1 ; RV32I-NEXT: .LBB92_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -7518,33 +7518,33 @@ define i16 @atomicrmw_max_i16_release(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_max_i16_release: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a7, a3, a0 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: addi a3, zero, 16 +; RV32IA-NEXT: sub a6, a3, a2 +; RV32IA-NEXT: lui a4, 16 +; RV32IA-NEXT: addi a4, a4, -1 +; RV32IA-NEXT: sll a7, a4, a2 ; RV32IA-NEXT: slli a1, a1, 16 ; RV32IA-NEXT: srai a1, a1, 16 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: addi a4, zero, 16 -; RV32IA-NEXT: sub a4, a4, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB92_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a5, (a6) -; RV32IA-NEXT: and a3, a5, a7 -; RV32IA-NEXT: mv a2, a5 -; RV32IA-NEXT: sll a3, a3, a4 -; RV32IA-NEXT: sra a3, a3, a4 -; RV32IA-NEXT: bge a3, a1, .LBB92_3 +; RV32IA-NEXT: lr.w a5, (a0) +; RV32IA-NEXT: and a4, a5, a7 +; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sll a4, a4, a6 +; RV32IA-NEXT: sra a4, a4, a6 +; RV32IA-NEXT: bge a4, a1, .LBB92_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB92_1 Depth=1 -; RV32IA-NEXT: xor a2, a5, a1 -; RV32IA-NEXT: and a2, a2, a7 -; RV32IA-NEXT: xor a2, a5, a2 +; RV32IA-NEXT: xor a3, a5, a1 +; RV32IA-NEXT: and a3, a3, a7 +; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: .LBB92_3: # in Loop: Header=BB92_1 Depth=1 -; RV32IA-NEXT: sc.w.rl a2, a2, (a6) -; RV32IA-NEXT: bnez a2, .LBB92_1 +; RV32IA-NEXT: sc.w.rl a3, a3, (a0) +; RV32IA-NEXT: bnez a3, .LBB92_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a5, a0 +; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_max_i16_release: @@ -7557,33 +7557,33 @@ define i16 @atomicrmw_max_i16_release(i16 *%a, i16 %b) nounwind { ; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: lhu a1, 0(a0) -; RV64I-NEXT: slli a0, s2, 48 -; RV64I-NEXT: srai s0, a0, 48 +; RV64I-NEXT: lhu a0, 0(a0) +; RV64I-NEXT: slli a1, a1, 48 +; RV64I-NEXT: srai s0, a1, 48 ; RV64I-NEXT: addi s3, sp, 6 ; RV64I-NEXT: j .LBB92_2 ; RV64I-NEXT: .LBB92_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB92_2 Depth=1 -; RV64I-NEXT: sh a1, 6(sp) -; RV64I-NEXT: addi a3, zero, 3 +; RV64I-NEXT: sh a0, 6(sp) ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s3 +; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: call __atomic_compare_exchange_2 -; RV64I-NEXT: lh a1, 6(sp) -; RV64I-NEXT: bnez a0, .LBB92_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lh a0, 6(sp) +; RV64I-NEXT: bnez a1, .LBB92_4 ; RV64I-NEXT: .LBB92_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: slli a0, a1, 48 -; RV64I-NEXT: srai a0, a0, 48 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: blt s0, a0, .LBB92_1 +; RV64I-NEXT: slli a1, a0, 48 +; RV64I-NEXT: srai a1, a1, 48 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: blt s0, a1, .LBB92_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB92_2 Depth=1 ; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB92_1 ; RV64I-NEXT: .LBB92_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -7594,33 +7594,33 @@ define i16 @atomicrmw_max_i16_release(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_max_i16_release: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a7, a3, a0 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: addi a3, zero, 48 +; RV64IA-NEXT: sub a6, a3, a2 +; RV64IA-NEXT: lui a4, 16 +; RV64IA-NEXT: addiw a4, a4, -1 +; RV64IA-NEXT: sllw a7, a4, a2 ; RV64IA-NEXT: slli a1, a1, 48 ; RV64IA-NEXT: srai a1, a1, 48 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: addi a4, zero, 48 -; RV64IA-NEXT: sub a4, a4, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB92_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w a5, (a6) -; RV64IA-NEXT: and a3, a5, a7 -; RV64IA-NEXT: mv a2, a5 -; RV64IA-NEXT: sll a3, a3, a4 -; RV64IA-NEXT: sra a3, a3, a4 -; RV64IA-NEXT: bge a3, a1, .LBB92_3 +; RV64IA-NEXT: lr.w a5, (a0) +; RV64IA-NEXT: and a4, a5, a7 +; RV64IA-NEXT: mv a3, a5 +; RV64IA-NEXT: sll a4, a4, a6 +; RV64IA-NEXT: sra a4, a4, a6 +; RV64IA-NEXT: bge a4, a1, .LBB92_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB92_1 Depth=1 -; RV64IA-NEXT: xor a2, a5, a1 -; RV64IA-NEXT: and a2, a2, a7 -; RV64IA-NEXT: xor a2, a5, a2 +; RV64IA-NEXT: xor a3, a5, a1 +; RV64IA-NEXT: and a3, a3, a7 +; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: .LBB92_3: # in Loop: Header=BB92_1 Depth=1 -; RV64IA-NEXT: sc.w.rl a2, a2, (a6) -; RV64IA-NEXT: bnez a2, .LBB92_1 +; RV64IA-NEXT: sc.w.rl a3, a3, (a0) +; RV64IA-NEXT: bnez a3, .LBB92_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a5, a0 +; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: ret %1 = atomicrmw max i16* %a, i16 %b release ret i16 %1 @@ -7637,33 +7637,33 @@ define i16 @atomicrmw_max_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: lhu a1, 0(a0) -; RV32I-NEXT: slli a0, s2, 16 -; RV32I-NEXT: srai s0, a0, 16 +; RV32I-NEXT: lhu a0, 0(a0) +; RV32I-NEXT: slli a1, a1, 16 +; RV32I-NEXT: srai s0, a1, 16 ; RV32I-NEXT: addi s3, sp, 10 ; RV32I-NEXT: j .LBB93_2 ; RV32I-NEXT: .LBB93_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB93_2 Depth=1 -; RV32I-NEXT: sh a1, 10(sp) -; RV32I-NEXT: addi a3, zero, 4 -; RV32I-NEXT: addi a4, zero, 2 +; RV32I-NEXT: sh a0, 10(sp) ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s3 +; RV32I-NEXT: addi a3, zero, 4 +; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: call __atomic_compare_exchange_2 -; RV32I-NEXT: lh a1, 10(sp) -; RV32I-NEXT: bnez a0, .LBB93_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lh a0, 10(sp) +; RV32I-NEXT: bnez a1, .LBB93_4 ; RV32I-NEXT: .LBB93_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: slli a0, a1, 16 -; RV32I-NEXT: srai a0, a0, 16 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: blt s0, a0, .LBB93_1 +; RV32I-NEXT: slli a1, a0, 16 +; RV32I-NEXT: srai a1, a1, 16 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: blt s0, a1, .LBB93_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB93_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB93_1 ; RV32I-NEXT: .LBB93_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -7674,33 +7674,33 @@ define i16 @atomicrmw_max_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_max_i16_acq_rel: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a7, a3, a0 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: addi a3, zero, 16 +; RV32IA-NEXT: sub a6, a3, a2 +; RV32IA-NEXT: lui a4, 16 +; RV32IA-NEXT: addi a4, a4, -1 +; RV32IA-NEXT: sll a7, a4, a2 ; RV32IA-NEXT: slli a1, a1, 16 ; RV32IA-NEXT: srai a1, a1, 16 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: addi a4, zero, 16 -; RV32IA-NEXT: sub a4, a4, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB93_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aq a5, (a6) -; RV32IA-NEXT: and a3, a5, a7 -; RV32IA-NEXT: mv a2, a5 -; RV32IA-NEXT: sll a3, a3, a4 -; RV32IA-NEXT: sra a3, a3, a4 -; RV32IA-NEXT: bge a3, a1, .LBB93_3 +; RV32IA-NEXT: lr.w.aq a5, (a0) +; RV32IA-NEXT: and a4, a5, a7 +; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sll a4, a4, a6 +; RV32IA-NEXT: sra a4, a4, a6 +; RV32IA-NEXT: bge a4, a1, .LBB93_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB93_1 Depth=1 -; RV32IA-NEXT: xor a2, a5, a1 -; RV32IA-NEXT: and a2, a2, a7 -; RV32IA-NEXT: xor a2, a5, a2 +; RV32IA-NEXT: xor a3, a5, a1 +; RV32IA-NEXT: and a3, a3, a7 +; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: .LBB93_3: # in Loop: Header=BB93_1 Depth=1 -; RV32IA-NEXT: sc.w.rl a2, a2, (a6) -; RV32IA-NEXT: bnez a2, .LBB93_1 +; RV32IA-NEXT: sc.w.rl a3, a3, (a0) +; RV32IA-NEXT: bnez a3, .LBB93_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a5, a0 +; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_max_i16_acq_rel: @@ -7713,33 +7713,33 @@ define i16 @atomicrmw_max_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: lhu a1, 0(a0) -; RV64I-NEXT: slli a0, s2, 48 -; RV64I-NEXT: srai s0, a0, 48 +; RV64I-NEXT: lhu a0, 0(a0) +; RV64I-NEXT: slli a1, a1, 48 +; RV64I-NEXT: srai s0, a1, 48 ; RV64I-NEXT: addi s3, sp, 6 ; RV64I-NEXT: j .LBB93_2 ; RV64I-NEXT: .LBB93_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB93_2 Depth=1 -; RV64I-NEXT: sh a1, 6(sp) -; RV64I-NEXT: addi a3, zero, 4 -; RV64I-NEXT: addi a4, zero, 2 +; RV64I-NEXT: sh a0, 6(sp) ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s3 +; RV64I-NEXT: addi a3, zero, 4 +; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: call __atomic_compare_exchange_2 -; RV64I-NEXT: lh a1, 6(sp) -; RV64I-NEXT: bnez a0, .LBB93_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lh a0, 6(sp) +; RV64I-NEXT: bnez a1, .LBB93_4 ; RV64I-NEXT: .LBB93_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: slli a0, a1, 48 -; RV64I-NEXT: srai a0, a0, 48 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: blt s0, a0, .LBB93_1 +; RV64I-NEXT: slli a1, a0, 48 +; RV64I-NEXT: srai a1, a1, 48 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: blt s0, a1, .LBB93_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB93_2 Depth=1 ; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB93_1 ; RV64I-NEXT: .LBB93_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -7750,33 +7750,33 @@ define i16 @atomicrmw_max_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_max_i16_acq_rel: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a7, a3, a0 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: addi a3, zero, 48 +; RV64IA-NEXT: sub a6, a3, a2 +; RV64IA-NEXT: lui a4, 16 +; RV64IA-NEXT: addiw a4, a4, -1 +; RV64IA-NEXT: sllw a7, a4, a2 ; RV64IA-NEXT: slli a1, a1, 48 ; RV64IA-NEXT: srai a1, a1, 48 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: addi a4, zero, 48 -; RV64IA-NEXT: sub a4, a4, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB93_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aq a5, (a6) -; RV64IA-NEXT: and a3, a5, a7 -; RV64IA-NEXT: mv a2, a5 -; RV64IA-NEXT: sll a3, a3, a4 -; RV64IA-NEXT: sra a3, a3, a4 -; RV64IA-NEXT: bge a3, a1, .LBB93_3 +; RV64IA-NEXT: lr.w.aq a5, (a0) +; RV64IA-NEXT: and a4, a5, a7 +; RV64IA-NEXT: mv a3, a5 +; RV64IA-NEXT: sll a4, a4, a6 +; RV64IA-NEXT: sra a4, a4, a6 +; RV64IA-NEXT: bge a4, a1, .LBB93_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB93_1 Depth=1 -; RV64IA-NEXT: xor a2, a5, a1 -; RV64IA-NEXT: and a2, a2, a7 -; RV64IA-NEXT: xor a2, a5, a2 +; RV64IA-NEXT: xor a3, a5, a1 +; RV64IA-NEXT: and a3, a3, a7 +; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: .LBB93_3: # in Loop: Header=BB93_1 Depth=1 -; RV64IA-NEXT: sc.w.rl a2, a2, (a6) -; RV64IA-NEXT: bnez a2, .LBB93_1 +; RV64IA-NEXT: sc.w.rl a3, a3, (a0) +; RV64IA-NEXT: bnez a3, .LBB93_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a5, a0 +; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: ret %1 = atomicrmw max i16* %a, i16 %b acq_rel ret i16 %1 @@ -7793,33 +7793,33 @@ define i16 @atomicrmw_max_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: lhu a1, 0(a0) -; RV32I-NEXT: slli a0, s2, 16 -; RV32I-NEXT: srai s0, a0, 16 +; RV32I-NEXT: lhu a0, 0(a0) +; RV32I-NEXT: slli a1, a1, 16 +; RV32I-NEXT: srai s0, a1, 16 ; RV32I-NEXT: addi s3, sp, 10 ; RV32I-NEXT: j .LBB94_2 ; RV32I-NEXT: .LBB94_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB94_2 Depth=1 -; RV32I-NEXT: sh a1, 10(sp) -; RV32I-NEXT: addi a3, zero, 5 -; RV32I-NEXT: addi a4, zero, 5 +; RV32I-NEXT: sh a0, 10(sp) ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s3 +; RV32I-NEXT: addi a3, zero, 5 +; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: call __atomic_compare_exchange_2 -; RV32I-NEXT: lh a1, 10(sp) -; RV32I-NEXT: bnez a0, .LBB94_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lh a0, 10(sp) +; RV32I-NEXT: bnez a1, .LBB94_4 ; RV32I-NEXT: .LBB94_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: slli a0, a1, 16 -; RV32I-NEXT: srai a0, a0, 16 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: blt s0, a0, .LBB94_1 +; RV32I-NEXT: slli a1, a0, 16 +; RV32I-NEXT: srai a1, a1, 16 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: blt s0, a1, .LBB94_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB94_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB94_1 ; RV32I-NEXT: .LBB94_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -7830,33 +7830,33 @@ define i16 @atomicrmw_max_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_max_i16_seq_cst: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a7, a3, a0 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: addi a3, zero, 16 +; RV32IA-NEXT: sub a6, a3, a2 +; RV32IA-NEXT: lui a4, 16 +; RV32IA-NEXT: addi a4, a4, -1 +; RV32IA-NEXT: sll a7, a4, a2 ; RV32IA-NEXT: slli a1, a1, 16 ; RV32IA-NEXT: srai a1, a1, 16 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: addi a4, zero, 16 -; RV32IA-NEXT: sub a4, a4, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB94_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aqrl a5, (a6) -; RV32IA-NEXT: and a3, a5, a7 -; RV32IA-NEXT: mv a2, a5 -; RV32IA-NEXT: sll a3, a3, a4 -; RV32IA-NEXT: sra a3, a3, a4 -; RV32IA-NEXT: bge a3, a1, .LBB94_3 +; RV32IA-NEXT: lr.w.aqrl a5, (a0) +; RV32IA-NEXT: and a4, a5, a7 +; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sll a4, a4, a6 +; RV32IA-NEXT: sra a4, a4, a6 +; RV32IA-NEXT: bge a4, a1, .LBB94_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB94_1 Depth=1 -; RV32IA-NEXT: xor a2, a5, a1 -; RV32IA-NEXT: and a2, a2, a7 -; RV32IA-NEXT: xor a2, a5, a2 +; RV32IA-NEXT: xor a3, a5, a1 +; RV32IA-NEXT: and a3, a3, a7 +; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: .LBB94_3: # in Loop: Header=BB94_1 Depth=1 -; RV32IA-NEXT: sc.w.aqrl a2, a2, (a6) -; RV32IA-NEXT: bnez a2, .LBB94_1 +; RV32IA-NEXT: sc.w.aqrl a3, a3, (a0) +; RV32IA-NEXT: bnez a3, .LBB94_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a5, a0 +; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_max_i16_seq_cst: @@ -7869,33 +7869,33 @@ define i16 @atomicrmw_max_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: lhu a1, 0(a0) -; RV64I-NEXT: slli a0, s2, 48 -; RV64I-NEXT: srai s0, a0, 48 +; RV64I-NEXT: lhu a0, 0(a0) +; RV64I-NEXT: slli a1, a1, 48 +; RV64I-NEXT: srai s0, a1, 48 ; RV64I-NEXT: addi s3, sp, 6 ; RV64I-NEXT: j .LBB94_2 ; RV64I-NEXT: .LBB94_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB94_2 Depth=1 -; RV64I-NEXT: sh a1, 6(sp) -; RV64I-NEXT: addi a3, zero, 5 -; RV64I-NEXT: addi a4, zero, 5 +; RV64I-NEXT: sh a0, 6(sp) ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s3 +; RV64I-NEXT: addi a3, zero, 5 +; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: call __atomic_compare_exchange_2 -; RV64I-NEXT: lh a1, 6(sp) -; RV64I-NEXT: bnez a0, .LBB94_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lh a0, 6(sp) +; RV64I-NEXT: bnez a1, .LBB94_4 ; RV64I-NEXT: .LBB94_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: slli a0, a1, 48 -; RV64I-NEXT: srai a0, a0, 48 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: blt s0, a0, .LBB94_1 +; RV64I-NEXT: slli a1, a0, 48 +; RV64I-NEXT: srai a1, a1, 48 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: blt s0, a1, .LBB94_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB94_2 Depth=1 ; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB94_1 ; RV64I-NEXT: .LBB94_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -7906,33 +7906,33 @@ define i16 @atomicrmw_max_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_max_i16_seq_cst: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a7, a3, a0 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: addi a3, zero, 48 +; RV64IA-NEXT: sub a6, a3, a2 +; RV64IA-NEXT: lui a4, 16 +; RV64IA-NEXT: addiw a4, a4, -1 +; RV64IA-NEXT: sllw a7, a4, a2 ; RV64IA-NEXT: slli a1, a1, 48 ; RV64IA-NEXT: srai a1, a1, 48 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: addi a4, zero, 48 -; RV64IA-NEXT: sub a4, a4, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB94_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aqrl a5, (a6) -; RV64IA-NEXT: and a3, a5, a7 -; RV64IA-NEXT: mv a2, a5 -; RV64IA-NEXT: sll a3, a3, a4 -; RV64IA-NEXT: sra a3, a3, a4 -; RV64IA-NEXT: bge a3, a1, .LBB94_3 +; RV64IA-NEXT: lr.w.aqrl a5, (a0) +; RV64IA-NEXT: and a4, a5, a7 +; RV64IA-NEXT: mv a3, a5 +; RV64IA-NEXT: sll a4, a4, a6 +; RV64IA-NEXT: sra a4, a4, a6 +; RV64IA-NEXT: bge a4, a1, .LBB94_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB94_1 Depth=1 -; RV64IA-NEXT: xor a2, a5, a1 -; RV64IA-NEXT: and a2, a2, a7 -; RV64IA-NEXT: xor a2, a5, a2 +; RV64IA-NEXT: xor a3, a5, a1 +; RV64IA-NEXT: and a3, a3, a7 +; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: .LBB94_3: # in Loop: Header=BB94_1 Depth=1 -; RV64IA-NEXT: sc.w.aqrl a2, a2, (a6) -; RV64IA-NEXT: bnez a2, .LBB94_1 +; RV64IA-NEXT: sc.w.aqrl a3, a3, (a0) +; RV64IA-NEXT: bnez a3, .LBB94_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a5, a0 +; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: ret %1 = atomicrmw max i16* %a, i16 %b seq_cst ret i16 %1 @@ -7949,33 +7949,33 @@ define i16 @atomicrmw_min_i16_monotonic(i16 *%a, i16 %b) nounwind { ; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: lhu a1, 0(a0) -; RV32I-NEXT: slli a0, s2, 16 -; RV32I-NEXT: srai s0, a0, 16 +; RV32I-NEXT: lhu a0, 0(a0) +; RV32I-NEXT: slli a1, a1, 16 +; RV32I-NEXT: srai s0, a1, 16 ; RV32I-NEXT: addi s3, sp, 10 ; RV32I-NEXT: j .LBB95_2 ; RV32I-NEXT: .LBB95_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB95_2 Depth=1 -; RV32I-NEXT: sh a1, 10(sp) +; RV32I-NEXT: sh a0, 10(sp) ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: call __atomic_compare_exchange_2 -; RV32I-NEXT: lh a1, 10(sp) -; RV32I-NEXT: bnez a0, .LBB95_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lh a0, 10(sp) +; RV32I-NEXT: bnez a1, .LBB95_4 ; RV32I-NEXT: .LBB95_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: slli a0, a1, 16 -; RV32I-NEXT: srai a0, a0, 16 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: bge s0, a0, .LBB95_1 +; RV32I-NEXT: slli a1, a0, 16 +; RV32I-NEXT: srai a1, a1, 16 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: bge s0, a1, .LBB95_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB95_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB95_1 ; RV32I-NEXT: .LBB95_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -7986,33 +7986,33 @@ define i16 @atomicrmw_min_i16_monotonic(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_min_i16_monotonic: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a7, a3, a0 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: addi a3, zero, 16 +; RV32IA-NEXT: sub a6, a3, a2 +; RV32IA-NEXT: lui a4, 16 +; RV32IA-NEXT: addi a4, a4, -1 +; RV32IA-NEXT: sll a7, a4, a2 ; RV32IA-NEXT: slli a1, a1, 16 ; RV32IA-NEXT: srai a1, a1, 16 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: addi a4, zero, 16 -; RV32IA-NEXT: sub a4, a4, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB95_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a5, (a6) -; RV32IA-NEXT: and a3, a5, a7 -; RV32IA-NEXT: mv a2, a5 -; RV32IA-NEXT: sll a3, a3, a4 -; RV32IA-NEXT: sra a3, a3, a4 -; RV32IA-NEXT: bge a1, a3, .LBB95_3 +; RV32IA-NEXT: lr.w a5, (a0) +; RV32IA-NEXT: and a4, a5, a7 +; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sll a4, a4, a6 +; RV32IA-NEXT: sra a4, a4, a6 +; RV32IA-NEXT: bge a1, a4, .LBB95_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB95_1 Depth=1 -; RV32IA-NEXT: xor a2, a5, a1 -; RV32IA-NEXT: and a2, a2, a7 -; RV32IA-NEXT: xor a2, a5, a2 +; RV32IA-NEXT: xor a3, a5, a1 +; RV32IA-NEXT: and a3, a3, a7 +; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: .LBB95_3: # in Loop: Header=BB95_1 Depth=1 -; RV32IA-NEXT: sc.w a2, a2, (a6) -; RV32IA-NEXT: bnez a2, .LBB95_1 +; RV32IA-NEXT: sc.w a3, a3, (a0) +; RV32IA-NEXT: bnez a3, .LBB95_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a5, a0 +; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_min_i16_monotonic: @@ -8025,33 +8025,33 @@ define i16 @atomicrmw_min_i16_monotonic(i16 *%a, i16 %b) nounwind { ; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: lhu a1, 0(a0) -; RV64I-NEXT: slli a0, s2, 48 -; RV64I-NEXT: srai s0, a0, 48 +; RV64I-NEXT: lhu a0, 0(a0) +; RV64I-NEXT: slli a1, a1, 48 +; RV64I-NEXT: srai s0, a1, 48 ; RV64I-NEXT: addi s3, sp, 6 ; RV64I-NEXT: j .LBB95_2 ; RV64I-NEXT: .LBB95_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB95_2 Depth=1 -; RV64I-NEXT: sh a1, 6(sp) +; RV64I-NEXT: sh a0, 6(sp) ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: call __atomic_compare_exchange_2 -; RV64I-NEXT: lh a1, 6(sp) -; RV64I-NEXT: bnez a0, .LBB95_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lh a0, 6(sp) +; RV64I-NEXT: bnez a1, .LBB95_4 ; RV64I-NEXT: .LBB95_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: slli a0, a1, 48 -; RV64I-NEXT: srai a0, a0, 48 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: bge s0, a0, .LBB95_1 +; RV64I-NEXT: slli a1, a0, 48 +; RV64I-NEXT: srai a1, a1, 48 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bge s0, a1, .LBB95_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB95_2 Depth=1 ; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB95_1 ; RV64I-NEXT: .LBB95_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -8062,33 +8062,33 @@ define i16 @atomicrmw_min_i16_monotonic(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_min_i16_monotonic: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a7, a3, a0 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: addi a3, zero, 48 +; RV64IA-NEXT: sub a6, a3, a2 +; RV64IA-NEXT: lui a4, 16 +; RV64IA-NEXT: addiw a4, a4, -1 +; RV64IA-NEXT: sllw a7, a4, a2 ; RV64IA-NEXT: slli a1, a1, 48 ; RV64IA-NEXT: srai a1, a1, 48 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: addi a4, zero, 48 -; RV64IA-NEXT: sub a4, a4, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB95_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w a5, (a6) -; RV64IA-NEXT: and a3, a5, a7 -; RV64IA-NEXT: mv a2, a5 -; RV64IA-NEXT: sll a3, a3, a4 -; RV64IA-NEXT: sra a3, a3, a4 -; RV64IA-NEXT: bge a1, a3, .LBB95_3 +; RV64IA-NEXT: lr.w a5, (a0) +; RV64IA-NEXT: and a4, a5, a7 +; RV64IA-NEXT: mv a3, a5 +; RV64IA-NEXT: sll a4, a4, a6 +; RV64IA-NEXT: sra a4, a4, a6 +; RV64IA-NEXT: bge a1, a4, .LBB95_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB95_1 Depth=1 -; RV64IA-NEXT: xor a2, a5, a1 -; RV64IA-NEXT: and a2, a2, a7 -; RV64IA-NEXT: xor a2, a5, a2 +; RV64IA-NEXT: xor a3, a5, a1 +; RV64IA-NEXT: and a3, a3, a7 +; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: .LBB95_3: # in Loop: Header=BB95_1 Depth=1 -; RV64IA-NEXT: sc.w a2, a2, (a6) -; RV64IA-NEXT: bnez a2, .LBB95_1 +; RV64IA-NEXT: sc.w a3, a3, (a0) +; RV64IA-NEXT: bnez a3, .LBB95_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a5, a0 +; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: ret %1 = atomicrmw min i16* %a, i16 %b monotonic ret i16 %1 @@ -8105,33 +8105,33 @@ define i16 @atomicrmw_min_i16_acquire(i16 *%a, i16 %b) nounwind { ; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: lhu a1, 0(a0) -; RV32I-NEXT: slli a0, s2, 16 -; RV32I-NEXT: srai s0, a0, 16 +; RV32I-NEXT: lhu a0, 0(a0) +; RV32I-NEXT: slli a1, a1, 16 +; RV32I-NEXT: srai s0, a1, 16 ; RV32I-NEXT: addi s3, sp, 10 ; RV32I-NEXT: j .LBB96_2 ; RV32I-NEXT: .LBB96_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB96_2 Depth=1 -; RV32I-NEXT: sh a1, 10(sp) -; RV32I-NEXT: addi a3, zero, 2 -; RV32I-NEXT: addi a4, zero, 2 +; RV32I-NEXT: sh a0, 10(sp) ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s3 +; RV32I-NEXT: addi a3, zero, 2 +; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: call __atomic_compare_exchange_2 -; RV32I-NEXT: lh a1, 10(sp) -; RV32I-NEXT: bnez a0, .LBB96_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lh a0, 10(sp) +; RV32I-NEXT: bnez a1, .LBB96_4 ; RV32I-NEXT: .LBB96_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: slli a0, a1, 16 -; RV32I-NEXT: srai a0, a0, 16 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: bge s0, a0, .LBB96_1 +; RV32I-NEXT: slli a1, a0, 16 +; RV32I-NEXT: srai a1, a1, 16 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: bge s0, a1, .LBB96_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB96_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB96_1 ; RV32I-NEXT: .LBB96_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -8142,33 +8142,33 @@ define i16 @atomicrmw_min_i16_acquire(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_min_i16_acquire: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a7, a3, a0 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: addi a3, zero, 16 +; RV32IA-NEXT: sub a6, a3, a2 +; RV32IA-NEXT: lui a4, 16 +; RV32IA-NEXT: addi a4, a4, -1 +; RV32IA-NEXT: sll a7, a4, a2 ; RV32IA-NEXT: slli a1, a1, 16 ; RV32IA-NEXT: srai a1, a1, 16 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: addi a4, zero, 16 -; RV32IA-NEXT: sub a4, a4, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aq a5, (a6) -; RV32IA-NEXT: and a3, a5, a7 -; RV32IA-NEXT: mv a2, a5 -; RV32IA-NEXT: sll a3, a3, a4 -; RV32IA-NEXT: sra a3, a3, a4 -; RV32IA-NEXT: bge a1, a3, .LBB96_3 +; RV32IA-NEXT: lr.w.aq a5, (a0) +; RV32IA-NEXT: and a4, a5, a7 +; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sll a4, a4, a6 +; RV32IA-NEXT: sra a4, a4, a6 +; RV32IA-NEXT: bge a1, a4, .LBB96_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB96_1 Depth=1 -; RV32IA-NEXT: xor a2, a5, a1 -; RV32IA-NEXT: and a2, a2, a7 -; RV32IA-NEXT: xor a2, a5, a2 +; RV32IA-NEXT: xor a3, a5, a1 +; RV32IA-NEXT: and a3, a3, a7 +; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: .LBB96_3: # in Loop: Header=BB96_1 Depth=1 -; RV32IA-NEXT: sc.w a2, a2, (a6) -; RV32IA-NEXT: bnez a2, .LBB96_1 +; RV32IA-NEXT: sc.w a3, a3, (a0) +; RV32IA-NEXT: bnez a3, .LBB96_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a5, a0 +; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_min_i16_acquire: @@ -8181,33 +8181,33 @@ define i16 @atomicrmw_min_i16_acquire(i16 *%a, i16 %b) nounwind { ; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: lhu a1, 0(a0) -; RV64I-NEXT: slli a0, s2, 48 -; RV64I-NEXT: srai s0, a0, 48 +; RV64I-NEXT: lhu a0, 0(a0) +; RV64I-NEXT: slli a1, a1, 48 +; RV64I-NEXT: srai s0, a1, 48 ; RV64I-NEXT: addi s3, sp, 6 ; RV64I-NEXT: j .LBB96_2 ; RV64I-NEXT: .LBB96_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB96_2 Depth=1 -; RV64I-NEXT: sh a1, 6(sp) -; RV64I-NEXT: addi a3, zero, 2 -; RV64I-NEXT: addi a4, zero, 2 +; RV64I-NEXT: sh a0, 6(sp) ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s3 +; RV64I-NEXT: addi a3, zero, 2 +; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: call __atomic_compare_exchange_2 -; RV64I-NEXT: lh a1, 6(sp) -; RV64I-NEXT: bnez a0, .LBB96_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lh a0, 6(sp) +; RV64I-NEXT: bnez a1, .LBB96_4 ; RV64I-NEXT: .LBB96_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: slli a0, a1, 48 -; RV64I-NEXT: srai a0, a0, 48 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: bge s0, a0, .LBB96_1 +; RV64I-NEXT: slli a1, a0, 48 +; RV64I-NEXT: srai a1, a1, 48 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bge s0, a1, .LBB96_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB96_2 Depth=1 ; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB96_1 ; RV64I-NEXT: .LBB96_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -8218,33 +8218,33 @@ define i16 @atomicrmw_min_i16_acquire(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_min_i16_acquire: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a7, a3, a0 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: addi a3, zero, 48 +; RV64IA-NEXT: sub a6, a3, a2 +; RV64IA-NEXT: lui a4, 16 +; RV64IA-NEXT: addiw a4, a4, -1 +; RV64IA-NEXT: sllw a7, a4, a2 ; RV64IA-NEXT: slli a1, a1, 48 ; RV64IA-NEXT: srai a1, a1, 48 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: addi a4, zero, 48 -; RV64IA-NEXT: sub a4, a4, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aq a5, (a6) -; RV64IA-NEXT: and a3, a5, a7 -; RV64IA-NEXT: mv a2, a5 -; RV64IA-NEXT: sll a3, a3, a4 -; RV64IA-NEXT: sra a3, a3, a4 -; RV64IA-NEXT: bge a1, a3, .LBB96_3 +; RV64IA-NEXT: lr.w.aq a5, (a0) +; RV64IA-NEXT: and a4, a5, a7 +; RV64IA-NEXT: mv a3, a5 +; RV64IA-NEXT: sll a4, a4, a6 +; RV64IA-NEXT: sra a4, a4, a6 +; RV64IA-NEXT: bge a1, a4, .LBB96_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB96_1 Depth=1 -; RV64IA-NEXT: xor a2, a5, a1 -; RV64IA-NEXT: and a2, a2, a7 -; RV64IA-NEXT: xor a2, a5, a2 +; RV64IA-NEXT: xor a3, a5, a1 +; RV64IA-NEXT: and a3, a3, a7 +; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: .LBB96_3: # in Loop: Header=BB96_1 Depth=1 -; RV64IA-NEXT: sc.w a2, a2, (a6) -; RV64IA-NEXT: bnez a2, .LBB96_1 +; RV64IA-NEXT: sc.w a3, a3, (a0) +; RV64IA-NEXT: bnez a3, .LBB96_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a5, a0 +; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: ret %1 = atomicrmw min i16* %a, i16 %b acquire ret i16 %1 @@ -8261,33 +8261,33 @@ define i16 @atomicrmw_min_i16_release(i16 *%a, i16 %b) nounwind { ; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: lhu a1, 0(a0) -; RV32I-NEXT: slli a0, s2, 16 -; RV32I-NEXT: srai s0, a0, 16 +; RV32I-NEXT: lhu a0, 0(a0) +; RV32I-NEXT: slli a1, a1, 16 +; RV32I-NEXT: srai s0, a1, 16 ; RV32I-NEXT: addi s3, sp, 10 ; RV32I-NEXT: j .LBB97_2 ; RV32I-NEXT: .LBB97_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB97_2 Depth=1 -; RV32I-NEXT: sh a1, 10(sp) -; RV32I-NEXT: addi a3, zero, 3 +; RV32I-NEXT: sh a0, 10(sp) ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s3 +; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: call __atomic_compare_exchange_2 -; RV32I-NEXT: lh a1, 10(sp) -; RV32I-NEXT: bnez a0, .LBB97_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lh a0, 10(sp) +; RV32I-NEXT: bnez a1, .LBB97_4 ; RV32I-NEXT: .LBB97_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: slli a0, a1, 16 -; RV32I-NEXT: srai a0, a0, 16 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: bge s0, a0, .LBB97_1 +; RV32I-NEXT: slli a1, a0, 16 +; RV32I-NEXT: srai a1, a1, 16 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: bge s0, a1, .LBB97_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB97_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB97_1 ; RV32I-NEXT: .LBB97_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -8298,33 +8298,33 @@ define i16 @atomicrmw_min_i16_release(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_min_i16_release: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a7, a3, a0 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: addi a3, zero, 16 +; RV32IA-NEXT: sub a6, a3, a2 +; RV32IA-NEXT: lui a4, 16 +; RV32IA-NEXT: addi a4, a4, -1 +; RV32IA-NEXT: sll a7, a4, a2 ; RV32IA-NEXT: slli a1, a1, 16 ; RV32IA-NEXT: srai a1, a1, 16 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: addi a4, zero, 16 -; RV32IA-NEXT: sub a4, a4, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a5, (a6) -; RV32IA-NEXT: and a3, a5, a7 -; RV32IA-NEXT: mv a2, a5 -; RV32IA-NEXT: sll a3, a3, a4 -; RV32IA-NEXT: sra a3, a3, a4 -; RV32IA-NEXT: bge a1, a3, .LBB97_3 +; RV32IA-NEXT: lr.w a5, (a0) +; RV32IA-NEXT: and a4, a5, a7 +; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sll a4, a4, a6 +; RV32IA-NEXT: sra a4, a4, a6 +; RV32IA-NEXT: bge a1, a4, .LBB97_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB97_1 Depth=1 -; RV32IA-NEXT: xor a2, a5, a1 -; RV32IA-NEXT: and a2, a2, a7 -; RV32IA-NEXT: xor a2, a5, a2 +; RV32IA-NEXT: xor a3, a5, a1 +; RV32IA-NEXT: and a3, a3, a7 +; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: .LBB97_3: # in Loop: Header=BB97_1 Depth=1 -; RV32IA-NEXT: sc.w.rl a2, a2, (a6) -; RV32IA-NEXT: bnez a2, .LBB97_1 +; RV32IA-NEXT: sc.w.rl a3, a3, (a0) +; RV32IA-NEXT: bnez a3, .LBB97_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a5, a0 +; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_min_i16_release: @@ -8337,33 +8337,33 @@ define i16 @atomicrmw_min_i16_release(i16 *%a, i16 %b) nounwind { ; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: lhu a1, 0(a0) -; RV64I-NEXT: slli a0, s2, 48 -; RV64I-NEXT: srai s0, a0, 48 +; RV64I-NEXT: lhu a0, 0(a0) +; RV64I-NEXT: slli a1, a1, 48 +; RV64I-NEXT: srai s0, a1, 48 ; RV64I-NEXT: addi s3, sp, 6 ; RV64I-NEXT: j .LBB97_2 ; RV64I-NEXT: .LBB97_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB97_2 Depth=1 -; RV64I-NEXT: sh a1, 6(sp) -; RV64I-NEXT: addi a3, zero, 3 +; RV64I-NEXT: sh a0, 6(sp) ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s3 +; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: call __atomic_compare_exchange_2 -; RV64I-NEXT: lh a1, 6(sp) -; RV64I-NEXT: bnez a0, .LBB97_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lh a0, 6(sp) +; RV64I-NEXT: bnez a1, .LBB97_4 ; RV64I-NEXT: .LBB97_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: slli a0, a1, 48 -; RV64I-NEXT: srai a0, a0, 48 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: bge s0, a0, .LBB97_1 +; RV64I-NEXT: slli a1, a0, 48 +; RV64I-NEXT: srai a1, a1, 48 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bge s0, a1, .LBB97_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB97_2 Depth=1 ; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB97_1 ; RV64I-NEXT: .LBB97_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -8374,33 +8374,33 @@ define i16 @atomicrmw_min_i16_release(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_min_i16_release: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a7, a3, a0 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: addi a3, zero, 48 +; RV64IA-NEXT: sub a6, a3, a2 +; RV64IA-NEXT: lui a4, 16 +; RV64IA-NEXT: addiw a4, a4, -1 +; RV64IA-NEXT: sllw a7, a4, a2 ; RV64IA-NEXT: slli a1, a1, 48 ; RV64IA-NEXT: srai a1, a1, 48 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: addi a4, zero, 48 -; RV64IA-NEXT: sub a4, a4, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w a5, (a6) -; RV64IA-NEXT: and a3, a5, a7 -; RV64IA-NEXT: mv a2, a5 -; RV64IA-NEXT: sll a3, a3, a4 -; RV64IA-NEXT: sra a3, a3, a4 -; RV64IA-NEXT: bge a1, a3, .LBB97_3 +; RV64IA-NEXT: lr.w a5, (a0) +; RV64IA-NEXT: and a4, a5, a7 +; RV64IA-NEXT: mv a3, a5 +; RV64IA-NEXT: sll a4, a4, a6 +; RV64IA-NEXT: sra a4, a4, a6 +; RV64IA-NEXT: bge a1, a4, .LBB97_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB97_1 Depth=1 -; RV64IA-NEXT: xor a2, a5, a1 -; RV64IA-NEXT: and a2, a2, a7 -; RV64IA-NEXT: xor a2, a5, a2 +; RV64IA-NEXT: xor a3, a5, a1 +; RV64IA-NEXT: and a3, a3, a7 +; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: .LBB97_3: # in Loop: Header=BB97_1 Depth=1 -; RV64IA-NEXT: sc.w.rl a2, a2, (a6) -; RV64IA-NEXT: bnez a2, .LBB97_1 +; RV64IA-NEXT: sc.w.rl a3, a3, (a0) +; RV64IA-NEXT: bnez a3, .LBB97_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a5, a0 +; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: ret %1 = atomicrmw min i16* %a, i16 %b release ret i16 %1 @@ -8417,33 +8417,33 @@ define i16 @atomicrmw_min_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: lhu a1, 0(a0) -; RV32I-NEXT: slli a0, s2, 16 -; RV32I-NEXT: srai s0, a0, 16 +; RV32I-NEXT: lhu a0, 0(a0) +; RV32I-NEXT: slli a1, a1, 16 +; RV32I-NEXT: srai s0, a1, 16 ; RV32I-NEXT: addi s3, sp, 10 ; RV32I-NEXT: j .LBB98_2 ; RV32I-NEXT: .LBB98_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB98_2 Depth=1 -; RV32I-NEXT: sh a1, 10(sp) -; RV32I-NEXT: addi a3, zero, 4 -; RV32I-NEXT: addi a4, zero, 2 +; RV32I-NEXT: sh a0, 10(sp) ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s3 +; RV32I-NEXT: addi a3, zero, 4 +; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: call __atomic_compare_exchange_2 -; RV32I-NEXT: lh a1, 10(sp) -; RV32I-NEXT: bnez a0, .LBB98_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lh a0, 10(sp) +; RV32I-NEXT: bnez a1, .LBB98_4 ; RV32I-NEXT: .LBB98_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: slli a0, a1, 16 -; RV32I-NEXT: srai a0, a0, 16 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: bge s0, a0, .LBB98_1 +; RV32I-NEXT: slli a1, a0, 16 +; RV32I-NEXT: srai a1, a1, 16 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: bge s0, a1, .LBB98_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB98_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB98_1 ; RV32I-NEXT: .LBB98_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -8454,33 +8454,33 @@ define i16 @atomicrmw_min_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_min_i16_acq_rel: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a7, a3, a0 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: addi a3, zero, 16 +; RV32IA-NEXT: sub a6, a3, a2 +; RV32IA-NEXT: lui a4, 16 +; RV32IA-NEXT: addi a4, a4, -1 +; RV32IA-NEXT: sll a7, a4, a2 ; RV32IA-NEXT: slli a1, a1, 16 ; RV32IA-NEXT: srai a1, a1, 16 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: addi a4, zero, 16 -; RV32IA-NEXT: sub a4, a4, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aq a5, (a6) -; RV32IA-NEXT: and a3, a5, a7 -; RV32IA-NEXT: mv a2, a5 -; RV32IA-NEXT: sll a3, a3, a4 -; RV32IA-NEXT: sra a3, a3, a4 -; RV32IA-NEXT: bge a1, a3, .LBB98_3 +; RV32IA-NEXT: lr.w.aq a5, (a0) +; RV32IA-NEXT: and a4, a5, a7 +; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sll a4, a4, a6 +; RV32IA-NEXT: sra a4, a4, a6 +; RV32IA-NEXT: bge a1, a4, .LBB98_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB98_1 Depth=1 -; RV32IA-NEXT: xor a2, a5, a1 -; RV32IA-NEXT: and a2, a2, a7 -; RV32IA-NEXT: xor a2, a5, a2 +; RV32IA-NEXT: xor a3, a5, a1 +; RV32IA-NEXT: and a3, a3, a7 +; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: .LBB98_3: # in Loop: Header=BB98_1 Depth=1 -; RV32IA-NEXT: sc.w.rl a2, a2, (a6) -; RV32IA-NEXT: bnez a2, .LBB98_1 +; RV32IA-NEXT: sc.w.rl a3, a3, (a0) +; RV32IA-NEXT: bnez a3, .LBB98_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a5, a0 +; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_min_i16_acq_rel: @@ -8493,33 +8493,33 @@ define i16 @atomicrmw_min_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: lhu a1, 0(a0) -; RV64I-NEXT: slli a0, s2, 48 -; RV64I-NEXT: srai s0, a0, 48 +; RV64I-NEXT: lhu a0, 0(a0) +; RV64I-NEXT: slli a1, a1, 48 +; RV64I-NEXT: srai s0, a1, 48 ; RV64I-NEXT: addi s3, sp, 6 ; RV64I-NEXT: j .LBB98_2 ; RV64I-NEXT: .LBB98_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB98_2 Depth=1 -; RV64I-NEXT: sh a1, 6(sp) -; RV64I-NEXT: addi a3, zero, 4 -; RV64I-NEXT: addi a4, zero, 2 +; RV64I-NEXT: sh a0, 6(sp) ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s3 +; RV64I-NEXT: addi a3, zero, 4 +; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: call __atomic_compare_exchange_2 -; RV64I-NEXT: lh a1, 6(sp) -; RV64I-NEXT: bnez a0, .LBB98_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lh a0, 6(sp) +; RV64I-NEXT: bnez a1, .LBB98_4 ; RV64I-NEXT: .LBB98_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: slli a0, a1, 48 -; RV64I-NEXT: srai a0, a0, 48 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: bge s0, a0, .LBB98_1 +; RV64I-NEXT: slli a1, a0, 48 +; RV64I-NEXT: srai a1, a1, 48 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bge s0, a1, .LBB98_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB98_2 Depth=1 ; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB98_1 ; RV64I-NEXT: .LBB98_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -8530,33 +8530,33 @@ define i16 @atomicrmw_min_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_min_i16_acq_rel: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a7, a3, a0 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: addi a3, zero, 48 +; RV64IA-NEXT: sub a6, a3, a2 +; RV64IA-NEXT: lui a4, 16 +; RV64IA-NEXT: addiw a4, a4, -1 +; RV64IA-NEXT: sllw a7, a4, a2 ; RV64IA-NEXT: slli a1, a1, 48 ; RV64IA-NEXT: srai a1, a1, 48 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: addi a4, zero, 48 -; RV64IA-NEXT: sub a4, a4, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aq a5, (a6) -; RV64IA-NEXT: and a3, a5, a7 -; RV64IA-NEXT: mv a2, a5 -; RV64IA-NEXT: sll a3, a3, a4 -; RV64IA-NEXT: sra a3, a3, a4 -; RV64IA-NEXT: bge a1, a3, .LBB98_3 +; RV64IA-NEXT: lr.w.aq a5, (a0) +; RV64IA-NEXT: and a4, a5, a7 +; RV64IA-NEXT: mv a3, a5 +; RV64IA-NEXT: sll a4, a4, a6 +; RV64IA-NEXT: sra a4, a4, a6 +; RV64IA-NEXT: bge a1, a4, .LBB98_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB98_1 Depth=1 -; RV64IA-NEXT: xor a2, a5, a1 -; RV64IA-NEXT: and a2, a2, a7 -; RV64IA-NEXT: xor a2, a5, a2 +; RV64IA-NEXT: xor a3, a5, a1 +; RV64IA-NEXT: and a3, a3, a7 +; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: .LBB98_3: # in Loop: Header=BB98_1 Depth=1 -; RV64IA-NEXT: sc.w.rl a2, a2, (a6) -; RV64IA-NEXT: bnez a2, .LBB98_1 +; RV64IA-NEXT: sc.w.rl a3, a3, (a0) +; RV64IA-NEXT: bnez a3, .LBB98_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a5, a0 +; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: ret %1 = atomicrmw min i16* %a, i16 %b acq_rel ret i16 %1 @@ -8573,33 +8573,33 @@ define i16 @atomicrmw_min_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: lhu a1, 0(a0) -; RV32I-NEXT: slli a0, s2, 16 -; RV32I-NEXT: srai s0, a0, 16 +; RV32I-NEXT: lhu a0, 0(a0) +; RV32I-NEXT: slli a1, a1, 16 +; RV32I-NEXT: srai s0, a1, 16 ; RV32I-NEXT: addi s3, sp, 10 ; RV32I-NEXT: j .LBB99_2 ; RV32I-NEXT: .LBB99_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB99_2 Depth=1 -; RV32I-NEXT: sh a1, 10(sp) -; RV32I-NEXT: addi a3, zero, 5 -; RV32I-NEXT: addi a4, zero, 5 +; RV32I-NEXT: sh a0, 10(sp) ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s3 +; RV32I-NEXT: addi a3, zero, 5 +; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: call __atomic_compare_exchange_2 -; RV32I-NEXT: lh a1, 10(sp) -; RV32I-NEXT: bnez a0, .LBB99_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lh a0, 10(sp) +; RV32I-NEXT: bnez a1, .LBB99_4 ; RV32I-NEXT: .LBB99_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: slli a0, a1, 16 -; RV32I-NEXT: srai a0, a0, 16 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: bge s0, a0, .LBB99_1 +; RV32I-NEXT: slli a1, a0, 16 +; RV32I-NEXT: srai a1, a1, 16 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: bge s0, a1, .LBB99_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB99_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB99_1 ; RV32I-NEXT: .LBB99_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -8610,33 +8610,33 @@ define i16 @atomicrmw_min_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_min_i16_seq_cst: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a7, a3, a0 +; RV32IA-NEXT: slli a2, a0, 3 +; RV32IA-NEXT: andi a2, a2, 24 +; RV32IA-NEXT: addi a3, zero, 16 +; RV32IA-NEXT: sub a6, a3, a2 +; RV32IA-NEXT: lui a4, 16 +; RV32IA-NEXT: addi a4, a4, -1 +; RV32IA-NEXT: sll a7, a4, a2 ; RV32IA-NEXT: slli a1, a1, 16 ; RV32IA-NEXT: srai a1, a1, 16 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: addi a4, zero, 16 -; RV32IA-NEXT: sub a4, a4, a0 +; RV32IA-NEXT: sll a1, a1, a2 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB99_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aqrl a5, (a6) -; RV32IA-NEXT: and a3, a5, a7 -; RV32IA-NEXT: mv a2, a5 -; RV32IA-NEXT: sll a3, a3, a4 -; RV32IA-NEXT: sra a3, a3, a4 -; RV32IA-NEXT: bge a1, a3, .LBB99_3 +; RV32IA-NEXT: lr.w.aqrl a5, (a0) +; RV32IA-NEXT: and a4, a5, a7 +; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sll a4, a4, a6 +; RV32IA-NEXT: sra a4, a4, a6 +; RV32IA-NEXT: bge a1, a4, .LBB99_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB99_1 Depth=1 -; RV32IA-NEXT: xor a2, a5, a1 -; RV32IA-NEXT: and a2, a2, a7 -; RV32IA-NEXT: xor a2, a5, a2 +; RV32IA-NEXT: xor a3, a5, a1 +; RV32IA-NEXT: and a3, a3, a7 +; RV32IA-NEXT: xor a3, a5, a3 ; RV32IA-NEXT: .LBB99_3: # in Loop: Header=BB99_1 Depth=1 -; RV32IA-NEXT: sc.w.aqrl a2, a2, (a6) -; RV32IA-NEXT: bnez a2, .LBB99_1 +; RV32IA-NEXT: sc.w.aqrl a3, a3, (a0) +; RV32IA-NEXT: bnez a3, .LBB99_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a5, a0 +; RV32IA-NEXT: srl a0, a5, a2 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_min_i16_seq_cst: @@ -8649,33 +8649,33 @@ define i16 @atomicrmw_min_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: lhu a1, 0(a0) -; RV64I-NEXT: slli a0, s2, 48 -; RV64I-NEXT: srai s0, a0, 48 +; RV64I-NEXT: lhu a0, 0(a0) +; RV64I-NEXT: slli a1, a1, 48 +; RV64I-NEXT: srai s0, a1, 48 ; RV64I-NEXT: addi s3, sp, 6 ; RV64I-NEXT: j .LBB99_2 ; RV64I-NEXT: .LBB99_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB99_2 Depth=1 -; RV64I-NEXT: sh a1, 6(sp) -; RV64I-NEXT: addi a3, zero, 5 -; RV64I-NEXT: addi a4, zero, 5 +; RV64I-NEXT: sh a0, 6(sp) ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s3 +; RV64I-NEXT: addi a3, zero, 5 +; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: call __atomic_compare_exchange_2 -; RV64I-NEXT: lh a1, 6(sp) -; RV64I-NEXT: bnez a0, .LBB99_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lh a0, 6(sp) +; RV64I-NEXT: bnez a1, .LBB99_4 ; RV64I-NEXT: .LBB99_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: slli a0, a1, 48 -; RV64I-NEXT: srai a0, a0, 48 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: bge s0, a0, .LBB99_1 +; RV64I-NEXT: slli a1, a0, 48 +; RV64I-NEXT: srai a1, a1, 48 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bge s0, a1, .LBB99_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB99_2 Depth=1 ; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB99_1 ; RV64I-NEXT: .LBB99_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -8686,33 +8686,33 @@ define i16 @atomicrmw_min_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_min_i16_seq_cst: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a7, a3, a0 +; RV64IA-NEXT: slli a2, a0, 3 +; RV64IA-NEXT: andi a2, a2, 24 +; RV64IA-NEXT: addi a3, zero, 48 +; RV64IA-NEXT: sub a6, a3, a2 +; RV64IA-NEXT: lui a4, 16 +; RV64IA-NEXT: addiw a4, a4, -1 +; RV64IA-NEXT: sllw a7, a4, a2 ; RV64IA-NEXT: slli a1, a1, 48 ; RV64IA-NEXT: srai a1, a1, 48 -; RV64IA-NEXT: sllw a1, a1, a0 -; RV64IA-NEXT: addi a4, zero, 48 -; RV64IA-NEXT: sub a4, a4, a0 +; RV64IA-NEXT: sllw a1, a1, a2 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB99_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aqrl a5, (a6) -; RV64IA-NEXT: and a3, a5, a7 -; RV64IA-NEXT: mv a2, a5 -; RV64IA-NEXT: sll a3, a3, a4 -; RV64IA-NEXT: sra a3, a3, a4 -; RV64IA-NEXT: bge a1, a3, .LBB99_3 +; RV64IA-NEXT: lr.w.aqrl a5, (a0) +; RV64IA-NEXT: and a4, a5, a7 +; RV64IA-NEXT: mv a3, a5 +; RV64IA-NEXT: sll a4, a4, a6 +; RV64IA-NEXT: sra a4, a4, a6 +; RV64IA-NEXT: bge a1, a4, .LBB99_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB99_1 Depth=1 -; RV64IA-NEXT: xor a2, a5, a1 -; RV64IA-NEXT: and a2, a2, a7 -; RV64IA-NEXT: xor a2, a5, a2 +; RV64IA-NEXT: xor a3, a5, a1 +; RV64IA-NEXT: and a3, a3, a7 +; RV64IA-NEXT: xor a3, a5, a3 ; RV64IA-NEXT: .LBB99_3: # in Loop: Header=BB99_1 Depth=1 -; RV64IA-NEXT: sc.w.aqrl a2, a2, (a6) -; RV64IA-NEXT: bnez a2, .LBB99_1 +; RV64IA-NEXT: sc.w.aqrl a3, a3, (a0) +; RV64IA-NEXT: bnez a3, .LBB99_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a5, a0 +; RV64IA-NEXT: srlw a0, a5, a2 ; RV64IA-NEXT: ret %1 = atomicrmw min i16* %a, i16 %b seq_cst ret i16 %1 @@ -8730,33 +8730,33 @@ define i16 @atomicrmw_umax_i16_monotonic(i16 *%a, i16 %b) nounwind { ; RV32I-NEXT: sw s4, 8(sp) ; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s4, a0 -; RV32I-NEXT: lhu a1, 0(a0) -; RV32I-NEXT: lui a0, 16 -; RV32I-NEXT: addi s0, a0, -1 +; RV32I-NEXT: lhu a0, 0(a0) +; RV32I-NEXT: lui a1, 16 +; RV32I-NEXT: addi s0, a1, -1 ; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: addi s3, sp, 6 ; RV32I-NEXT: j .LBB100_2 ; RV32I-NEXT: .LBB100_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB100_2 Depth=1 -; RV32I-NEXT: sh a1, 6(sp) +; RV32I-NEXT: sh a0, 6(sp) ; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: call __atomic_compare_exchange_2 -; RV32I-NEXT: lh a1, 6(sp) -; RV32I-NEXT: bnez a0, .LBB100_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lh a0, 6(sp) +; RV32I-NEXT: bnez a1, .LBB100_4 ; RV32I-NEXT: .LBB100_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: and a0, a1, s0 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: bltu s1, a0, .LBB100_1 +; RV32I-NEXT: and a1, a0, s0 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: bltu s1, a1, .LBB100_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB100_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB100_1 ; RV32I-NEXT: .LBB100_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: lw s4, 8(sp) ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) @@ -8768,28 +8768,28 @@ define i16 @atomicrmw_umax_i16_monotonic(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_umax_i16_monotonic: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a3, a0, 3 +; RV32IA-NEXT: andi a3, a3, 24 +; RV32IA-NEXT: sll a6, a2, a3 +; RV32IA-NEXT: sll a1, a1, a3 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB100_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a3, (a6) -; RV32IA-NEXT: and a2, a3, a4 -; RV32IA-NEXT: mv a5, a3 +; RV32IA-NEXT: lr.w a4, (a0) +; RV32IA-NEXT: and a2, a4, a6 +; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: bgeu a2, a1, .LBB100_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB100_1 Depth=1 -; RV32IA-NEXT: xor a5, a3, a1 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 +; RV32IA-NEXT: xor a5, a4, a1 +; RV32IA-NEXT: and a5, a5, a6 +; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: .LBB100_3: # in Loop: Header=BB100_1 Depth=1 -; RV32IA-NEXT: sc.w a5, a5, (a6) +; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB100_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a3, a0 +; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umax_i16_monotonic: @@ -8803,33 +8803,33 @@ define i16 @atomicrmw_umax_i16_monotonic(i16 *%a, i16 %b) nounwind { ; RV64I-NEXT: sd s4, 16(sp) ; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s4, a0 -; RV64I-NEXT: lhu a1, 0(a0) -; RV64I-NEXT: lui a0, 16 -; RV64I-NEXT: addiw s0, a0, -1 +; RV64I-NEXT: lhu a0, 0(a0) +; RV64I-NEXT: lui a1, 16 +; RV64I-NEXT: addiw s0, a1, -1 ; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: addi s3, sp, 14 ; RV64I-NEXT: j .LBB100_2 ; RV64I-NEXT: .LBB100_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB100_2 Depth=1 -; RV64I-NEXT: sh a1, 14(sp) +; RV64I-NEXT: sh a0, 14(sp) ; RV64I-NEXT: mv a0, s4 ; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: call __atomic_compare_exchange_2 -; RV64I-NEXT: lh a1, 14(sp) -; RV64I-NEXT: bnez a0, .LBB100_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lh a0, 14(sp) +; RV64I-NEXT: bnez a1, .LBB100_4 ; RV64I-NEXT: .LBB100_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: and a0, a1, s0 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: bltu s1, a0, .LBB100_1 +; RV64I-NEXT: and a1, a0, s0 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bltu s1, a1, .LBB100_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB100_2 Depth=1 ; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB100_1 ; RV64I-NEXT: .LBB100_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: ld s4, 16(sp) ; RV64I-NEXT: ld s3, 24(sp) ; RV64I-NEXT: ld s2, 32(sp) @@ -8841,28 +8841,28 @@ define i16 @atomicrmw_umax_i16_monotonic(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_umax_i16_monotonic: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a4, a3, a0 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a3, a0, 3 +; RV64IA-NEXT: andi a3, a3, 24 +; RV64IA-NEXT: sllw a6, a2, a3 +; RV64IA-NEXT: sllw a1, a1, a3 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB100_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w a3, (a6) -; RV64IA-NEXT: and a2, a3, a4 -; RV64IA-NEXT: mv a5, a3 +; RV64IA-NEXT: lr.w a4, (a0) +; RV64IA-NEXT: and a2, a4, a6 +; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: bgeu a2, a1, .LBB100_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB100_1 Depth=1 -; RV64IA-NEXT: xor a5, a3, a1 -; RV64IA-NEXT: and a5, a5, a4 -; RV64IA-NEXT: xor a5, a3, a5 +; RV64IA-NEXT: xor a5, a4, a1 +; RV64IA-NEXT: and a5, a5, a6 +; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: .LBB100_3: # in Loop: Header=BB100_1 Depth=1 -; RV64IA-NEXT: sc.w a5, a5, (a6) +; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB100_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a3, a0 +; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: ret %1 = atomicrmw umax i16* %a, i16 %b monotonic ret i16 %1 @@ -8880,33 +8880,33 @@ define i16 @atomicrmw_umax_i16_acquire(i16 *%a, i16 %b) nounwind { ; RV32I-NEXT: sw s4, 8(sp) ; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s4, a0 -; RV32I-NEXT: lhu a1, 0(a0) -; RV32I-NEXT: lui a0, 16 -; RV32I-NEXT: addi s0, a0, -1 +; RV32I-NEXT: lhu a0, 0(a0) +; RV32I-NEXT: lui a1, 16 +; RV32I-NEXT: addi s0, a1, -1 ; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: addi s3, sp, 6 ; RV32I-NEXT: j .LBB101_2 ; RV32I-NEXT: .LBB101_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB101_2 Depth=1 -; RV32I-NEXT: sh a1, 6(sp) -; RV32I-NEXT: addi a3, zero, 2 -; RV32I-NEXT: addi a4, zero, 2 +; RV32I-NEXT: sh a0, 6(sp) ; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: mv a1, s3 +; RV32I-NEXT: addi a3, zero, 2 +; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: call __atomic_compare_exchange_2 -; RV32I-NEXT: lh a1, 6(sp) -; RV32I-NEXT: bnez a0, .LBB101_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lh a0, 6(sp) +; RV32I-NEXT: bnez a1, .LBB101_4 ; RV32I-NEXT: .LBB101_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: and a0, a1, s0 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: bltu s1, a0, .LBB101_1 +; RV32I-NEXT: and a1, a0, s0 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: bltu s1, a1, .LBB101_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB101_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB101_1 ; RV32I-NEXT: .LBB101_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: lw s4, 8(sp) ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) @@ -8918,28 +8918,28 @@ define i16 @atomicrmw_umax_i16_acquire(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_umax_i16_acquire: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a3, a0, 3 +; RV32IA-NEXT: andi a3, a3, 24 +; RV32IA-NEXT: sll a6, a2, a3 +; RV32IA-NEXT: sll a1, a1, a3 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB101_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aq a3, (a6) -; RV32IA-NEXT: and a2, a3, a4 -; RV32IA-NEXT: mv a5, a3 +; RV32IA-NEXT: lr.w.aq a4, (a0) +; RV32IA-NEXT: and a2, a4, a6 +; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: bgeu a2, a1, .LBB101_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB101_1 Depth=1 -; RV32IA-NEXT: xor a5, a3, a1 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 +; RV32IA-NEXT: xor a5, a4, a1 +; RV32IA-NEXT: and a5, a5, a6 +; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: .LBB101_3: # in Loop: Header=BB101_1 Depth=1 -; RV32IA-NEXT: sc.w a5, a5, (a6) +; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB101_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a3, a0 +; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umax_i16_acquire: @@ -8953,33 +8953,33 @@ define i16 @atomicrmw_umax_i16_acquire(i16 *%a, i16 %b) nounwind { ; RV64I-NEXT: sd s4, 16(sp) ; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s4, a0 -; RV64I-NEXT: lhu a1, 0(a0) -; RV64I-NEXT: lui a0, 16 -; RV64I-NEXT: addiw s0, a0, -1 +; RV64I-NEXT: lhu a0, 0(a0) +; RV64I-NEXT: lui a1, 16 +; RV64I-NEXT: addiw s0, a1, -1 ; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: addi s3, sp, 14 ; RV64I-NEXT: j .LBB101_2 ; RV64I-NEXT: .LBB101_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB101_2 Depth=1 -; RV64I-NEXT: sh a1, 14(sp) -; RV64I-NEXT: addi a3, zero, 2 -; RV64I-NEXT: addi a4, zero, 2 +; RV64I-NEXT: sh a0, 14(sp) ; RV64I-NEXT: mv a0, s4 ; RV64I-NEXT: mv a1, s3 +; RV64I-NEXT: addi a3, zero, 2 +; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: call __atomic_compare_exchange_2 -; RV64I-NEXT: lh a1, 14(sp) -; RV64I-NEXT: bnez a0, .LBB101_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lh a0, 14(sp) +; RV64I-NEXT: bnez a1, .LBB101_4 ; RV64I-NEXT: .LBB101_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: and a0, a1, s0 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: bltu s1, a0, .LBB101_1 +; RV64I-NEXT: and a1, a0, s0 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bltu s1, a1, .LBB101_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB101_2 Depth=1 ; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB101_1 ; RV64I-NEXT: .LBB101_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: ld s4, 16(sp) ; RV64I-NEXT: ld s3, 24(sp) ; RV64I-NEXT: ld s2, 32(sp) @@ -8991,28 +8991,28 @@ define i16 @atomicrmw_umax_i16_acquire(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_umax_i16_acquire: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a4, a3, a0 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a3, a0, 3 +; RV64IA-NEXT: andi a3, a3, 24 +; RV64IA-NEXT: sllw a6, a2, a3 +; RV64IA-NEXT: sllw a1, a1, a3 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB101_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aq a3, (a6) -; RV64IA-NEXT: and a2, a3, a4 -; RV64IA-NEXT: mv a5, a3 +; RV64IA-NEXT: lr.w.aq a4, (a0) +; RV64IA-NEXT: and a2, a4, a6 +; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: bgeu a2, a1, .LBB101_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB101_1 Depth=1 -; RV64IA-NEXT: xor a5, a3, a1 -; RV64IA-NEXT: and a5, a5, a4 -; RV64IA-NEXT: xor a5, a3, a5 +; RV64IA-NEXT: xor a5, a4, a1 +; RV64IA-NEXT: and a5, a5, a6 +; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: .LBB101_3: # in Loop: Header=BB101_1 Depth=1 -; RV64IA-NEXT: sc.w a5, a5, (a6) +; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB101_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a3, a0 +; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: ret %1 = atomicrmw umax i16* %a, i16 %b acquire ret i16 %1 @@ -9030,33 +9030,33 @@ define i16 @atomicrmw_umax_i16_release(i16 *%a, i16 %b) nounwind { ; RV32I-NEXT: sw s4, 8(sp) ; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s4, a0 -; RV32I-NEXT: lhu a1, 0(a0) -; RV32I-NEXT: lui a0, 16 -; RV32I-NEXT: addi s0, a0, -1 +; RV32I-NEXT: lhu a0, 0(a0) +; RV32I-NEXT: lui a1, 16 +; RV32I-NEXT: addi s0, a1, -1 ; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: addi s3, sp, 6 ; RV32I-NEXT: j .LBB102_2 ; RV32I-NEXT: .LBB102_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB102_2 Depth=1 -; RV32I-NEXT: sh a1, 6(sp) -; RV32I-NEXT: addi a3, zero, 3 +; RV32I-NEXT: sh a0, 6(sp) ; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: mv a1, s3 +; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: call __atomic_compare_exchange_2 -; RV32I-NEXT: lh a1, 6(sp) -; RV32I-NEXT: bnez a0, .LBB102_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lh a0, 6(sp) +; RV32I-NEXT: bnez a1, .LBB102_4 ; RV32I-NEXT: .LBB102_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: and a0, a1, s0 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: bltu s1, a0, .LBB102_1 +; RV32I-NEXT: and a1, a0, s0 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: bltu s1, a1, .LBB102_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB102_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB102_1 ; RV32I-NEXT: .LBB102_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: lw s4, 8(sp) ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) @@ -9068,28 +9068,28 @@ define i16 @atomicrmw_umax_i16_release(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_umax_i16_release: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a3, a0, 3 +; RV32IA-NEXT: andi a3, a3, 24 +; RV32IA-NEXT: sll a6, a2, a3 +; RV32IA-NEXT: sll a1, a1, a3 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB102_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a3, (a6) -; RV32IA-NEXT: and a2, a3, a4 -; RV32IA-NEXT: mv a5, a3 +; RV32IA-NEXT: lr.w a4, (a0) +; RV32IA-NEXT: and a2, a4, a6 +; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: bgeu a2, a1, .LBB102_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB102_1 Depth=1 -; RV32IA-NEXT: xor a5, a3, a1 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 +; RV32IA-NEXT: xor a5, a4, a1 +; RV32IA-NEXT: and a5, a5, a6 +; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: .LBB102_3: # in Loop: Header=BB102_1 Depth=1 -; RV32IA-NEXT: sc.w.rl a5, a5, (a6) +; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB102_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a3, a0 +; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umax_i16_release: @@ -9103,33 +9103,33 @@ define i16 @atomicrmw_umax_i16_release(i16 *%a, i16 %b) nounwind { ; RV64I-NEXT: sd s4, 16(sp) ; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s4, a0 -; RV64I-NEXT: lhu a1, 0(a0) -; RV64I-NEXT: lui a0, 16 -; RV64I-NEXT: addiw s0, a0, -1 +; RV64I-NEXT: lhu a0, 0(a0) +; RV64I-NEXT: lui a1, 16 +; RV64I-NEXT: addiw s0, a1, -1 ; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: addi s3, sp, 14 ; RV64I-NEXT: j .LBB102_2 ; RV64I-NEXT: .LBB102_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB102_2 Depth=1 -; RV64I-NEXT: sh a1, 14(sp) -; RV64I-NEXT: addi a3, zero, 3 +; RV64I-NEXT: sh a0, 14(sp) ; RV64I-NEXT: mv a0, s4 ; RV64I-NEXT: mv a1, s3 +; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: call __atomic_compare_exchange_2 -; RV64I-NEXT: lh a1, 14(sp) -; RV64I-NEXT: bnez a0, .LBB102_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lh a0, 14(sp) +; RV64I-NEXT: bnez a1, .LBB102_4 ; RV64I-NEXT: .LBB102_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: and a0, a1, s0 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: bltu s1, a0, .LBB102_1 +; RV64I-NEXT: and a1, a0, s0 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bltu s1, a1, .LBB102_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB102_2 Depth=1 ; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB102_1 ; RV64I-NEXT: .LBB102_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: ld s4, 16(sp) ; RV64I-NEXT: ld s3, 24(sp) ; RV64I-NEXT: ld s2, 32(sp) @@ -9141,28 +9141,28 @@ define i16 @atomicrmw_umax_i16_release(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_umax_i16_release: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a4, a3, a0 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a3, a0, 3 +; RV64IA-NEXT: andi a3, a3, 24 +; RV64IA-NEXT: sllw a6, a2, a3 +; RV64IA-NEXT: sllw a1, a1, a3 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB102_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w a3, (a6) -; RV64IA-NEXT: and a2, a3, a4 -; RV64IA-NEXT: mv a5, a3 +; RV64IA-NEXT: lr.w a4, (a0) +; RV64IA-NEXT: and a2, a4, a6 +; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: bgeu a2, a1, .LBB102_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB102_1 Depth=1 -; RV64IA-NEXT: xor a5, a3, a1 -; RV64IA-NEXT: and a5, a5, a4 -; RV64IA-NEXT: xor a5, a3, a5 +; RV64IA-NEXT: xor a5, a4, a1 +; RV64IA-NEXT: and a5, a5, a6 +; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: .LBB102_3: # in Loop: Header=BB102_1 Depth=1 -; RV64IA-NEXT: sc.w.rl a5, a5, (a6) +; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB102_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a3, a0 +; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: ret %1 = atomicrmw umax i16* %a, i16 %b release ret i16 %1 @@ -9180,33 +9180,33 @@ define i16 @atomicrmw_umax_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; RV32I-NEXT: sw s4, 8(sp) ; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s4, a0 -; RV32I-NEXT: lhu a1, 0(a0) -; RV32I-NEXT: lui a0, 16 -; RV32I-NEXT: addi s0, a0, -1 +; RV32I-NEXT: lhu a0, 0(a0) +; RV32I-NEXT: lui a1, 16 +; RV32I-NEXT: addi s0, a1, -1 ; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: addi s3, sp, 6 ; RV32I-NEXT: j .LBB103_2 ; RV32I-NEXT: .LBB103_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB103_2 Depth=1 -; RV32I-NEXT: sh a1, 6(sp) -; RV32I-NEXT: addi a3, zero, 4 -; RV32I-NEXT: addi a4, zero, 2 +; RV32I-NEXT: sh a0, 6(sp) ; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: mv a1, s3 +; RV32I-NEXT: addi a3, zero, 4 +; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: call __atomic_compare_exchange_2 -; RV32I-NEXT: lh a1, 6(sp) -; RV32I-NEXT: bnez a0, .LBB103_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lh a0, 6(sp) +; RV32I-NEXT: bnez a1, .LBB103_4 ; RV32I-NEXT: .LBB103_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: and a0, a1, s0 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: bltu s1, a0, .LBB103_1 +; RV32I-NEXT: and a1, a0, s0 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: bltu s1, a1, .LBB103_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB103_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB103_1 ; RV32I-NEXT: .LBB103_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: lw s4, 8(sp) ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) @@ -9218,28 +9218,28 @@ define i16 @atomicrmw_umax_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_umax_i16_acq_rel: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a3, a0, 3 +; RV32IA-NEXT: andi a3, a3, 24 +; RV32IA-NEXT: sll a6, a2, a3 +; RV32IA-NEXT: sll a1, a1, a3 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB103_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aq a3, (a6) -; RV32IA-NEXT: and a2, a3, a4 -; RV32IA-NEXT: mv a5, a3 +; RV32IA-NEXT: lr.w.aq a4, (a0) +; RV32IA-NEXT: and a2, a4, a6 +; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: bgeu a2, a1, .LBB103_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB103_1 Depth=1 -; RV32IA-NEXT: xor a5, a3, a1 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 +; RV32IA-NEXT: xor a5, a4, a1 +; RV32IA-NEXT: and a5, a5, a6 +; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: .LBB103_3: # in Loop: Header=BB103_1 Depth=1 -; RV32IA-NEXT: sc.w.rl a5, a5, (a6) +; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB103_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a3, a0 +; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umax_i16_acq_rel: @@ -9253,33 +9253,33 @@ define i16 @atomicrmw_umax_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; RV64I-NEXT: sd s4, 16(sp) ; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s4, a0 -; RV64I-NEXT: lhu a1, 0(a0) -; RV64I-NEXT: lui a0, 16 -; RV64I-NEXT: addiw s0, a0, -1 +; RV64I-NEXT: lhu a0, 0(a0) +; RV64I-NEXT: lui a1, 16 +; RV64I-NEXT: addiw s0, a1, -1 ; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: addi s3, sp, 14 ; RV64I-NEXT: j .LBB103_2 ; RV64I-NEXT: .LBB103_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB103_2 Depth=1 -; RV64I-NEXT: sh a1, 14(sp) -; RV64I-NEXT: addi a3, zero, 4 -; RV64I-NEXT: addi a4, zero, 2 +; RV64I-NEXT: sh a0, 14(sp) ; RV64I-NEXT: mv a0, s4 ; RV64I-NEXT: mv a1, s3 +; RV64I-NEXT: addi a3, zero, 4 +; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: call __atomic_compare_exchange_2 -; RV64I-NEXT: lh a1, 14(sp) -; RV64I-NEXT: bnez a0, .LBB103_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lh a0, 14(sp) +; RV64I-NEXT: bnez a1, .LBB103_4 ; RV64I-NEXT: .LBB103_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: and a0, a1, s0 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: bltu s1, a0, .LBB103_1 +; RV64I-NEXT: and a1, a0, s0 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bltu s1, a1, .LBB103_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB103_2 Depth=1 ; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB103_1 ; RV64I-NEXT: .LBB103_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: ld s4, 16(sp) ; RV64I-NEXT: ld s3, 24(sp) ; RV64I-NEXT: ld s2, 32(sp) @@ -9291,28 +9291,28 @@ define i16 @atomicrmw_umax_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_umax_i16_acq_rel: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a4, a3, a0 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a3, a0, 3 +; RV64IA-NEXT: andi a3, a3, 24 +; RV64IA-NEXT: sllw a6, a2, a3 +; RV64IA-NEXT: sllw a1, a1, a3 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB103_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aq a3, (a6) -; RV64IA-NEXT: and a2, a3, a4 -; RV64IA-NEXT: mv a5, a3 +; RV64IA-NEXT: lr.w.aq a4, (a0) +; RV64IA-NEXT: and a2, a4, a6 +; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: bgeu a2, a1, .LBB103_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB103_1 Depth=1 -; RV64IA-NEXT: xor a5, a3, a1 -; RV64IA-NEXT: and a5, a5, a4 -; RV64IA-NEXT: xor a5, a3, a5 +; RV64IA-NEXT: xor a5, a4, a1 +; RV64IA-NEXT: and a5, a5, a6 +; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: .LBB103_3: # in Loop: Header=BB103_1 Depth=1 -; RV64IA-NEXT: sc.w.rl a5, a5, (a6) +; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB103_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a3, a0 +; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: ret %1 = atomicrmw umax i16* %a, i16 %b acq_rel ret i16 %1 @@ -9330,33 +9330,33 @@ define i16 @atomicrmw_umax_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; RV32I-NEXT: sw s4, 8(sp) ; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s4, a0 -; RV32I-NEXT: lhu a1, 0(a0) -; RV32I-NEXT: lui a0, 16 -; RV32I-NEXT: addi s0, a0, -1 +; RV32I-NEXT: lhu a0, 0(a0) +; RV32I-NEXT: lui a1, 16 +; RV32I-NEXT: addi s0, a1, -1 ; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: addi s3, sp, 6 ; RV32I-NEXT: j .LBB104_2 ; RV32I-NEXT: .LBB104_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB104_2 Depth=1 -; RV32I-NEXT: sh a1, 6(sp) -; RV32I-NEXT: addi a3, zero, 5 -; RV32I-NEXT: addi a4, zero, 5 +; RV32I-NEXT: sh a0, 6(sp) ; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: mv a1, s3 +; RV32I-NEXT: addi a3, zero, 5 +; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: call __atomic_compare_exchange_2 -; RV32I-NEXT: lh a1, 6(sp) -; RV32I-NEXT: bnez a0, .LBB104_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lh a0, 6(sp) +; RV32I-NEXT: bnez a1, .LBB104_4 ; RV32I-NEXT: .LBB104_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: and a0, a1, s0 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: bltu s1, a0, .LBB104_1 +; RV32I-NEXT: and a1, a0, s0 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: bltu s1, a1, .LBB104_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB104_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB104_1 ; RV32I-NEXT: .LBB104_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: lw s4, 8(sp) ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) @@ -9368,28 +9368,28 @@ define i16 @atomicrmw_umax_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_umax_i16_seq_cst: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a3, a0, 3 +; RV32IA-NEXT: andi a3, a3, 24 +; RV32IA-NEXT: sll a6, a2, a3 +; RV32IA-NEXT: sll a1, a1, a3 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB104_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aqrl a3, (a6) -; RV32IA-NEXT: and a2, a3, a4 -; RV32IA-NEXT: mv a5, a3 +; RV32IA-NEXT: lr.w.aqrl a4, (a0) +; RV32IA-NEXT: and a2, a4, a6 +; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: bgeu a2, a1, .LBB104_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB104_1 Depth=1 -; RV32IA-NEXT: xor a5, a3, a1 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 +; RV32IA-NEXT: xor a5, a4, a1 +; RV32IA-NEXT: and a5, a5, a6 +; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: .LBB104_3: # in Loop: Header=BB104_1 Depth=1 -; RV32IA-NEXT: sc.w.aqrl a5, a5, (a6) +; RV32IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB104_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a3, a0 +; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umax_i16_seq_cst: @@ -9403,33 +9403,33 @@ define i16 @atomicrmw_umax_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; RV64I-NEXT: sd s4, 16(sp) ; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s4, a0 -; RV64I-NEXT: lhu a1, 0(a0) -; RV64I-NEXT: lui a0, 16 -; RV64I-NEXT: addiw s0, a0, -1 +; RV64I-NEXT: lhu a0, 0(a0) +; RV64I-NEXT: lui a1, 16 +; RV64I-NEXT: addiw s0, a1, -1 ; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: addi s3, sp, 14 ; RV64I-NEXT: j .LBB104_2 ; RV64I-NEXT: .LBB104_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB104_2 Depth=1 -; RV64I-NEXT: sh a1, 14(sp) -; RV64I-NEXT: addi a3, zero, 5 -; RV64I-NEXT: addi a4, zero, 5 +; RV64I-NEXT: sh a0, 14(sp) ; RV64I-NEXT: mv a0, s4 ; RV64I-NEXT: mv a1, s3 +; RV64I-NEXT: addi a3, zero, 5 +; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: call __atomic_compare_exchange_2 -; RV64I-NEXT: lh a1, 14(sp) -; RV64I-NEXT: bnez a0, .LBB104_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lh a0, 14(sp) +; RV64I-NEXT: bnez a1, .LBB104_4 ; RV64I-NEXT: .LBB104_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: and a0, a1, s0 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: bltu s1, a0, .LBB104_1 +; RV64I-NEXT: and a1, a0, s0 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bltu s1, a1, .LBB104_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB104_2 Depth=1 ; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB104_1 ; RV64I-NEXT: .LBB104_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: ld s4, 16(sp) ; RV64I-NEXT: ld s3, 24(sp) ; RV64I-NEXT: ld s2, 32(sp) @@ -9441,28 +9441,28 @@ define i16 @atomicrmw_umax_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_umax_i16_seq_cst: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a4, a3, a0 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a3, a0, 3 +; RV64IA-NEXT: andi a3, a3, 24 +; RV64IA-NEXT: sllw a6, a2, a3 +; RV64IA-NEXT: sllw a1, a1, a3 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB104_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aqrl a3, (a6) -; RV64IA-NEXT: and a2, a3, a4 -; RV64IA-NEXT: mv a5, a3 +; RV64IA-NEXT: lr.w.aqrl a4, (a0) +; RV64IA-NEXT: and a2, a4, a6 +; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: bgeu a2, a1, .LBB104_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB104_1 Depth=1 -; RV64IA-NEXT: xor a5, a3, a1 -; RV64IA-NEXT: and a5, a5, a4 -; RV64IA-NEXT: xor a5, a3, a5 +; RV64IA-NEXT: xor a5, a4, a1 +; RV64IA-NEXT: and a5, a5, a6 +; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: .LBB104_3: # in Loop: Header=BB104_1 Depth=1 -; RV64IA-NEXT: sc.w.aqrl a5, a5, (a6) +; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB104_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a3, a0 +; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: ret %1 = atomicrmw umax i16* %a, i16 %b seq_cst ret i16 %1 @@ -9480,33 +9480,33 @@ define i16 @atomicrmw_umin_i16_monotonic(i16 *%a, i16 %b) nounwind { ; RV32I-NEXT: sw s4, 8(sp) ; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s4, a0 -; RV32I-NEXT: lhu a1, 0(a0) -; RV32I-NEXT: lui a0, 16 -; RV32I-NEXT: addi s0, a0, -1 +; RV32I-NEXT: lhu a0, 0(a0) +; RV32I-NEXT: lui a1, 16 +; RV32I-NEXT: addi s0, a1, -1 ; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: addi s3, sp, 6 ; RV32I-NEXT: j .LBB105_2 ; RV32I-NEXT: .LBB105_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB105_2 Depth=1 -; RV32I-NEXT: sh a1, 6(sp) +; RV32I-NEXT: sh a0, 6(sp) ; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: call __atomic_compare_exchange_2 -; RV32I-NEXT: lh a1, 6(sp) -; RV32I-NEXT: bnez a0, .LBB105_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lh a0, 6(sp) +; RV32I-NEXT: bnez a1, .LBB105_4 ; RV32I-NEXT: .LBB105_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: and a0, a1, s0 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: bgeu s1, a0, .LBB105_1 +; RV32I-NEXT: and a1, a0, s0 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: bgeu s1, a1, .LBB105_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB105_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB105_1 ; RV32I-NEXT: .LBB105_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: lw s4, 8(sp) ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) @@ -9518,28 +9518,28 @@ define i16 @atomicrmw_umin_i16_monotonic(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_umin_i16_monotonic: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a3, a0, 3 +; RV32IA-NEXT: andi a3, a3, 24 +; RV32IA-NEXT: sll a6, a2, a3 +; RV32IA-NEXT: sll a1, a1, a3 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB105_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a3, (a6) -; RV32IA-NEXT: and a2, a3, a4 -; RV32IA-NEXT: mv a5, a3 +; RV32IA-NEXT: lr.w a4, (a0) +; RV32IA-NEXT: and a2, a4, a6 +; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: bgeu a1, a2, .LBB105_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB105_1 Depth=1 -; RV32IA-NEXT: xor a5, a3, a1 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 +; RV32IA-NEXT: xor a5, a4, a1 +; RV32IA-NEXT: and a5, a5, a6 +; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: .LBB105_3: # in Loop: Header=BB105_1 Depth=1 -; RV32IA-NEXT: sc.w a5, a5, (a6) +; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB105_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a3, a0 +; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umin_i16_monotonic: @@ -9553,33 +9553,33 @@ define i16 @atomicrmw_umin_i16_monotonic(i16 *%a, i16 %b) nounwind { ; RV64I-NEXT: sd s4, 16(sp) ; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s4, a0 -; RV64I-NEXT: lhu a1, 0(a0) -; RV64I-NEXT: lui a0, 16 -; RV64I-NEXT: addiw s0, a0, -1 +; RV64I-NEXT: lhu a0, 0(a0) +; RV64I-NEXT: lui a1, 16 +; RV64I-NEXT: addiw s0, a1, -1 ; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: addi s3, sp, 14 ; RV64I-NEXT: j .LBB105_2 ; RV64I-NEXT: .LBB105_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB105_2 Depth=1 -; RV64I-NEXT: sh a1, 14(sp) +; RV64I-NEXT: sh a0, 14(sp) ; RV64I-NEXT: mv a0, s4 ; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: call __atomic_compare_exchange_2 -; RV64I-NEXT: lh a1, 14(sp) -; RV64I-NEXT: bnez a0, .LBB105_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lh a0, 14(sp) +; RV64I-NEXT: bnez a1, .LBB105_4 ; RV64I-NEXT: .LBB105_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: and a0, a1, s0 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: bgeu s1, a0, .LBB105_1 +; RV64I-NEXT: and a1, a0, s0 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bgeu s1, a1, .LBB105_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB105_2 Depth=1 ; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB105_1 ; RV64I-NEXT: .LBB105_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: ld s4, 16(sp) ; RV64I-NEXT: ld s3, 24(sp) ; RV64I-NEXT: ld s2, 32(sp) @@ -9591,28 +9591,28 @@ define i16 @atomicrmw_umin_i16_monotonic(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_umin_i16_monotonic: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a4, a3, a0 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a3, a0, 3 +; RV64IA-NEXT: andi a3, a3, 24 +; RV64IA-NEXT: sllw a6, a2, a3 +; RV64IA-NEXT: sllw a1, a1, a3 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB105_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w a3, (a6) -; RV64IA-NEXT: and a2, a3, a4 -; RV64IA-NEXT: mv a5, a3 +; RV64IA-NEXT: lr.w a4, (a0) +; RV64IA-NEXT: and a2, a4, a6 +; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: bgeu a1, a2, .LBB105_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB105_1 Depth=1 -; RV64IA-NEXT: xor a5, a3, a1 -; RV64IA-NEXT: and a5, a5, a4 -; RV64IA-NEXT: xor a5, a3, a5 +; RV64IA-NEXT: xor a5, a4, a1 +; RV64IA-NEXT: and a5, a5, a6 +; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: .LBB105_3: # in Loop: Header=BB105_1 Depth=1 -; RV64IA-NEXT: sc.w a5, a5, (a6) +; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB105_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a3, a0 +; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: ret %1 = atomicrmw umin i16* %a, i16 %b monotonic ret i16 %1 @@ -9630,33 +9630,33 @@ define i16 @atomicrmw_umin_i16_acquire(i16 *%a, i16 %b) nounwind { ; RV32I-NEXT: sw s4, 8(sp) ; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s4, a0 -; RV32I-NEXT: lhu a1, 0(a0) -; RV32I-NEXT: lui a0, 16 -; RV32I-NEXT: addi s0, a0, -1 +; RV32I-NEXT: lhu a0, 0(a0) +; RV32I-NEXT: lui a1, 16 +; RV32I-NEXT: addi s0, a1, -1 ; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: addi s3, sp, 6 ; RV32I-NEXT: j .LBB106_2 ; RV32I-NEXT: .LBB106_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB106_2 Depth=1 -; RV32I-NEXT: sh a1, 6(sp) -; RV32I-NEXT: addi a3, zero, 2 -; RV32I-NEXT: addi a4, zero, 2 +; RV32I-NEXT: sh a0, 6(sp) ; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: mv a1, s3 +; RV32I-NEXT: addi a3, zero, 2 +; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: call __atomic_compare_exchange_2 -; RV32I-NEXT: lh a1, 6(sp) -; RV32I-NEXT: bnez a0, .LBB106_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lh a0, 6(sp) +; RV32I-NEXT: bnez a1, .LBB106_4 ; RV32I-NEXT: .LBB106_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: and a0, a1, s0 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: bgeu s1, a0, .LBB106_1 +; RV32I-NEXT: and a1, a0, s0 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: bgeu s1, a1, .LBB106_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB106_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB106_1 ; RV32I-NEXT: .LBB106_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: lw s4, 8(sp) ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) @@ -9668,28 +9668,28 @@ define i16 @atomicrmw_umin_i16_acquire(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_umin_i16_acquire: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a3, a0, 3 +; RV32IA-NEXT: andi a3, a3, 24 +; RV32IA-NEXT: sll a6, a2, a3 +; RV32IA-NEXT: sll a1, a1, a3 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB106_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aq a3, (a6) -; RV32IA-NEXT: and a2, a3, a4 -; RV32IA-NEXT: mv a5, a3 +; RV32IA-NEXT: lr.w.aq a4, (a0) +; RV32IA-NEXT: and a2, a4, a6 +; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: bgeu a1, a2, .LBB106_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB106_1 Depth=1 -; RV32IA-NEXT: xor a5, a3, a1 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 +; RV32IA-NEXT: xor a5, a4, a1 +; RV32IA-NEXT: and a5, a5, a6 +; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: .LBB106_3: # in Loop: Header=BB106_1 Depth=1 -; RV32IA-NEXT: sc.w a5, a5, (a6) +; RV32IA-NEXT: sc.w a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB106_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a3, a0 +; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umin_i16_acquire: @@ -9703,33 +9703,33 @@ define i16 @atomicrmw_umin_i16_acquire(i16 *%a, i16 %b) nounwind { ; RV64I-NEXT: sd s4, 16(sp) ; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s4, a0 -; RV64I-NEXT: lhu a1, 0(a0) -; RV64I-NEXT: lui a0, 16 -; RV64I-NEXT: addiw s0, a0, -1 +; RV64I-NEXT: lhu a0, 0(a0) +; RV64I-NEXT: lui a1, 16 +; RV64I-NEXT: addiw s0, a1, -1 ; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: addi s3, sp, 14 ; RV64I-NEXT: j .LBB106_2 ; RV64I-NEXT: .LBB106_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB106_2 Depth=1 -; RV64I-NEXT: sh a1, 14(sp) -; RV64I-NEXT: addi a3, zero, 2 -; RV64I-NEXT: addi a4, zero, 2 +; RV64I-NEXT: sh a0, 14(sp) ; RV64I-NEXT: mv a0, s4 ; RV64I-NEXT: mv a1, s3 +; RV64I-NEXT: addi a3, zero, 2 +; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: call __atomic_compare_exchange_2 -; RV64I-NEXT: lh a1, 14(sp) -; RV64I-NEXT: bnez a0, .LBB106_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lh a0, 14(sp) +; RV64I-NEXT: bnez a1, .LBB106_4 ; RV64I-NEXT: .LBB106_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: and a0, a1, s0 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: bgeu s1, a0, .LBB106_1 +; RV64I-NEXT: and a1, a0, s0 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bgeu s1, a1, .LBB106_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB106_2 Depth=1 ; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB106_1 ; RV64I-NEXT: .LBB106_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: ld s4, 16(sp) ; RV64I-NEXT: ld s3, 24(sp) ; RV64I-NEXT: ld s2, 32(sp) @@ -9741,28 +9741,28 @@ define i16 @atomicrmw_umin_i16_acquire(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_umin_i16_acquire: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a4, a3, a0 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a3, a0, 3 +; RV64IA-NEXT: andi a3, a3, 24 +; RV64IA-NEXT: sllw a6, a2, a3 +; RV64IA-NEXT: sllw a1, a1, a3 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB106_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aq a3, (a6) -; RV64IA-NEXT: and a2, a3, a4 -; RV64IA-NEXT: mv a5, a3 +; RV64IA-NEXT: lr.w.aq a4, (a0) +; RV64IA-NEXT: and a2, a4, a6 +; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: bgeu a1, a2, .LBB106_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB106_1 Depth=1 -; RV64IA-NEXT: xor a5, a3, a1 -; RV64IA-NEXT: and a5, a5, a4 -; RV64IA-NEXT: xor a5, a3, a5 +; RV64IA-NEXT: xor a5, a4, a1 +; RV64IA-NEXT: and a5, a5, a6 +; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: .LBB106_3: # in Loop: Header=BB106_1 Depth=1 -; RV64IA-NEXT: sc.w a5, a5, (a6) +; RV64IA-NEXT: sc.w a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB106_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a3, a0 +; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: ret %1 = atomicrmw umin i16* %a, i16 %b acquire ret i16 %1 @@ -9780,33 +9780,33 @@ define i16 @atomicrmw_umin_i16_release(i16 *%a, i16 %b) nounwind { ; RV32I-NEXT: sw s4, 8(sp) ; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s4, a0 -; RV32I-NEXT: lhu a1, 0(a0) -; RV32I-NEXT: lui a0, 16 -; RV32I-NEXT: addi s0, a0, -1 +; RV32I-NEXT: lhu a0, 0(a0) +; RV32I-NEXT: lui a1, 16 +; RV32I-NEXT: addi s0, a1, -1 ; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: addi s3, sp, 6 ; RV32I-NEXT: j .LBB107_2 ; RV32I-NEXT: .LBB107_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB107_2 Depth=1 -; RV32I-NEXT: sh a1, 6(sp) -; RV32I-NEXT: addi a3, zero, 3 +; RV32I-NEXT: sh a0, 6(sp) ; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: mv a1, s3 +; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: call __atomic_compare_exchange_2 -; RV32I-NEXT: lh a1, 6(sp) -; RV32I-NEXT: bnez a0, .LBB107_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lh a0, 6(sp) +; RV32I-NEXT: bnez a1, .LBB107_4 ; RV32I-NEXT: .LBB107_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: and a0, a1, s0 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: bgeu s1, a0, .LBB107_1 +; RV32I-NEXT: and a1, a0, s0 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: bgeu s1, a1, .LBB107_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB107_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB107_1 ; RV32I-NEXT: .LBB107_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: lw s4, 8(sp) ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) @@ -9818,28 +9818,28 @@ define i16 @atomicrmw_umin_i16_release(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_umin_i16_release: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a3, a0, 3 +; RV32IA-NEXT: andi a3, a3, 24 +; RV32IA-NEXT: sll a6, a2, a3 +; RV32IA-NEXT: sll a1, a1, a3 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB107_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a3, (a6) -; RV32IA-NEXT: and a2, a3, a4 -; RV32IA-NEXT: mv a5, a3 +; RV32IA-NEXT: lr.w a4, (a0) +; RV32IA-NEXT: and a2, a4, a6 +; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: bgeu a1, a2, .LBB107_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB107_1 Depth=1 -; RV32IA-NEXT: xor a5, a3, a1 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 +; RV32IA-NEXT: xor a5, a4, a1 +; RV32IA-NEXT: and a5, a5, a6 +; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: .LBB107_3: # in Loop: Header=BB107_1 Depth=1 -; RV32IA-NEXT: sc.w.rl a5, a5, (a6) +; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB107_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a3, a0 +; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umin_i16_release: @@ -9853,33 +9853,33 @@ define i16 @atomicrmw_umin_i16_release(i16 *%a, i16 %b) nounwind { ; RV64I-NEXT: sd s4, 16(sp) ; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s4, a0 -; RV64I-NEXT: lhu a1, 0(a0) -; RV64I-NEXT: lui a0, 16 -; RV64I-NEXT: addiw s0, a0, -1 +; RV64I-NEXT: lhu a0, 0(a0) +; RV64I-NEXT: lui a1, 16 +; RV64I-NEXT: addiw s0, a1, -1 ; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: addi s3, sp, 14 ; RV64I-NEXT: j .LBB107_2 ; RV64I-NEXT: .LBB107_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB107_2 Depth=1 -; RV64I-NEXT: sh a1, 14(sp) -; RV64I-NEXT: addi a3, zero, 3 +; RV64I-NEXT: sh a0, 14(sp) ; RV64I-NEXT: mv a0, s4 ; RV64I-NEXT: mv a1, s3 +; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: call __atomic_compare_exchange_2 -; RV64I-NEXT: lh a1, 14(sp) -; RV64I-NEXT: bnez a0, .LBB107_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lh a0, 14(sp) +; RV64I-NEXT: bnez a1, .LBB107_4 ; RV64I-NEXT: .LBB107_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: and a0, a1, s0 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: bgeu s1, a0, .LBB107_1 +; RV64I-NEXT: and a1, a0, s0 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bgeu s1, a1, .LBB107_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB107_2 Depth=1 ; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB107_1 ; RV64I-NEXT: .LBB107_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: ld s4, 16(sp) ; RV64I-NEXT: ld s3, 24(sp) ; RV64I-NEXT: ld s2, 32(sp) @@ -9891,28 +9891,28 @@ define i16 @atomicrmw_umin_i16_release(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_umin_i16_release: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a4, a3, a0 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a3, a0, 3 +; RV64IA-NEXT: andi a3, a3, 24 +; RV64IA-NEXT: sllw a6, a2, a3 +; RV64IA-NEXT: sllw a1, a1, a3 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB107_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w a3, (a6) -; RV64IA-NEXT: and a2, a3, a4 -; RV64IA-NEXT: mv a5, a3 +; RV64IA-NEXT: lr.w a4, (a0) +; RV64IA-NEXT: and a2, a4, a6 +; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: bgeu a1, a2, .LBB107_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB107_1 Depth=1 -; RV64IA-NEXT: xor a5, a3, a1 -; RV64IA-NEXT: and a5, a5, a4 -; RV64IA-NEXT: xor a5, a3, a5 +; RV64IA-NEXT: xor a5, a4, a1 +; RV64IA-NEXT: and a5, a5, a6 +; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: .LBB107_3: # in Loop: Header=BB107_1 Depth=1 -; RV64IA-NEXT: sc.w.rl a5, a5, (a6) +; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB107_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a3, a0 +; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: ret %1 = atomicrmw umin i16* %a, i16 %b release ret i16 %1 @@ -9930,33 +9930,33 @@ define i16 @atomicrmw_umin_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; RV32I-NEXT: sw s4, 8(sp) ; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s4, a0 -; RV32I-NEXT: lhu a1, 0(a0) -; RV32I-NEXT: lui a0, 16 -; RV32I-NEXT: addi s0, a0, -1 +; RV32I-NEXT: lhu a0, 0(a0) +; RV32I-NEXT: lui a1, 16 +; RV32I-NEXT: addi s0, a1, -1 ; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: addi s3, sp, 6 ; RV32I-NEXT: j .LBB108_2 ; RV32I-NEXT: .LBB108_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB108_2 Depth=1 -; RV32I-NEXT: sh a1, 6(sp) -; RV32I-NEXT: addi a3, zero, 4 -; RV32I-NEXT: addi a4, zero, 2 +; RV32I-NEXT: sh a0, 6(sp) ; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: mv a1, s3 +; RV32I-NEXT: addi a3, zero, 4 +; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: call __atomic_compare_exchange_2 -; RV32I-NEXT: lh a1, 6(sp) -; RV32I-NEXT: bnez a0, .LBB108_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lh a0, 6(sp) +; RV32I-NEXT: bnez a1, .LBB108_4 ; RV32I-NEXT: .LBB108_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: and a0, a1, s0 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: bgeu s1, a0, .LBB108_1 +; RV32I-NEXT: and a1, a0, s0 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: bgeu s1, a1, .LBB108_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB108_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB108_1 ; RV32I-NEXT: .LBB108_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: lw s4, 8(sp) ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) @@ -9968,28 +9968,28 @@ define i16 @atomicrmw_umin_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_umin_i16_acq_rel: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a3, a0, 3 +; RV32IA-NEXT: andi a3, a3, 24 +; RV32IA-NEXT: sll a6, a2, a3 +; RV32IA-NEXT: sll a1, a1, a3 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB108_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aq a3, (a6) -; RV32IA-NEXT: and a2, a3, a4 -; RV32IA-NEXT: mv a5, a3 +; RV32IA-NEXT: lr.w.aq a4, (a0) +; RV32IA-NEXT: and a2, a4, a6 +; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: bgeu a1, a2, .LBB108_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB108_1 Depth=1 -; RV32IA-NEXT: xor a5, a3, a1 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 +; RV32IA-NEXT: xor a5, a4, a1 +; RV32IA-NEXT: and a5, a5, a6 +; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: .LBB108_3: # in Loop: Header=BB108_1 Depth=1 -; RV32IA-NEXT: sc.w.rl a5, a5, (a6) +; RV32IA-NEXT: sc.w.rl a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB108_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a3, a0 +; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umin_i16_acq_rel: @@ -10003,33 +10003,33 @@ define i16 @atomicrmw_umin_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; RV64I-NEXT: sd s4, 16(sp) ; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s4, a0 -; RV64I-NEXT: lhu a1, 0(a0) -; RV64I-NEXT: lui a0, 16 -; RV64I-NEXT: addiw s0, a0, -1 +; RV64I-NEXT: lhu a0, 0(a0) +; RV64I-NEXT: lui a1, 16 +; RV64I-NEXT: addiw s0, a1, -1 ; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: addi s3, sp, 14 ; RV64I-NEXT: j .LBB108_2 ; RV64I-NEXT: .LBB108_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB108_2 Depth=1 -; RV64I-NEXT: sh a1, 14(sp) -; RV64I-NEXT: addi a3, zero, 4 -; RV64I-NEXT: addi a4, zero, 2 +; RV64I-NEXT: sh a0, 14(sp) ; RV64I-NEXT: mv a0, s4 ; RV64I-NEXT: mv a1, s3 +; RV64I-NEXT: addi a3, zero, 4 +; RV64I-NEXT: addi a4, zero, 2 ; RV64I-NEXT: call __atomic_compare_exchange_2 -; RV64I-NEXT: lh a1, 14(sp) -; RV64I-NEXT: bnez a0, .LBB108_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lh a0, 14(sp) +; RV64I-NEXT: bnez a1, .LBB108_4 ; RV64I-NEXT: .LBB108_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: and a0, a1, s0 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: bgeu s1, a0, .LBB108_1 +; RV64I-NEXT: and a1, a0, s0 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bgeu s1, a1, .LBB108_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB108_2 Depth=1 ; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB108_1 ; RV64I-NEXT: .LBB108_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: ld s4, 16(sp) ; RV64I-NEXT: ld s3, 24(sp) ; RV64I-NEXT: ld s2, 32(sp) @@ -10041,28 +10041,28 @@ define i16 @atomicrmw_umin_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_umin_i16_acq_rel: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a4, a3, a0 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a3, a0, 3 +; RV64IA-NEXT: andi a3, a3, 24 +; RV64IA-NEXT: sllw a6, a2, a3 +; RV64IA-NEXT: sllw a1, a1, a3 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB108_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aq a3, (a6) -; RV64IA-NEXT: and a2, a3, a4 -; RV64IA-NEXT: mv a5, a3 +; RV64IA-NEXT: lr.w.aq a4, (a0) +; RV64IA-NEXT: and a2, a4, a6 +; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: bgeu a1, a2, .LBB108_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB108_1 Depth=1 -; RV64IA-NEXT: xor a5, a3, a1 -; RV64IA-NEXT: and a5, a5, a4 -; RV64IA-NEXT: xor a5, a3, a5 +; RV64IA-NEXT: xor a5, a4, a1 +; RV64IA-NEXT: and a5, a5, a6 +; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: .LBB108_3: # in Loop: Header=BB108_1 Depth=1 -; RV64IA-NEXT: sc.w.rl a5, a5, (a6) +; RV64IA-NEXT: sc.w.rl a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB108_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a3, a0 +; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: ret %1 = atomicrmw umin i16* %a, i16 %b acq_rel ret i16 %1 @@ -10080,33 +10080,33 @@ define i16 @atomicrmw_umin_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; RV32I-NEXT: sw s4, 8(sp) ; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s4, a0 -; RV32I-NEXT: lhu a1, 0(a0) -; RV32I-NEXT: lui a0, 16 -; RV32I-NEXT: addi s0, a0, -1 +; RV32I-NEXT: lhu a0, 0(a0) +; RV32I-NEXT: lui a1, 16 +; RV32I-NEXT: addi s0, a1, -1 ; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: addi s3, sp, 6 ; RV32I-NEXT: j .LBB109_2 ; RV32I-NEXT: .LBB109_1: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB109_2 Depth=1 -; RV32I-NEXT: sh a1, 6(sp) -; RV32I-NEXT: addi a3, zero, 5 -; RV32I-NEXT: addi a4, zero, 5 +; RV32I-NEXT: sh a0, 6(sp) ; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: mv a1, s3 +; RV32I-NEXT: addi a3, zero, 5 +; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: call __atomic_compare_exchange_2 -; RV32I-NEXT: lh a1, 6(sp) -; RV32I-NEXT: bnez a0, .LBB109_4 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: lh a0, 6(sp) +; RV32I-NEXT: bnez a1, .LBB109_4 ; RV32I-NEXT: .LBB109_2: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: and a0, a1, s0 -; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: bgeu s1, a0, .LBB109_1 +; RV32I-NEXT: and a1, a0, s0 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: bgeu s1, a1, .LBB109_1 ; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB109_2 Depth=1 ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: j .LBB109_1 ; RV32I-NEXT: .LBB109_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: lw s4, 8(sp) ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) @@ -10118,28 +10118,28 @@ define i16 @atomicrmw_umin_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomicrmw_umin_i16_seq_cst: ; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a6, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: andi a0, a0, 24 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 +; RV32IA-NEXT: lui a2, 16 +; RV32IA-NEXT: addi a2, a2, -1 +; RV32IA-NEXT: and a1, a1, a2 +; RV32IA-NEXT: slli a3, a0, 3 +; RV32IA-NEXT: andi a3, a3, 24 +; RV32IA-NEXT: sll a6, a2, a3 +; RV32IA-NEXT: sll a1, a1, a3 +; RV32IA-NEXT: andi a0, a0, -4 ; RV32IA-NEXT: .LBB109_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aqrl a3, (a6) -; RV32IA-NEXT: and a2, a3, a4 -; RV32IA-NEXT: mv a5, a3 +; RV32IA-NEXT: lr.w.aqrl a4, (a0) +; RV32IA-NEXT: and a2, a4, a6 +; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: bgeu a1, a2, .LBB109_3 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB109_1 Depth=1 -; RV32IA-NEXT: xor a5, a3, a1 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 +; RV32IA-NEXT: xor a5, a4, a1 +; RV32IA-NEXT: and a5, a5, a6 +; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: .LBB109_3: # in Loop: Header=BB109_1 Depth=1 -; RV32IA-NEXT: sc.w.aqrl a5, a5, (a6) +; RV32IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV32IA-NEXT: bnez a5, .LBB109_1 ; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a3, a0 +; RV32IA-NEXT: srl a0, a4, a3 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umin_i16_seq_cst: @@ -10153,33 +10153,33 @@ define i16 @atomicrmw_umin_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; RV64I-NEXT: sd s4, 16(sp) ; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s4, a0 -; RV64I-NEXT: lhu a1, 0(a0) -; RV64I-NEXT: lui a0, 16 -; RV64I-NEXT: addiw s0, a0, -1 +; RV64I-NEXT: lhu a0, 0(a0) +; RV64I-NEXT: lui a1, 16 +; RV64I-NEXT: addiw s0, a1, -1 ; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: addi s3, sp, 14 ; RV64I-NEXT: j .LBB109_2 ; RV64I-NEXT: .LBB109_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB109_2 Depth=1 -; RV64I-NEXT: sh a1, 14(sp) -; RV64I-NEXT: addi a3, zero, 5 -; RV64I-NEXT: addi a4, zero, 5 +; RV64I-NEXT: sh a0, 14(sp) ; RV64I-NEXT: mv a0, s4 ; RV64I-NEXT: mv a1, s3 +; RV64I-NEXT: addi a3, zero, 5 +; RV64I-NEXT: addi a4, zero, 5 ; RV64I-NEXT: call __atomic_compare_exchange_2 -; RV64I-NEXT: lh a1, 14(sp) -; RV64I-NEXT: bnez a0, .LBB109_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lh a0, 14(sp) +; RV64I-NEXT: bnez a1, .LBB109_4 ; RV64I-NEXT: .LBB109_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: and a0, a1, s0 -; RV64I-NEXT: mv a2, a1 -; RV64I-NEXT: bgeu s1, a0, .LBB109_1 +; RV64I-NEXT: and a1, a0, s0 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bgeu s1, a1, .LBB109_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB109_2 Depth=1 ; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB109_1 ; RV64I-NEXT: .LBB109_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: ld s4, 16(sp) ; RV64I-NEXT: ld s3, 24(sp) ; RV64I-NEXT: ld s2, 32(sp) @@ -10191,28 +10191,28 @@ define i16 @atomicrmw_umin_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; ; RV64IA-LABEL: atomicrmw_umin_i16_seq_cst: ; RV64IA: # %bb.0: -; RV64IA-NEXT: andi a6, a0, -4 -; RV64IA-NEXT: slli a0, a0, 3 -; RV64IA-NEXT: andi a0, a0, 24 -; RV64IA-NEXT: lui a3, 16 -; RV64IA-NEXT: addiw a3, a3, -1 -; RV64IA-NEXT: sllw a4, a3, a0 -; RV64IA-NEXT: and a1, a1, a3 -; RV64IA-NEXT: sllw a1, a1, a0 +; RV64IA-NEXT: lui a2, 16 +; RV64IA-NEXT: addiw a2, a2, -1 +; RV64IA-NEXT: and a1, a1, a2 +; RV64IA-NEXT: slli a3, a0, 3 +; RV64IA-NEXT: andi a3, a3, 24 +; RV64IA-NEXT: sllw a6, a2, a3 +; RV64IA-NEXT: sllw a1, a1, a3 +; RV64IA-NEXT: andi a0, a0, -4 ; RV64IA-NEXT: .LBB109_1: # =>This Inner Loop Header: Depth=1 -; RV64IA-NEXT: lr.w.aqrl a3, (a6) -; RV64IA-NEXT: and a2, a3, a4 -; RV64IA-NEXT: mv a5, a3 +; RV64IA-NEXT: lr.w.aqrl a4, (a0) +; RV64IA-NEXT: and a2, a4, a6 +; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: bgeu a1, a2, .LBB109_3 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB109_1 Depth=1 -; RV64IA-NEXT: xor a5, a3, a1 -; RV64IA-NEXT: and a5, a5, a4 -; RV64IA-NEXT: xor a5, a3, a5 +; RV64IA-NEXT: xor a5, a4, a1 +; RV64IA-NEXT: and a5, a5, a6 +; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: .LBB109_3: # in Loop: Header=BB109_1 Depth=1 -; RV64IA-NEXT: sc.w.aqrl a5, a5, (a6) +; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0) ; RV64IA-NEXT: bnez a5, .LBB109_1 ; RV64IA-NEXT: # %bb.4: -; RV64IA-NEXT: srlw a0, a3, a0 +; RV64IA-NEXT: srlw a0, a4, a3 ; RV64IA-NEXT: ret %1 = atomicrmw umin i16* %a, i16 %b seq_cst ret i16 %1 @@ -11496,31 +11496,30 @@ define i32 @atomicrmw_max_i32_monotonic(i32 *%a, i32 %b) nounwind { ; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a3, 0(a0) -; RV32I-NEXT: mv s1, a1 +; RV32I-NEXT: mv s0, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: addi s2, sp, 12 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s1, a3, .LBB145_3 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: bge s0, a2, .LBB145_3 ; RV32I-NEXT: .LBB145_1: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: sw a3, 12(sp) -; RV32I-NEXT: mv a0, s0 +; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: call __atomic_compare_exchange_4 -; RV32I-NEXT: lw a3, 12(sp) +; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: bnez a0, .LBB145_4 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB145_1 Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: blt s1, a3, .LBB145_1 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: blt s0, a2, .LBB145_1 ; RV32I-NEXT: .LBB145_3: # %atomicrmw.start -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: j .LBB145_1 ; RV32I-NEXT: .LBB145_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a3 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s0, 24(sp) @@ -11541,33 +11540,33 @@ define i32 @atomicrmw_max_i32_monotonic(i32 *%a, i32 %b) nounwind { ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s3, 8(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: lwu a3, 0(a0) -; RV64I-NEXT: mv s3, a1 -; RV64I-NEXT: sext.w s1, a1 -; RV64I-NEXT: addi s2, sp, 4 +; RV64I-NEXT: mv s2, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: lwu a0, 0(a0) +; RV64I-NEXT: sext.w s0, a1 +; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: j .LBB145_2 ; RV64I-NEXT: .LBB145_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB145_2 Depth=1 -; RV64I-NEXT: sw a3, 4(sp) -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 +; RV64I-NEXT: sw a0, 4(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: call __atomic_compare_exchange_4 -; RV64I-NEXT: lw a3, 4(sp) -; RV64I-NEXT: bnez a0, .LBB145_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lw a0, 4(sp) +; RV64I-NEXT: bnez a1, .LBB145_4 ; RV64I-NEXT: .LBB145_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sext.w a0, a3 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: blt s1, a0, .LBB145_1 +; RV64I-NEXT: sext.w a1, a0 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: blt s0, a1, .LBB145_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB145_2 Depth=1 -; RV64I-NEXT: mv a2, s3 +; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB145_1 ; RV64I-NEXT: .LBB145_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -11592,31 +11591,30 @@ define i32 @atomicrmw_max_i32_acquire(i32 *%a, i32 %b) nounwind { ; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a3, 0(a0) -; RV32I-NEXT: mv s1, a1 +; RV32I-NEXT: mv s0, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: addi s2, sp, 12 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s1, a3, .LBB146_3 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: bge s0, a2, .LBB146_3 ; RV32I-NEXT: .LBB146_1: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: sw a3, 12(sp) +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a4, zero, 2 -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: call __atomic_compare_exchange_4 -; RV32I-NEXT: lw a3, 12(sp) +; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: bnez a0, .LBB146_4 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB146_1 Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: blt s1, a3, .LBB146_1 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: blt s0, a2, .LBB146_1 ; RV32I-NEXT: .LBB146_3: # %atomicrmw.start -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: j .LBB146_1 ; RV32I-NEXT: .LBB146_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a3 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s0, 24(sp) @@ -11637,33 +11635,33 @@ define i32 @atomicrmw_max_i32_acquire(i32 *%a, i32 %b) nounwind { ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s3, 8(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: lwu a3, 0(a0) -; RV64I-NEXT: mv s3, a1 -; RV64I-NEXT: sext.w s1, a1 -; RV64I-NEXT: addi s2, sp, 4 +; RV64I-NEXT: mv s2, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: lwu a0, 0(a0) +; RV64I-NEXT: sext.w s0, a1 +; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: j .LBB146_2 ; RV64I-NEXT: .LBB146_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB146_2 Depth=1 -; RV64I-NEXT: sw a3, 4(sp) +; RV64I-NEXT: sw a0, 4(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a4, zero, 2 -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: call __atomic_compare_exchange_4 -; RV64I-NEXT: lw a3, 4(sp) -; RV64I-NEXT: bnez a0, .LBB146_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lw a0, 4(sp) +; RV64I-NEXT: bnez a1, .LBB146_4 ; RV64I-NEXT: .LBB146_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sext.w a0, a3 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: blt s1, a0, .LBB146_1 +; RV64I-NEXT: sext.w a1, a0 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: blt s0, a1, .LBB146_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB146_2 Depth=1 -; RV64I-NEXT: mv a2, s3 +; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB146_1 ; RV64I-NEXT: .LBB146_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -11688,31 +11686,30 @@ define i32 @atomicrmw_max_i32_release(i32 *%a, i32 %b) nounwind { ; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a3, 0(a0) -; RV32I-NEXT: mv s1, a1 +; RV32I-NEXT: mv s0, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: addi s2, sp, 12 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s1, a3, .LBB147_3 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: bge s0, a2, .LBB147_3 ; RV32I-NEXT: .LBB147_1: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: sw a3, 12(sp) -; RV32I-NEXT: addi a3, zero, 3 -; RV32I-NEXT: mv a0, s0 +; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s2 +; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: call __atomic_compare_exchange_4 -; RV32I-NEXT: lw a3, 12(sp) +; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: bnez a0, .LBB147_4 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB147_1 Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: blt s1, a3, .LBB147_1 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: blt s0, a2, .LBB147_1 ; RV32I-NEXT: .LBB147_3: # %atomicrmw.start -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: j .LBB147_1 ; RV32I-NEXT: .LBB147_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a3 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s0, 24(sp) @@ -11733,33 +11730,33 @@ define i32 @atomicrmw_max_i32_release(i32 *%a, i32 %b) nounwind { ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s3, 8(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: lwu a3, 0(a0) -; RV64I-NEXT: mv s3, a1 -; RV64I-NEXT: sext.w s1, a1 -; RV64I-NEXT: addi s2, sp, 4 +; RV64I-NEXT: mv s2, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: lwu a0, 0(a0) +; RV64I-NEXT: sext.w s0, a1 +; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: j .LBB147_2 ; RV64I-NEXT: .LBB147_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB147_2 Depth=1 -; RV64I-NEXT: sw a3, 4(sp) +; RV64I-NEXT: sw a0, 4(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: addi a3, zero, 3 -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: call __atomic_compare_exchange_4 -; RV64I-NEXT: lw a3, 4(sp) -; RV64I-NEXT: bnez a0, .LBB147_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lw a0, 4(sp) +; RV64I-NEXT: bnez a1, .LBB147_4 ; RV64I-NEXT: .LBB147_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sext.w a0, a3 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: blt s1, a0, .LBB147_1 +; RV64I-NEXT: sext.w a1, a0 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: blt s0, a1, .LBB147_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB147_2 Depth=1 -; RV64I-NEXT: mv a2, s3 +; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB147_1 ; RV64I-NEXT: .LBB147_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -11784,31 +11781,30 @@ define i32 @atomicrmw_max_i32_acq_rel(i32 *%a, i32 %b) nounwind { ; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a3, 0(a0) -; RV32I-NEXT: mv s1, a1 +; RV32I-NEXT: mv s0, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: addi s2, sp, 12 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s1, a3, .LBB148_3 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: bge s0, a2, .LBB148_3 ; RV32I-NEXT: .LBB148_1: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: sw a3, 12(sp) +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a4, zero, 2 -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: call __atomic_compare_exchange_4 -; RV32I-NEXT: lw a3, 12(sp) +; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: bnez a0, .LBB148_4 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB148_1 Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: blt s1, a3, .LBB148_1 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: blt s0, a2, .LBB148_1 ; RV32I-NEXT: .LBB148_3: # %atomicrmw.start -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: j .LBB148_1 ; RV32I-NEXT: .LBB148_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a3 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s0, 24(sp) @@ -11829,33 +11825,33 @@ define i32 @atomicrmw_max_i32_acq_rel(i32 *%a, i32 %b) nounwind { ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s3, 8(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: lwu a3, 0(a0) -; RV64I-NEXT: mv s3, a1 -; RV64I-NEXT: sext.w s1, a1 -; RV64I-NEXT: addi s2, sp, 4 +; RV64I-NEXT: mv s2, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: lwu a0, 0(a0) +; RV64I-NEXT: sext.w s0, a1 +; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: j .LBB148_2 ; RV64I-NEXT: .LBB148_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB148_2 Depth=1 -; RV64I-NEXT: sw a3, 4(sp) +; RV64I-NEXT: sw a0, 4(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a4, zero, 2 -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: call __atomic_compare_exchange_4 -; RV64I-NEXT: lw a3, 4(sp) -; RV64I-NEXT: bnez a0, .LBB148_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lw a0, 4(sp) +; RV64I-NEXT: bnez a1, .LBB148_4 ; RV64I-NEXT: .LBB148_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sext.w a0, a3 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: blt s1, a0, .LBB148_1 +; RV64I-NEXT: sext.w a1, a0 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: blt s0, a1, .LBB148_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB148_2 Depth=1 -; RV64I-NEXT: mv a2, s3 +; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB148_1 ; RV64I-NEXT: .LBB148_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -11880,31 +11876,30 @@ define i32 @atomicrmw_max_i32_seq_cst(i32 *%a, i32 %b) nounwind { ; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a3, 0(a0) -; RV32I-NEXT: mv s1, a1 +; RV32I-NEXT: mv s0, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: addi s2, sp, 12 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s1, a3, .LBB149_3 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: bge s0, a2, .LBB149_3 ; RV32I-NEXT: .LBB149_1: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: sw a3, 12(sp) +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a4, zero, 5 -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: call __atomic_compare_exchange_4 -; RV32I-NEXT: lw a3, 12(sp) +; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: bnez a0, .LBB149_4 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB149_1 Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: blt s1, a3, .LBB149_1 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: blt s0, a2, .LBB149_1 ; RV32I-NEXT: .LBB149_3: # %atomicrmw.start -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: j .LBB149_1 ; RV32I-NEXT: .LBB149_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a3 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s0, 24(sp) @@ -11925,33 +11920,33 @@ define i32 @atomicrmw_max_i32_seq_cst(i32 *%a, i32 %b) nounwind { ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s3, 8(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: lwu a3, 0(a0) -; RV64I-NEXT: mv s3, a1 -; RV64I-NEXT: sext.w s1, a1 -; RV64I-NEXT: addi s2, sp, 4 +; RV64I-NEXT: mv s2, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: lwu a0, 0(a0) +; RV64I-NEXT: sext.w s0, a1 +; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: j .LBB149_2 ; RV64I-NEXT: .LBB149_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB149_2 Depth=1 -; RV64I-NEXT: sw a3, 4(sp) +; RV64I-NEXT: sw a0, 4(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a4, zero, 5 -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: call __atomic_compare_exchange_4 -; RV64I-NEXT: lw a3, 4(sp) -; RV64I-NEXT: bnez a0, .LBB149_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lw a0, 4(sp) +; RV64I-NEXT: bnez a1, .LBB149_4 ; RV64I-NEXT: .LBB149_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sext.w a0, a3 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: blt s1, a0, .LBB149_1 +; RV64I-NEXT: sext.w a1, a0 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: blt s0, a1, .LBB149_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB149_2 Depth=1 -; RV64I-NEXT: mv a2, s3 +; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB149_1 ; RV64I-NEXT: .LBB149_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -11976,31 +11971,30 @@ define i32 @atomicrmw_min_i32_monotonic(i32 *%a, i32 %b) nounwind { ; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a3, 0(a0) -; RV32I-NEXT: mv s1, a1 +; RV32I-NEXT: mv s0, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: addi s2, sp, 12 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: blt s1, a3, .LBB150_3 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: blt s0, a2, .LBB150_3 ; RV32I-NEXT: .LBB150_1: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: sw a3, 12(sp) -; RV32I-NEXT: mv a0, s0 +; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: call __atomic_compare_exchange_4 -; RV32I-NEXT: lw a3, 12(sp) +; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: bnez a0, .LBB150_4 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB150_1 Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s1, a3, .LBB150_1 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: bge s0, a2, .LBB150_1 ; RV32I-NEXT: .LBB150_3: # %atomicrmw.start -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: j .LBB150_1 ; RV32I-NEXT: .LBB150_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a3 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s0, 24(sp) @@ -12021,33 +12015,33 @@ define i32 @atomicrmw_min_i32_monotonic(i32 *%a, i32 %b) nounwind { ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s3, 8(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: lwu a3, 0(a0) -; RV64I-NEXT: mv s3, a1 -; RV64I-NEXT: sext.w s1, a1 -; RV64I-NEXT: addi s2, sp, 4 +; RV64I-NEXT: mv s2, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: lwu a0, 0(a0) +; RV64I-NEXT: sext.w s0, a1 +; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: j .LBB150_2 ; RV64I-NEXT: .LBB150_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB150_2 Depth=1 -; RV64I-NEXT: sw a3, 4(sp) -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 +; RV64I-NEXT: sw a0, 4(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: call __atomic_compare_exchange_4 -; RV64I-NEXT: lw a3, 4(sp) -; RV64I-NEXT: bnez a0, .LBB150_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lw a0, 4(sp) +; RV64I-NEXT: bnez a1, .LBB150_4 ; RV64I-NEXT: .LBB150_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sext.w a0, a3 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s1, a0, .LBB150_1 +; RV64I-NEXT: sext.w a1, a0 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bge s0, a1, .LBB150_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB150_2 Depth=1 -; RV64I-NEXT: mv a2, s3 +; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB150_1 ; RV64I-NEXT: .LBB150_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -12072,31 +12066,30 @@ define i32 @atomicrmw_min_i32_acquire(i32 *%a, i32 %b) nounwind { ; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a3, 0(a0) -; RV32I-NEXT: mv s1, a1 +; RV32I-NEXT: mv s0, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: addi s2, sp, 12 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: blt s1, a3, .LBB151_3 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: blt s0, a2, .LBB151_3 ; RV32I-NEXT: .LBB151_1: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: sw a3, 12(sp) +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a4, zero, 2 -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: call __atomic_compare_exchange_4 -; RV32I-NEXT: lw a3, 12(sp) +; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: bnez a0, .LBB151_4 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB151_1 Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s1, a3, .LBB151_1 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: bge s0, a2, .LBB151_1 ; RV32I-NEXT: .LBB151_3: # %atomicrmw.start -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: j .LBB151_1 ; RV32I-NEXT: .LBB151_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a3 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s0, 24(sp) @@ -12117,33 +12110,33 @@ define i32 @atomicrmw_min_i32_acquire(i32 *%a, i32 %b) nounwind { ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s3, 8(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: lwu a3, 0(a0) -; RV64I-NEXT: mv s3, a1 -; RV64I-NEXT: sext.w s1, a1 -; RV64I-NEXT: addi s2, sp, 4 +; RV64I-NEXT: mv s2, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: lwu a0, 0(a0) +; RV64I-NEXT: sext.w s0, a1 +; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: j .LBB151_2 ; RV64I-NEXT: .LBB151_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB151_2 Depth=1 -; RV64I-NEXT: sw a3, 4(sp) +; RV64I-NEXT: sw a0, 4(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a4, zero, 2 -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: call __atomic_compare_exchange_4 -; RV64I-NEXT: lw a3, 4(sp) -; RV64I-NEXT: bnez a0, .LBB151_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lw a0, 4(sp) +; RV64I-NEXT: bnez a1, .LBB151_4 ; RV64I-NEXT: .LBB151_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sext.w a0, a3 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s1, a0, .LBB151_1 +; RV64I-NEXT: sext.w a1, a0 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bge s0, a1, .LBB151_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB151_2 Depth=1 -; RV64I-NEXT: mv a2, s3 +; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB151_1 ; RV64I-NEXT: .LBB151_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -12168,31 +12161,30 @@ define i32 @atomicrmw_min_i32_release(i32 *%a, i32 %b) nounwind { ; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a3, 0(a0) -; RV32I-NEXT: mv s1, a1 +; RV32I-NEXT: mv s0, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: addi s2, sp, 12 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: blt s1, a3, .LBB152_3 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: blt s0, a2, .LBB152_3 ; RV32I-NEXT: .LBB152_1: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: sw a3, 12(sp) -; RV32I-NEXT: addi a3, zero, 3 -; RV32I-NEXT: mv a0, s0 +; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s2 +; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: call __atomic_compare_exchange_4 -; RV32I-NEXT: lw a3, 12(sp) +; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: bnez a0, .LBB152_4 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB152_1 Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s1, a3, .LBB152_1 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: bge s0, a2, .LBB152_1 ; RV32I-NEXT: .LBB152_3: # %atomicrmw.start -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: j .LBB152_1 ; RV32I-NEXT: .LBB152_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a3 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s0, 24(sp) @@ -12213,33 +12205,33 @@ define i32 @atomicrmw_min_i32_release(i32 *%a, i32 %b) nounwind { ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s3, 8(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: lwu a3, 0(a0) -; RV64I-NEXT: mv s3, a1 -; RV64I-NEXT: sext.w s1, a1 -; RV64I-NEXT: addi s2, sp, 4 +; RV64I-NEXT: mv s2, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: lwu a0, 0(a0) +; RV64I-NEXT: sext.w s0, a1 +; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: j .LBB152_2 ; RV64I-NEXT: .LBB152_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB152_2 Depth=1 -; RV64I-NEXT: sw a3, 4(sp) +; RV64I-NEXT: sw a0, 4(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: addi a3, zero, 3 -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: call __atomic_compare_exchange_4 -; RV64I-NEXT: lw a3, 4(sp) -; RV64I-NEXT: bnez a0, .LBB152_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lw a0, 4(sp) +; RV64I-NEXT: bnez a1, .LBB152_4 ; RV64I-NEXT: .LBB152_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sext.w a0, a3 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s1, a0, .LBB152_1 +; RV64I-NEXT: sext.w a1, a0 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bge s0, a1, .LBB152_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB152_2 Depth=1 -; RV64I-NEXT: mv a2, s3 +; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB152_1 ; RV64I-NEXT: .LBB152_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -12264,31 +12256,30 @@ define i32 @atomicrmw_min_i32_acq_rel(i32 *%a, i32 %b) nounwind { ; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a3, 0(a0) -; RV32I-NEXT: mv s1, a1 +; RV32I-NEXT: mv s0, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: addi s2, sp, 12 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: blt s1, a3, .LBB153_3 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: blt s0, a2, .LBB153_3 ; RV32I-NEXT: .LBB153_1: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: sw a3, 12(sp) +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a4, zero, 2 -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: call __atomic_compare_exchange_4 -; RV32I-NEXT: lw a3, 12(sp) +; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: bnez a0, .LBB153_4 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB153_1 Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s1, a3, .LBB153_1 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: bge s0, a2, .LBB153_1 ; RV32I-NEXT: .LBB153_3: # %atomicrmw.start -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: j .LBB153_1 ; RV32I-NEXT: .LBB153_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a3 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s0, 24(sp) @@ -12309,33 +12300,33 @@ define i32 @atomicrmw_min_i32_acq_rel(i32 *%a, i32 %b) nounwind { ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s3, 8(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: lwu a3, 0(a0) -; RV64I-NEXT: mv s3, a1 -; RV64I-NEXT: sext.w s1, a1 -; RV64I-NEXT: addi s2, sp, 4 +; RV64I-NEXT: mv s2, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: lwu a0, 0(a0) +; RV64I-NEXT: sext.w s0, a1 +; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: j .LBB153_2 ; RV64I-NEXT: .LBB153_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB153_2 Depth=1 -; RV64I-NEXT: sw a3, 4(sp) +; RV64I-NEXT: sw a0, 4(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a4, zero, 2 -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: call __atomic_compare_exchange_4 -; RV64I-NEXT: lw a3, 4(sp) -; RV64I-NEXT: bnez a0, .LBB153_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lw a0, 4(sp) +; RV64I-NEXT: bnez a1, .LBB153_4 ; RV64I-NEXT: .LBB153_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sext.w a0, a3 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s1, a0, .LBB153_1 +; RV64I-NEXT: sext.w a1, a0 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bge s0, a1, .LBB153_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB153_2 Depth=1 -; RV64I-NEXT: mv a2, s3 +; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB153_1 ; RV64I-NEXT: .LBB153_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -12360,31 +12351,30 @@ define i32 @atomicrmw_min_i32_seq_cst(i32 *%a, i32 %b) nounwind { ; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a3, 0(a0) -; RV32I-NEXT: mv s1, a1 +; RV32I-NEXT: mv s0, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: addi s2, sp, 12 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: blt s1, a3, .LBB154_3 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: blt s0, a2, .LBB154_3 ; RV32I-NEXT: .LBB154_1: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: sw a3, 12(sp) +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a4, zero, 5 -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: call __atomic_compare_exchange_4 -; RV32I-NEXT: lw a3, 12(sp) +; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: bnez a0, .LBB154_4 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB154_1 Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bge s1, a3, .LBB154_1 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: bge s0, a2, .LBB154_1 ; RV32I-NEXT: .LBB154_3: # %atomicrmw.start -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: j .LBB154_1 ; RV32I-NEXT: .LBB154_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a3 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s0, 24(sp) @@ -12405,33 +12395,33 @@ define i32 @atomicrmw_min_i32_seq_cst(i32 *%a, i32 %b) nounwind { ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s3, 8(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: lwu a3, 0(a0) -; RV64I-NEXT: mv s3, a1 -; RV64I-NEXT: sext.w s1, a1 -; RV64I-NEXT: addi s2, sp, 4 +; RV64I-NEXT: mv s2, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: lwu a0, 0(a0) +; RV64I-NEXT: sext.w s0, a1 +; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: j .LBB154_2 ; RV64I-NEXT: .LBB154_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB154_2 Depth=1 -; RV64I-NEXT: sw a3, 4(sp) +; RV64I-NEXT: sw a0, 4(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a4, zero, 5 -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: call __atomic_compare_exchange_4 -; RV64I-NEXT: lw a3, 4(sp) -; RV64I-NEXT: bnez a0, .LBB154_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lw a0, 4(sp) +; RV64I-NEXT: bnez a1, .LBB154_4 ; RV64I-NEXT: .LBB154_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sext.w a0, a3 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s1, a0, .LBB154_1 +; RV64I-NEXT: sext.w a1, a0 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bge s0, a1, .LBB154_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB154_2 Depth=1 -; RV64I-NEXT: mv a2, s3 +; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB154_1 ; RV64I-NEXT: .LBB154_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -12456,31 +12446,30 @@ define i32 @atomicrmw_umax_i32_monotonic(i32 *%a, i32 %b) nounwind { ; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a3, 0(a0) -; RV32I-NEXT: mv s1, a1 +; RV32I-NEXT: mv s0, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: addi s2, sp, 12 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s1, a3, .LBB155_3 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: bgeu s0, a2, .LBB155_3 ; RV32I-NEXT: .LBB155_1: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: sw a3, 12(sp) -; RV32I-NEXT: mv a0, s0 +; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: call __atomic_compare_exchange_4 -; RV32I-NEXT: lw a3, 12(sp) +; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: bnez a0, .LBB155_4 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB155_1 Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bltu s1, a3, .LBB155_1 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: bltu s0, a2, .LBB155_1 ; RV32I-NEXT: .LBB155_3: # %atomicrmw.start -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: j .LBB155_1 ; RV32I-NEXT: .LBB155_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a3 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s0, 24(sp) @@ -12501,33 +12490,33 @@ define i32 @atomicrmw_umax_i32_monotonic(i32 *%a, i32 %b) nounwind { ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s3, 8(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: lwu a3, 0(a0) -; RV64I-NEXT: mv s3, a1 -; RV64I-NEXT: sext.w s1, a1 -; RV64I-NEXT: addi s2, sp, 4 +; RV64I-NEXT: mv s2, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: lwu a0, 0(a0) +; RV64I-NEXT: sext.w s0, a1 +; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: j .LBB155_2 ; RV64I-NEXT: .LBB155_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB155_2 Depth=1 -; RV64I-NEXT: sw a3, 4(sp) -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 +; RV64I-NEXT: sw a0, 4(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: call __atomic_compare_exchange_4 -; RV64I-NEXT: lw a3, 4(sp) -; RV64I-NEXT: bnez a0, .LBB155_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lw a0, 4(sp) +; RV64I-NEXT: bnez a1, .LBB155_4 ; RV64I-NEXT: .LBB155_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sext.w a0, a3 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bltu s1, a0, .LBB155_1 +; RV64I-NEXT: sext.w a1, a0 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bltu s0, a1, .LBB155_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB155_2 Depth=1 -; RV64I-NEXT: mv a2, s3 +; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB155_1 ; RV64I-NEXT: .LBB155_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -12552,31 +12541,30 @@ define i32 @atomicrmw_umax_i32_acquire(i32 *%a, i32 %b) nounwind { ; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a3, 0(a0) -; RV32I-NEXT: mv s1, a1 +; RV32I-NEXT: mv s0, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: addi s2, sp, 12 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s1, a3, .LBB156_3 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: bgeu s0, a2, .LBB156_3 ; RV32I-NEXT: .LBB156_1: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: sw a3, 12(sp) +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a4, zero, 2 -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: call __atomic_compare_exchange_4 -; RV32I-NEXT: lw a3, 12(sp) +; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: bnez a0, .LBB156_4 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB156_1 Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bltu s1, a3, .LBB156_1 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: bltu s0, a2, .LBB156_1 ; RV32I-NEXT: .LBB156_3: # %atomicrmw.start -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: j .LBB156_1 ; RV32I-NEXT: .LBB156_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a3 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s0, 24(sp) @@ -12597,33 +12585,33 @@ define i32 @atomicrmw_umax_i32_acquire(i32 *%a, i32 %b) nounwind { ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s3, 8(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: lwu a3, 0(a0) -; RV64I-NEXT: mv s3, a1 -; RV64I-NEXT: sext.w s1, a1 -; RV64I-NEXT: addi s2, sp, 4 +; RV64I-NEXT: mv s2, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: lwu a0, 0(a0) +; RV64I-NEXT: sext.w s0, a1 +; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: j .LBB156_2 ; RV64I-NEXT: .LBB156_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB156_2 Depth=1 -; RV64I-NEXT: sw a3, 4(sp) +; RV64I-NEXT: sw a0, 4(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a4, zero, 2 -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: call __atomic_compare_exchange_4 -; RV64I-NEXT: lw a3, 4(sp) -; RV64I-NEXT: bnez a0, .LBB156_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lw a0, 4(sp) +; RV64I-NEXT: bnez a1, .LBB156_4 ; RV64I-NEXT: .LBB156_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sext.w a0, a3 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bltu s1, a0, .LBB156_1 +; RV64I-NEXT: sext.w a1, a0 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bltu s0, a1, .LBB156_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB156_2 Depth=1 -; RV64I-NEXT: mv a2, s3 +; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB156_1 ; RV64I-NEXT: .LBB156_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -12648,31 +12636,30 @@ define i32 @atomicrmw_umax_i32_release(i32 *%a, i32 %b) nounwind { ; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a3, 0(a0) -; RV32I-NEXT: mv s1, a1 +; RV32I-NEXT: mv s0, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: addi s2, sp, 12 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s1, a3, .LBB157_3 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: bgeu s0, a2, .LBB157_3 ; RV32I-NEXT: .LBB157_1: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: sw a3, 12(sp) -; RV32I-NEXT: addi a3, zero, 3 -; RV32I-NEXT: mv a0, s0 +; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s2 +; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: call __atomic_compare_exchange_4 -; RV32I-NEXT: lw a3, 12(sp) +; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: bnez a0, .LBB157_4 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB157_1 Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bltu s1, a3, .LBB157_1 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: bltu s0, a2, .LBB157_1 ; RV32I-NEXT: .LBB157_3: # %atomicrmw.start -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: j .LBB157_1 ; RV32I-NEXT: .LBB157_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a3 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s0, 24(sp) @@ -12693,33 +12680,33 @@ define i32 @atomicrmw_umax_i32_release(i32 *%a, i32 %b) nounwind { ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s3, 8(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: lwu a3, 0(a0) -; RV64I-NEXT: mv s3, a1 -; RV64I-NEXT: sext.w s1, a1 -; RV64I-NEXT: addi s2, sp, 4 +; RV64I-NEXT: mv s2, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: lwu a0, 0(a0) +; RV64I-NEXT: sext.w s0, a1 +; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: j .LBB157_2 ; RV64I-NEXT: .LBB157_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB157_2 Depth=1 -; RV64I-NEXT: sw a3, 4(sp) +; RV64I-NEXT: sw a0, 4(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: addi a3, zero, 3 -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: call __atomic_compare_exchange_4 -; RV64I-NEXT: lw a3, 4(sp) -; RV64I-NEXT: bnez a0, .LBB157_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lw a0, 4(sp) +; RV64I-NEXT: bnez a1, .LBB157_4 ; RV64I-NEXT: .LBB157_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sext.w a0, a3 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bltu s1, a0, .LBB157_1 +; RV64I-NEXT: sext.w a1, a0 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bltu s0, a1, .LBB157_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB157_2 Depth=1 -; RV64I-NEXT: mv a2, s3 +; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB157_1 ; RV64I-NEXT: .LBB157_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -12744,31 +12731,30 @@ define i32 @atomicrmw_umax_i32_acq_rel(i32 *%a, i32 %b) nounwind { ; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a3, 0(a0) -; RV32I-NEXT: mv s1, a1 +; RV32I-NEXT: mv s0, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: addi s2, sp, 12 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s1, a3, .LBB158_3 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: bgeu s0, a2, .LBB158_3 ; RV32I-NEXT: .LBB158_1: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: sw a3, 12(sp) +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a4, zero, 2 -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: call __atomic_compare_exchange_4 -; RV32I-NEXT: lw a3, 12(sp) +; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: bnez a0, .LBB158_4 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB158_1 Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bltu s1, a3, .LBB158_1 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: bltu s0, a2, .LBB158_1 ; RV32I-NEXT: .LBB158_3: # %atomicrmw.start -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: j .LBB158_1 ; RV32I-NEXT: .LBB158_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a3 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s0, 24(sp) @@ -12789,33 +12775,33 @@ define i32 @atomicrmw_umax_i32_acq_rel(i32 *%a, i32 %b) nounwind { ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s3, 8(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: lwu a3, 0(a0) -; RV64I-NEXT: mv s3, a1 -; RV64I-NEXT: sext.w s1, a1 -; RV64I-NEXT: addi s2, sp, 4 +; RV64I-NEXT: mv s2, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: lwu a0, 0(a0) +; RV64I-NEXT: sext.w s0, a1 +; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: j .LBB158_2 ; RV64I-NEXT: .LBB158_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB158_2 Depth=1 -; RV64I-NEXT: sw a3, 4(sp) +; RV64I-NEXT: sw a0, 4(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a4, zero, 2 -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: call __atomic_compare_exchange_4 -; RV64I-NEXT: lw a3, 4(sp) -; RV64I-NEXT: bnez a0, .LBB158_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lw a0, 4(sp) +; RV64I-NEXT: bnez a1, .LBB158_4 ; RV64I-NEXT: .LBB158_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sext.w a0, a3 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bltu s1, a0, .LBB158_1 +; RV64I-NEXT: sext.w a1, a0 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bltu s0, a1, .LBB158_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB158_2 Depth=1 -; RV64I-NEXT: mv a2, s3 +; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB158_1 ; RV64I-NEXT: .LBB158_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -12840,31 +12826,30 @@ define i32 @atomicrmw_umax_i32_seq_cst(i32 *%a, i32 %b) nounwind { ; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a3, 0(a0) -; RV32I-NEXT: mv s1, a1 +; RV32I-NEXT: mv s0, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: addi s2, sp, 12 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s1, a3, .LBB159_3 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: bgeu s0, a2, .LBB159_3 ; RV32I-NEXT: .LBB159_1: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: sw a3, 12(sp) +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a4, zero, 5 -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: call __atomic_compare_exchange_4 -; RV32I-NEXT: lw a3, 12(sp) +; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: bnez a0, .LBB159_4 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB159_1 Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bltu s1, a3, .LBB159_1 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: bltu s0, a2, .LBB159_1 ; RV32I-NEXT: .LBB159_3: # %atomicrmw.start -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: j .LBB159_1 ; RV32I-NEXT: .LBB159_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a3 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s0, 24(sp) @@ -12885,33 +12870,33 @@ define i32 @atomicrmw_umax_i32_seq_cst(i32 *%a, i32 %b) nounwind { ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s3, 8(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: lwu a3, 0(a0) -; RV64I-NEXT: mv s3, a1 -; RV64I-NEXT: sext.w s1, a1 -; RV64I-NEXT: addi s2, sp, 4 +; RV64I-NEXT: mv s2, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: lwu a0, 0(a0) +; RV64I-NEXT: sext.w s0, a1 +; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: j .LBB159_2 ; RV64I-NEXT: .LBB159_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB159_2 Depth=1 -; RV64I-NEXT: sw a3, 4(sp) +; RV64I-NEXT: sw a0, 4(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a4, zero, 5 -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: call __atomic_compare_exchange_4 -; RV64I-NEXT: lw a3, 4(sp) -; RV64I-NEXT: bnez a0, .LBB159_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lw a0, 4(sp) +; RV64I-NEXT: bnez a1, .LBB159_4 ; RV64I-NEXT: .LBB159_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sext.w a0, a3 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bltu s1, a0, .LBB159_1 +; RV64I-NEXT: sext.w a1, a0 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bltu s0, a1, .LBB159_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB159_2 Depth=1 -; RV64I-NEXT: mv a2, s3 +; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB159_1 ; RV64I-NEXT: .LBB159_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -12936,31 +12921,30 @@ define i32 @atomicrmw_umin_i32_monotonic(i32 *%a, i32 %b) nounwind { ; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a3, 0(a0) -; RV32I-NEXT: mv s1, a1 +; RV32I-NEXT: mv s0, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: addi s2, sp, 12 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bltu s1, a3, .LBB160_3 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: bltu s0, a2, .LBB160_3 ; RV32I-NEXT: .LBB160_1: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: sw a3, 12(sp) -; RV32I-NEXT: mv a0, s0 +; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: call __atomic_compare_exchange_4 -; RV32I-NEXT: lw a3, 12(sp) +; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: bnez a0, .LBB160_4 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB160_1 Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s1, a3, .LBB160_1 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: bgeu s0, a2, .LBB160_1 ; RV32I-NEXT: .LBB160_3: # %atomicrmw.start -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: j .LBB160_1 ; RV32I-NEXT: .LBB160_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a3 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s0, 24(sp) @@ -12981,33 +12965,33 @@ define i32 @atomicrmw_umin_i32_monotonic(i32 *%a, i32 %b) nounwind { ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s3, 8(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: lwu a3, 0(a0) -; RV64I-NEXT: mv s3, a1 -; RV64I-NEXT: sext.w s1, a1 -; RV64I-NEXT: addi s2, sp, 4 +; RV64I-NEXT: mv s2, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: lwu a0, 0(a0) +; RV64I-NEXT: sext.w s0, a1 +; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: j .LBB160_2 ; RV64I-NEXT: .LBB160_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB160_2 Depth=1 -; RV64I-NEXT: sw a3, 4(sp) -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 +; RV64I-NEXT: sw a0, 4(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: call __atomic_compare_exchange_4 -; RV64I-NEXT: lw a3, 4(sp) -; RV64I-NEXT: bnez a0, .LBB160_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lw a0, 4(sp) +; RV64I-NEXT: bnez a1, .LBB160_4 ; RV64I-NEXT: .LBB160_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sext.w a0, a3 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s1, a0, .LBB160_1 +; RV64I-NEXT: sext.w a1, a0 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bgeu s0, a1, .LBB160_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB160_2 Depth=1 -; RV64I-NEXT: mv a2, s3 +; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB160_1 ; RV64I-NEXT: .LBB160_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -13032,31 +13016,30 @@ define i32 @atomicrmw_umin_i32_acquire(i32 *%a, i32 %b) nounwind { ; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a3, 0(a0) -; RV32I-NEXT: mv s1, a1 +; RV32I-NEXT: mv s0, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: addi s2, sp, 12 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bltu s1, a3, .LBB161_3 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: bltu s0, a2, .LBB161_3 ; RV32I-NEXT: .LBB161_1: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: sw a3, 12(sp) +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: addi a3, zero, 2 ; RV32I-NEXT: addi a4, zero, 2 -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: call __atomic_compare_exchange_4 -; RV32I-NEXT: lw a3, 12(sp) +; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: bnez a0, .LBB161_4 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB161_1 Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s1, a3, .LBB161_1 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: bgeu s0, a2, .LBB161_1 ; RV32I-NEXT: .LBB161_3: # %atomicrmw.start -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: j .LBB161_1 ; RV32I-NEXT: .LBB161_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a3 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s0, 24(sp) @@ -13077,33 +13060,33 @@ define i32 @atomicrmw_umin_i32_acquire(i32 *%a, i32 %b) nounwind { ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s3, 8(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: lwu a3, 0(a0) -; RV64I-NEXT: mv s3, a1 -; RV64I-NEXT: sext.w s1, a1 -; RV64I-NEXT: addi s2, sp, 4 +; RV64I-NEXT: mv s2, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: lwu a0, 0(a0) +; RV64I-NEXT: sext.w s0, a1 +; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: j .LBB161_2 ; RV64I-NEXT: .LBB161_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB161_2 Depth=1 -; RV64I-NEXT: sw a3, 4(sp) +; RV64I-NEXT: sw a0, 4(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a4, zero, 2 -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: call __atomic_compare_exchange_4 -; RV64I-NEXT: lw a3, 4(sp) -; RV64I-NEXT: bnez a0, .LBB161_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lw a0, 4(sp) +; RV64I-NEXT: bnez a1, .LBB161_4 ; RV64I-NEXT: .LBB161_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sext.w a0, a3 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s1, a0, .LBB161_1 +; RV64I-NEXT: sext.w a1, a0 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bgeu s0, a1, .LBB161_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB161_2 Depth=1 -; RV64I-NEXT: mv a2, s3 +; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB161_1 ; RV64I-NEXT: .LBB161_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -13128,31 +13111,30 @@ define i32 @atomicrmw_umin_i32_release(i32 *%a, i32 %b) nounwind { ; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a3, 0(a0) -; RV32I-NEXT: mv s1, a1 +; RV32I-NEXT: mv s0, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: addi s2, sp, 12 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bltu s1, a3, .LBB162_3 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: bltu s0, a2, .LBB162_3 ; RV32I-NEXT: .LBB162_1: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: sw a3, 12(sp) -; RV32I-NEXT: addi a3, zero, 3 -; RV32I-NEXT: mv a0, s0 +; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s2 +; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: call __atomic_compare_exchange_4 -; RV32I-NEXT: lw a3, 12(sp) +; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: bnez a0, .LBB162_4 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB162_1 Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s1, a3, .LBB162_1 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: bgeu s0, a2, .LBB162_1 ; RV32I-NEXT: .LBB162_3: # %atomicrmw.start -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: j .LBB162_1 ; RV32I-NEXT: .LBB162_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a3 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s0, 24(sp) @@ -13173,33 +13155,33 @@ define i32 @atomicrmw_umin_i32_release(i32 *%a, i32 %b) nounwind { ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s3, 8(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: lwu a3, 0(a0) -; RV64I-NEXT: mv s3, a1 -; RV64I-NEXT: sext.w s1, a1 -; RV64I-NEXT: addi s2, sp, 4 +; RV64I-NEXT: mv s2, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: lwu a0, 0(a0) +; RV64I-NEXT: sext.w s0, a1 +; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: j .LBB162_2 ; RV64I-NEXT: .LBB162_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB162_2 Depth=1 -; RV64I-NEXT: sw a3, 4(sp) +; RV64I-NEXT: sw a0, 4(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: addi a3, zero, 3 -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: call __atomic_compare_exchange_4 -; RV64I-NEXT: lw a3, 4(sp) -; RV64I-NEXT: bnez a0, .LBB162_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lw a0, 4(sp) +; RV64I-NEXT: bnez a1, .LBB162_4 ; RV64I-NEXT: .LBB162_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sext.w a0, a3 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s1, a0, .LBB162_1 +; RV64I-NEXT: sext.w a1, a0 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bgeu s0, a1, .LBB162_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB162_2 Depth=1 -; RV64I-NEXT: mv a2, s3 +; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB162_1 ; RV64I-NEXT: .LBB162_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -13224,31 +13206,30 @@ define i32 @atomicrmw_umin_i32_acq_rel(i32 *%a, i32 %b) nounwind { ; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a3, 0(a0) -; RV32I-NEXT: mv s1, a1 +; RV32I-NEXT: mv s0, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: addi s2, sp, 12 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bltu s1, a3, .LBB163_3 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: bltu s0, a2, .LBB163_3 ; RV32I-NEXT: .LBB163_1: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: sw a3, 12(sp) +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: addi a3, zero, 4 ; RV32I-NEXT: addi a4, zero, 2 -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: call __atomic_compare_exchange_4 -; RV32I-NEXT: lw a3, 12(sp) +; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: bnez a0, .LBB163_4 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB163_1 Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s1, a3, .LBB163_1 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: bgeu s0, a2, .LBB163_1 ; RV32I-NEXT: .LBB163_3: # %atomicrmw.start -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: j .LBB163_1 ; RV32I-NEXT: .LBB163_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a3 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s0, 24(sp) @@ -13269,33 +13250,33 @@ define i32 @atomicrmw_umin_i32_acq_rel(i32 *%a, i32 %b) nounwind { ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s3, 8(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: lwu a3, 0(a0) -; RV64I-NEXT: mv s3, a1 -; RV64I-NEXT: sext.w s1, a1 -; RV64I-NEXT: addi s2, sp, 4 +; RV64I-NEXT: mv s2, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: lwu a0, 0(a0) +; RV64I-NEXT: sext.w s0, a1 +; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: j .LBB163_2 ; RV64I-NEXT: .LBB163_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB163_2 Depth=1 -; RV64I-NEXT: sw a3, 4(sp) +; RV64I-NEXT: sw a0, 4(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a4, zero, 2 -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: call __atomic_compare_exchange_4 -; RV64I-NEXT: lw a3, 4(sp) -; RV64I-NEXT: bnez a0, .LBB163_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lw a0, 4(sp) +; RV64I-NEXT: bnez a1, .LBB163_4 ; RV64I-NEXT: .LBB163_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sext.w a0, a3 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s1, a0, .LBB163_1 +; RV64I-NEXT: sext.w a1, a0 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bgeu s0, a1, .LBB163_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB163_2 Depth=1 -; RV64I-NEXT: mv a2, s3 +; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB163_1 ; RV64I-NEXT: .LBB163_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -13320,31 +13301,30 @@ define i32 @atomicrmw_umin_i32_seq_cst(i32 *%a, i32 %b) nounwind { ; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a3, 0(a0) -; RV32I-NEXT: mv s1, a1 +; RV32I-NEXT: mv s0, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: addi s2, sp, 12 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bltu s1, a3, .LBB164_3 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: bltu s0, a2, .LBB164_3 ; RV32I-NEXT: .LBB164_1: # %atomicrmw.start ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV32I-NEXT: sw a3, 12(sp) +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: addi a3, zero, 5 ; RV32I-NEXT: addi a4, zero, 5 -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: call __atomic_compare_exchange_4 -; RV32I-NEXT: lw a3, 12(sp) +; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: bnez a0, .LBB164_4 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start ; RV32I-NEXT: # in Loop: Header=BB164_1 Depth=1 -; RV32I-NEXT: mv a2, a3 -; RV32I-NEXT: bgeu s1, a3, .LBB164_1 +; RV32I-NEXT: sw a2, 12(sp) +; RV32I-NEXT: bgeu s0, a2, .LBB164_1 ; RV32I-NEXT: .LBB164_3: # %atomicrmw.start -; RV32I-NEXT: mv a2, s1 +; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: j .LBB164_1 ; RV32I-NEXT: .LBB164_4: # %atomicrmw.end -; RV32I-NEXT: mv a0, a3 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s0, 24(sp) @@ -13365,33 +13345,33 @@ define i32 @atomicrmw_umin_i32_seq_cst(i32 *%a, i32 %b) nounwind { ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s3, 8(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: lwu a3, 0(a0) -; RV64I-NEXT: mv s3, a1 -; RV64I-NEXT: sext.w s1, a1 -; RV64I-NEXT: addi s2, sp, 4 +; RV64I-NEXT: mv s2, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: lwu a0, 0(a0) +; RV64I-NEXT: sext.w s0, a1 +; RV64I-NEXT: addi s3, sp, 4 ; RV64I-NEXT: j .LBB164_2 ; RV64I-NEXT: .LBB164_1: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB164_2 Depth=1 -; RV64I-NEXT: sw a3, 4(sp) +; RV64I-NEXT: sw a0, 4(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a4, zero, 5 -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: call __atomic_compare_exchange_4 -; RV64I-NEXT: lw a3, 4(sp) -; RV64I-NEXT: bnez a0, .LBB164_4 +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: lw a0, 4(sp) +; RV64I-NEXT: bnez a1, .LBB164_4 ; RV64I-NEXT: .LBB164_2: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sext.w a0, a3 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s1, a0, .LBB164_1 +; RV64I-NEXT: sext.w a1, a0 +; RV64I-NEXT: mv a2, a0 +; RV64I-NEXT: bgeu s0, a1, .LBB164_1 ; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB164_2 Depth=1 -; RV64I-NEXT: mv a2, s3 +; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: j .LBB164_1 ; RV64I-NEXT: .LBB164_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) @@ -14822,43 +14802,41 @@ define i64 @atomicrmw_max_i64_monotonic(i64 *%a, i64 %b) nounwind { ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s3, 12(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a5, 4(a0) -; RV32I-NEXT: lw a4, 0(a0) -; RV32I-NEXT: mv s1, a2 +; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s2, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a1, 4(a0) +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s3, sp -; RV32I-NEXT: bne a5, s1, .LBB200_3 +; RV32I-NEXT: bne a1, s0, .LBB200_3 ; RV32I-NEXT: j .LBB200_4 ; RV32I-NEXT: .LBB200_1: # %atomicrmw.start -; RV32I-NEXT: sw a4, 0(sp) -; RV32I-NEXT: sw a5, 4(sp) -; RV32I-NEXT: mv a0, s0 +; RV32I-NEXT: sw a1, 4(sp) +; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: call __atomic_compare_exchange_8 -; RV32I-NEXT: lw a5, 4(sp) -; RV32I-NEXT: lw a4, 0(sp) +; RV32I-NEXT: lw a1, 4(sp) +; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: bnez a0, .LBB200_7 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start -; RV32I-NEXT: beq a5, s1, .LBB200_4 +; RV32I-NEXT: beq a1, s0, .LBB200_4 ; RV32I-NEXT: .LBB200_3: # %atomicrmw.start -; RV32I-NEXT: slt a0, s1, a5 +; RV32I-NEXT: slt a0, s0, a1 ; RV32I-NEXT: j .LBB200_5 ; RV32I-NEXT: .LBB200_4: -; RV32I-NEXT: sltu a0, s2, a4 +; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: .LBB200_5: # %atomicrmw.start -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 +; RV32I-NEXT: sw a2, 0(sp) +; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: bnez a0, .LBB200_1 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: mv a2, s2 -; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: j .LBB200_1 ; RV32I-NEXT: .LBB200_7: # %atomicrmw.end -; RV32I-NEXT: mv a0, a4 -; RV32I-NEXT: mv a1, a5 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -14875,43 +14853,41 @@ define i64 @atomicrmw_max_i64_monotonic(i64 *%a, i64 %b) nounwind { ; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s3, 12(sp) -; RV32IA-NEXT: mv s0, a0 -; RV32IA-NEXT: lw a5, 4(a0) -; RV32IA-NEXT: lw a4, 0(a0) -; RV32IA-NEXT: mv s1, a2 +; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s2, a1 +; RV32IA-NEXT: mv s1, a0 +; RV32IA-NEXT: lw a1, 4(a0) +; RV32IA-NEXT: lw a2, 0(a0) ; RV32IA-NEXT: mv s3, sp -; RV32IA-NEXT: bne a5, s1, .LBB200_3 +; RV32IA-NEXT: bne a1, s0, .LBB200_3 ; RV32IA-NEXT: j .LBB200_4 ; RV32IA-NEXT: .LBB200_1: # %atomicrmw.start -; RV32IA-NEXT: sw a4, 0(sp) -; RV32IA-NEXT: sw a5, 4(sp) -; RV32IA-NEXT: mv a0, s0 +; RV32IA-NEXT: sw a1, 4(sp) +; RV32IA-NEXT: mv a0, s1 ; RV32IA-NEXT: mv a1, s3 ; RV32IA-NEXT: mv a4, zero ; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: call __atomic_compare_exchange_8 -; RV32IA-NEXT: lw a5, 4(sp) -; RV32IA-NEXT: lw a4, 0(sp) +; RV32IA-NEXT: lw a1, 4(sp) +; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: bnez a0, .LBB200_7 ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start -; RV32IA-NEXT: beq a5, s1, .LBB200_4 +; RV32IA-NEXT: beq a1, s0, .LBB200_4 ; RV32IA-NEXT: .LBB200_3: # %atomicrmw.start -; RV32IA-NEXT: slt a0, s1, a5 +; RV32IA-NEXT: slt a0, s0, a1 ; RV32IA-NEXT: j .LBB200_5 ; RV32IA-NEXT: .LBB200_4: -; RV32IA-NEXT: sltu a0, s2, a4 +; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: .LBB200_5: # %atomicrmw.start -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sw a2, 0(sp) +; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: bnez a0, .LBB200_1 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: mv a2, s2 -; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: j .LBB200_1 ; RV32IA-NEXT: .LBB200_7: # %atomicrmw.end -; RV32IA-NEXT: mv a0, a4 -; RV32IA-NEXT: mv a1, a5 +; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s1, 20(sp) @@ -14927,31 +14903,30 @@ define i64 @atomicrmw_max_i64_monotonic(i64 *%a, i64 %b) nounwind { ; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: ld a3, 0(a0) -; RV64I-NEXT: mv s1, a1 +; RV64I-NEXT: mv s0, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: addi s2, sp, 8 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s1, a3, .LBB200_3 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: bge s0, a2, .LBB200_3 ; RV64I-NEXT: .LBB200_1: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sd a3, 8(sp) -; RV64I-NEXT: mv a0, s0 +; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: call __atomic_compare_exchange_8 -; RV64I-NEXT: ld a3, 8(sp) +; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: bnez a0, .LBB200_4 ; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB200_1 Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: blt s1, a3, .LBB200_1 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: blt s0, a2, .LBB200_1 ; RV64I-NEXT: .LBB200_3: # %atomicrmw.start -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: j .LBB200_1 ; RV64I-NEXT: .LBB200_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 +; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s0, 32(sp) @@ -14976,43 +14951,41 @@ define i64 @atomicrmw_max_i64_acquire(i64 *%a, i64 %b) nounwind { ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s3, 12(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a5, 4(a0) -; RV32I-NEXT: lw a4, 0(a0) -; RV32I-NEXT: mv s1, a2 +; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s2, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a1, 4(a0) +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s3, sp -; RV32I-NEXT: bne a5, s1, .LBB201_3 +; RV32I-NEXT: bne a1, s0, .LBB201_3 ; RV32I-NEXT: j .LBB201_4 ; RV32I-NEXT: .LBB201_1: # %atomicrmw.start -; RV32I-NEXT: sw a4, 0(sp) -; RV32I-NEXT: sw a5, 4(sp) +; RV32I-NEXT: sw a1, 4(sp) +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a5, zero, 2 -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: call __atomic_compare_exchange_8 -; RV32I-NEXT: lw a5, 4(sp) -; RV32I-NEXT: lw a4, 0(sp) +; RV32I-NEXT: lw a1, 4(sp) +; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: bnez a0, .LBB201_7 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start -; RV32I-NEXT: beq a5, s1, .LBB201_4 +; RV32I-NEXT: beq a1, s0, .LBB201_4 ; RV32I-NEXT: .LBB201_3: # %atomicrmw.start -; RV32I-NEXT: slt a0, s1, a5 +; RV32I-NEXT: slt a0, s0, a1 ; RV32I-NEXT: j .LBB201_5 ; RV32I-NEXT: .LBB201_4: -; RV32I-NEXT: sltu a0, s2, a4 +; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: .LBB201_5: # %atomicrmw.start -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 +; RV32I-NEXT: sw a2, 0(sp) +; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: bnez a0, .LBB201_1 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: mv a2, s2 -; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: j .LBB201_1 ; RV32I-NEXT: .LBB201_7: # %atomicrmw.end -; RV32I-NEXT: mv a0, a4 -; RV32I-NEXT: mv a1, a5 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -15029,43 +15002,41 @@ define i64 @atomicrmw_max_i64_acquire(i64 *%a, i64 %b) nounwind { ; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s3, 12(sp) -; RV32IA-NEXT: mv s0, a0 -; RV32IA-NEXT: lw a5, 4(a0) -; RV32IA-NEXT: lw a4, 0(a0) -; RV32IA-NEXT: mv s1, a2 +; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s2, a1 +; RV32IA-NEXT: mv s1, a0 +; RV32IA-NEXT: lw a1, 4(a0) +; RV32IA-NEXT: lw a2, 0(a0) ; RV32IA-NEXT: mv s3, sp -; RV32IA-NEXT: bne a5, s1, .LBB201_3 +; RV32IA-NEXT: bne a1, s0, .LBB201_3 ; RV32IA-NEXT: j .LBB201_4 ; RV32IA-NEXT: .LBB201_1: # %atomicrmw.start -; RV32IA-NEXT: sw a4, 0(sp) -; RV32IA-NEXT: sw a5, 4(sp) +; RV32IA-NEXT: sw a1, 4(sp) +; RV32IA-NEXT: mv a0, s1 +; RV32IA-NEXT: mv a1, s3 ; RV32IA-NEXT: addi a4, zero, 2 ; RV32IA-NEXT: addi a5, zero, 2 -; RV32IA-NEXT: mv a0, s0 -; RV32IA-NEXT: mv a1, s3 ; RV32IA-NEXT: call __atomic_compare_exchange_8 -; RV32IA-NEXT: lw a5, 4(sp) -; RV32IA-NEXT: lw a4, 0(sp) +; RV32IA-NEXT: lw a1, 4(sp) +; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: bnez a0, .LBB201_7 ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start -; RV32IA-NEXT: beq a5, s1, .LBB201_4 +; RV32IA-NEXT: beq a1, s0, .LBB201_4 ; RV32IA-NEXT: .LBB201_3: # %atomicrmw.start -; RV32IA-NEXT: slt a0, s1, a5 +; RV32IA-NEXT: slt a0, s0, a1 ; RV32IA-NEXT: j .LBB201_5 ; RV32IA-NEXT: .LBB201_4: -; RV32IA-NEXT: sltu a0, s2, a4 +; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: .LBB201_5: # %atomicrmw.start -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sw a2, 0(sp) +; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: bnez a0, .LBB201_1 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: mv a2, s2 -; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: j .LBB201_1 ; RV32IA-NEXT: .LBB201_7: # %atomicrmw.end -; RV32IA-NEXT: mv a0, a4 -; RV32IA-NEXT: mv a1, a5 +; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s1, 20(sp) @@ -15081,31 +15052,30 @@ define i64 @atomicrmw_max_i64_acquire(i64 *%a, i64 %b) nounwind { ; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: ld a3, 0(a0) -; RV64I-NEXT: mv s1, a1 +; RV64I-NEXT: mv s0, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: addi s2, sp, 8 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s1, a3, .LBB201_3 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: bge s0, a2, .LBB201_3 ; RV64I-NEXT: .LBB201_1: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sd a3, 8(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a4, zero, 2 -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: call __atomic_compare_exchange_8 -; RV64I-NEXT: ld a3, 8(sp) +; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: bnez a0, .LBB201_4 ; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB201_1 Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: blt s1, a3, .LBB201_1 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: blt s0, a2, .LBB201_1 ; RV64I-NEXT: .LBB201_3: # %atomicrmw.start -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: j .LBB201_1 ; RV64I-NEXT: .LBB201_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 +; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s0, 32(sp) @@ -15130,43 +15100,41 @@ define i64 @atomicrmw_max_i64_release(i64 *%a, i64 %b) nounwind { ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s3, 12(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a5, 4(a0) -; RV32I-NEXT: lw a4, 0(a0) -; RV32I-NEXT: mv s1, a2 +; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s2, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a1, 4(a0) +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s3, sp -; RV32I-NEXT: bne a5, s1, .LBB202_3 +; RV32I-NEXT: bne a1, s0, .LBB202_3 ; RV32I-NEXT: j .LBB202_4 ; RV32I-NEXT: .LBB202_1: # %atomicrmw.start -; RV32I-NEXT: sw a4, 0(sp) -; RV32I-NEXT: sw a5, 4(sp) -; RV32I-NEXT: addi a4, zero, 3 -; RV32I-NEXT: mv a0, s0 +; RV32I-NEXT: sw a1, 4(sp) +; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s3 +; RV32I-NEXT: addi a4, zero, 3 ; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: call __atomic_compare_exchange_8 -; RV32I-NEXT: lw a5, 4(sp) -; RV32I-NEXT: lw a4, 0(sp) +; RV32I-NEXT: lw a1, 4(sp) +; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: bnez a0, .LBB202_7 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start -; RV32I-NEXT: beq a5, s1, .LBB202_4 +; RV32I-NEXT: beq a1, s0, .LBB202_4 ; RV32I-NEXT: .LBB202_3: # %atomicrmw.start -; RV32I-NEXT: slt a0, s1, a5 +; RV32I-NEXT: slt a0, s0, a1 ; RV32I-NEXT: j .LBB202_5 ; RV32I-NEXT: .LBB202_4: -; RV32I-NEXT: sltu a0, s2, a4 +; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: .LBB202_5: # %atomicrmw.start -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 +; RV32I-NEXT: sw a2, 0(sp) +; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: bnez a0, .LBB202_1 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: mv a2, s2 -; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: j .LBB202_1 ; RV32I-NEXT: .LBB202_7: # %atomicrmw.end -; RV32I-NEXT: mv a0, a4 -; RV32I-NEXT: mv a1, a5 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -15183,43 +15151,41 @@ define i64 @atomicrmw_max_i64_release(i64 *%a, i64 %b) nounwind { ; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s3, 12(sp) -; RV32IA-NEXT: mv s0, a0 -; RV32IA-NEXT: lw a5, 4(a0) -; RV32IA-NEXT: lw a4, 0(a0) -; RV32IA-NEXT: mv s1, a2 +; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s2, a1 +; RV32IA-NEXT: mv s1, a0 +; RV32IA-NEXT: lw a1, 4(a0) +; RV32IA-NEXT: lw a2, 0(a0) ; RV32IA-NEXT: mv s3, sp -; RV32IA-NEXT: bne a5, s1, .LBB202_3 +; RV32IA-NEXT: bne a1, s0, .LBB202_3 ; RV32IA-NEXT: j .LBB202_4 ; RV32IA-NEXT: .LBB202_1: # %atomicrmw.start -; RV32IA-NEXT: sw a4, 0(sp) -; RV32IA-NEXT: sw a5, 4(sp) -; RV32IA-NEXT: addi a4, zero, 3 -; RV32IA-NEXT: mv a0, s0 +; RV32IA-NEXT: sw a1, 4(sp) +; RV32IA-NEXT: mv a0, s1 ; RV32IA-NEXT: mv a1, s3 +; RV32IA-NEXT: addi a4, zero, 3 ; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: call __atomic_compare_exchange_8 -; RV32IA-NEXT: lw a5, 4(sp) -; RV32IA-NEXT: lw a4, 0(sp) +; RV32IA-NEXT: lw a1, 4(sp) +; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: bnez a0, .LBB202_7 ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start -; RV32IA-NEXT: beq a5, s1, .LBB202_4 +; RV32IA-NEXT: beq a1, s0, .LBB202_4 ; RV32IA-NEXT: .LBB202_3: # %atomicrmw.start -; RV32IA-NEXT: slt a0, s1, a5 +; RV32IA-NEXT: slt a0, s0, a1 ; RV32IA-NEXT: j .LBB202_5 ; RV32IA-NEXT: .LBB202_4: -; RV32IA-NEXT: sltu a0, s2, a4 +; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: .LBB202_5: # %atomicrmw.start -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sw a2, 0(sp) +; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: bnez a0, .LBB202_1 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: mv a2, s2 -; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: j .LBB202_1 ; RV32IA-NEXT: .LBB202_7: # %atomicrmw.end -; RV32IA-NEXT: mv a0, a4 -; RV32IA-NEXT: mv a1, a5 +; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s1, 20(sp) @@ -15235,31 +15201,30 @@ define i64 @atomicrmw_max_i64_release(i64 *%a, i64 %b) nounwind { ; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: ld a3, 0(a0) -; RV64I-NEXT: mv s1, a1 +; RV64I-NEXT: mv s0, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: addi s2, sp, 8 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s1, a3, .LBB202_3 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: bge s0, a2, .LBB202_3 ; RV64I-NEXT: .LBB202_1: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sd a3, 8(sp) -; RV64I-NEXT: addi a3, zero, 3 -; RV64I-NEXT: mv a0, s0 +; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s2 +; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: call __atomic_compare_exchange_8 -; RV64I-NEXT: ld a3, 8(sp) +; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: bnez a0, .LBB202_4 ; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB202_1 Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: blt s1, a3, .LBB202_1 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: blt s0, a2, .LBB202_1 ; RV64I-NEXT: .LBB202_3: # %atomicrmw.start -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: j .LBB202_1 ; RV64I-NEXT: .LBB202_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 +; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s0, 32(sp) @@ -15284,43 +15249,41 @@ define i64 @atomicrmw_max_i64_acq_rel(i64 *%a, i64 %b) nounwind { ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s3, 12(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a5, 4(a0) -; RV32I-NEXT: lw a4, 0(a0) -; RV32I-NEXT: mv s1, a2 +; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s2, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a1, 4(a0) +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s3, sp -; RV32I-NEXT: bne a5, s1, .LBB203_3 +; RV32I-NEXT: bne a1, s0, .LBB203_3 ; RV32I-NEXT: j .LBB203_4 ; RV32I-NEXT: .LBB203_1: # %atomicrmw.start -; RV32I-NEXT: sw a4, 0(sp) -; RV32I-NEXT: sw a5, 4(sp) +; RV32I-NEXT: sw a1, 4(sp) +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: addi a4, zero, 4 ; RV32I-NEXT: addi a5, zero, 2 -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: call __atomic_compare_exchange_8 -; RV32I-NEXT: lw a5, 4(sp) -; RV32I-NEXT: lw a4, 0(sp) +; RV32I-NEXT: lw a1, 4(sp) +; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: bnez a0, .LBB203_7 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start -; RV32I-NEXT: beq a5, s1, .LBB203_4 +; RV32I-NEXT: beq a1, s0, .LBB203_4 ; RV32I-NEXT: .LBB203_3: # %atomicrmw.start -; RV32I-NEXT: slt a0, s1, a5 +; RV32I-NEXT: slt a0, s0, a1 ; RV32I-NEXT: j .LBB203_5 ; RV32I-NEXT: .LBB203_4: -; RV32I-NEXT: sltu a0, s2, a4 +; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: .LBB203_5: # %atomicrmw.start -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 +; RV32I-NEXT: sw a2, 0(sp) +; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: bnez a0, .LBB203_1 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: mv a2, s2 -; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: j .LBB203_1 ; RV32I-NEXT: .LBB203_7: # %atomicrmw.end -; RV32I-NEXT: mv a0, a4 -; RV32I-NEXT: mv a1, a5 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -15337,43 +15300,41 @@ define i64 @atomicrmw_max_i64_acq_rel(i64 *%a, i64 %b) nounwind { ; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s3, 12(sp) -; RV32IA-NEXT: mv s0, a0 -; RV32IA-NEXT: lw a5, 4(a0) -; RV32IA-NEXT: lw a4, 0(a0) -; RV32IA-NEXT: mv s1, a2 +; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s2, a1 +; RV32IA-NEXT: mv s1, a0 +; RV32IA-NEXT: lw a1, 4(a0) +; RV32IA-NEXT: lw a2, 0(a0) ; RV32IA-NEXT: mv s3, sp -; RV32IA-NEXT: bne a5, s1, .LBB203_3 +; RV32IA-NEXT: bne a1, s0, .LBB203_3 ; RV32IA-NEXT: j .LBB203_4 ; RV32IA-NEXT: .LBB203_1: # %atomicrmw.start -; RV32IA-NEXT: sw a4, 0(sp) -; RV32IA-NEXT: sw a5, 4(sp) +; RV32IA-NEXT: sw a1, 4(sp) +; RV32IA-NEXT: mv a0, s1 +; RV32IA-NEXT: mv a1, s3 ; RV32IA-NEXT: addi a4, zero, 4 ; RV32IA-NEXT: addi a5, zero, 2 -; RV32IA-NEXT: mv a0, s0 -; RV32IA-NEXT: mv a1, s3 ; RV32IA-NEXT: call __atomic_compare_exchange_8 -; RV32IA-NEXT: lw a5, 4(sp) -; RV32IA-NEXT: lw a4, 0(sp) +; RV32IA-NEXT: lw a1, 4(sp) +; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: bnez a0, .LBB203_7 ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start -; RV32IA-NEXT: beq a5, s1, .LBB203_4 +; RV32IA-NEXT: beq a1, s0, .LBB203_4 ; RV32IA-NEXT: .LBB203_3: # %atomicrmw.start -; RV32IA-NEXT: slt a0, s1, a5 +; RV32IA-NEXT: slt a0, s0, a1 ; RV32IA-NEXT: j .LBB203_5 ; RV32IA-NEXT: .LBB203_4: -; RV32IA-NEXT: sltu a0, s2, a4 +; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: .LBB203_5: # %atomicrmw.start -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sw a2, 0(sp) +; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: bnez a0, .LBB203_1 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: mv a2, s2 -; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: j .LBB203_1 ; RV32IA-NEXT: .LBB203_7: # %atomicrmw.end -; RV32IA-NEXT: mv a0, a4 -; RV32IA-NEXT: mv a1, a5 +; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s1, 20(sp) @@ -15389,31 +15350,30 @@ define i64 @atomicrmw_max_i64_acq_rel(i64 *%a, i64 %b) nounwind { ; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: ld a3, 0(a0) -; RV64I-NEXT: mv s1, a1 +; RV64I-NEXT: mv s0, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: addi s2, sp, 8 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s1, a3, .LBB203_3 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: bge s0, a2, .LBB203_3 ; RV64I-NEXT: .LBB203_1: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sd a3, 8(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a4, zero, 2 -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: call __atomic_compare_exchange_8 -; RV64I-NEXT: ld a3, 8(sp) +; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: bnez a0, .LBB203_4 ; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB203_1 Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: blt s1, a3, .LBB203_1 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: blt s0, a2, .LBB203_1 ; RV64I-NEXT: .LBB203_3: # %atomicrmw.start -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: j .LBB203_1 ; RV64I-NEXT: .LBB203_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 +; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s0, 32(sp) @@ -15438,43 +15398,41 @@ define i64 @atomicrmw_max_i64_seq_cst(i64 *%a, i64 %b) nounwind { ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s3, 12(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a5, 4(a0) -; RV32I-NEXT: lw a4, 0(a0) -; RV32I-NEXT: mv s1, a2 +; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s2, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a1, 4(a0) +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s3, sp -; RV32I-NEXT: bne a5, s1, .LBB204_3 +; RV32I-NEXT: bne a1, s0, .LBB204_3 ; RV32I-NEXT: j .LBB204_4 ; RV32I-NEXT: .LBB204_1: # %atomicrmw.start -; RV32I-NEXT: sw a4, 0(sp) -; RV32I-NEXT: sw a5, 4(sp) +; RV32I-NEXT: sw a1, 4(sp) +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a5, zero, 5 -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: call __atomic_compare_exchange_8 -; RV32I-NEXT: lw a5, 4(sp) -; RV32I-NEXT: lw a4, 0(sp) +; RV32I-NEXT: lw a1, 4(sp) +; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: bnez a0, .LBB204_7 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start -; RV32I-NEXT: beq a5, s1, .LBB204_4 +; RV32I-NEXT: beq a1, s0, .LBB204_4 ; RV32I-NEXT: .LBB204_3: # %atomicrmw.start -; RV32I-NEXT: slt a0, s1, a5 +; RV32I-NEXT: slt a0, s0, a1 ; RV32I-NEXT: j .LBB204_5 ; RV32I-NEXT: .LBB204_4: -; RV32I-NEXT: sltu a0, s2, a4 +; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: .LBB204_5: # %atomicrmw.start -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 +; RV32I-NEXT: sw a2, 0(sp) +; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: bnez a0, .LBB204_1 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: mv a2, s2 -; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: j .LBB204_1 ; RV32I-NEXT: .LBB204_7: # %atomicrmw.end -; RV32I-NEXT: mv a0, a4 -; RV32I-NEXT: mv a1, a5 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -15491,43 +15449,41 @@ define i64 @atomicrmw_max_i64_seq_cst(i64 *%a, i64 %b) nounwind { ; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s3, 12(sp) -; RV32IA-NEXT: mv s0, a0 -; RV32IA-NEXT: lw a5, 4(a0) -; RV32IA-NEXT: lw a4, 0(a0) -; RV32IA-NEXT: mv s1, a2 +; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s2, a1 +; RV32IA-NEXT: mv s1, a0 +; RV32IA-NEXT: lw a1, 4(a0) +; RV32IA-NEXT: lw a2, 0(a0) ; RV32IA-NEXT: mv s3, sp -; RV32IA-NEXT: bne a5, s1, .LBB204_3 +; RV32IA-NEXT: bne a1, s0, .LBB204_3 ; RV32IA-NEXT: j .LBB204_4 ; RV32IA-NEXT: .LBB204_1: # %atomicrmw.start -; RV32IA-NEXT: sw a4, 0(sp) -; RV32IA-NEXT: sw a5, 4(sp) +; RV32IA-NEXT: sw a1, 4(sp) +; RV32IA-NEXT: mv a0, s1 +; RV32IA-NEXT: mv a1, s3 ; RV32IA-NEXT: addi a4, zero, 5 ; RV32IA-NEXT: addi a5, zero, 5 -; RV32IA-NEXT: mv a0, s0 -; RV32IA-NEXT: mv a1, s3 ; RV32IA-NEXT: call __atomic_compare_exchange_8 -; RV32IA-NEXT: lw a5, 4(sp) -; RV32IA-NEXT: lw a4, 0(sp) +; RV32IA-NEXT: lw a1, 4(sp) +; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: bnez a0, .LBB204_7 ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start -; RV32IA-NEXT: beq a5, s1, .LBB204_4 +; RV32IA-NEXT: beq a1, s0, .LBB204_4 ; RV32IA-NEXT: .LBB204_3: # %atomicrmw.start -; RV32IA-NEXT: slt a0, s1, a5 +; RV32IA-NEXT: slt a0, s0, a1 ; RV32IA-NEXT: j .LBB204_5 ; RV32IA-NEXT: .LBB204_4: -; RV32IA-NEXT: sltu a0, s2, a4 +; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: .LBB204_5: # %atomicrmw.start -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sw a2, 0(sp) +; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: bnez a0, .LBB204_1 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: mv a2, s2 -; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: j .LBB204_1 ; RV32IA-NEXT: .LBB204_7: # %atomicrmw.end -; RV32IA-NEXT: mv a0, a4 -; RV32IA-NEXT: mv a1, a5 +; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s1, 20(sp) @@ -15543,31 +15499,30 @@ define i64 @atomicrmw_max_i64_seq_cst(i64 *%a, i64 %b) nounwind { ; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: ld a3, 0(a0) -; RV64I-NEXT: mv s1, a1 +; RV64I-NEXT: mv s0, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: addi s2, sp, 8 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s1, a3, .LBB204_3 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: bge s0, a2, .LBB204_3 ; RV64I-NEXT: .LBB204_1: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sd a3, 8(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a4, zero, 5 -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: call __atomic_compare_exchange_8 -; RV64I-NEXT: ld a3, 8(sp) +; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: bnez a0, .LBB204_4 ; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB204_1 Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: blt s1, a3, .LBB204_1 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: blt s0, a2, .LBB204_1 ; RV64I-NEXT: .LBB204_3: # %atomicrmw.start -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: j .LBB204_1 ; RV64I-NEXT: .LBB204_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 +; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s0, 32(sp) @@ -15592,44 +15547,42 @@ define i64 @atomicrmw_min_i64_monotonic(i64 *%a, i64 %b) nounwind { ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s3, 12(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a5, 4(a0) -; RV32I-NEXT: lw a4, 0(a0) -; RV32I-NEXT: mv s1, a2 +; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s2, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a1, 4(a0) +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s3, sp -; RV32I-NEXT: bne a5, s1, .LBB205_3 +; RV32I-NEXT: bne a1, s0, .LBB205_3 ; RV32I-NEXT: j .LBB205_4 ; RV32I-NEXT: .LBB205_1: # %atomicrmw.start -; RV32I-NEXT: sw a4, 0(sp) -; RV32I-NEXT: sw a5, 4(sp) -; RV32I-NEXT: mv a0, s0 +; RV32I-NEXT: sw a1, 4(sp) +; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: call __atomic_compare_exchange_8 -; RV32I-NEXT: lw a5, 4(sp) -; RV32I-NEXT: lw a4, 0(sp) +; RV32I-NEXT: lw a1, 4(sp) +; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: bnez a0, .LBB205_7 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start -; RV32I-NEXT: beq a5, s1, .LBB205_4 +; RV32I-NEXT: beq a1, s0, .LBB205_4 ; RV32I-NEXT: .LBB205_3: # %atomicrmw.start -; RV32I-NEXT: slt a0, s1, a5 +; RV32I-NEXT: slt a0, s0, a1 ; RV32I-NEXT: j .LBB205_5 ; RV32I-NEXT: .LBB205_4: -; RV32I-NEXT: sltu a0, s2, a4 +; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: .LBB205_5: # %atomicrmw.start ; RV32I-NEXT: xori a0, a0, 1 -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 +; RV32I-NEXT: sw a2, 0(sp) +; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: bnez a0, .LBB205_1 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: mv a2, s2 -; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: j .LBB205_1 ; RV32I-NEXT: .LBB205_7: # %atomicrmw.end -; RV32I-NEXT: mv a0, a4 -; RV32I-NEXT: mv a1, a5 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -15646,44 +15599,42 @@ define i64 @atomicrmw_min_i64_monotonic(i64 *%a, i64 %b) nounwind { ; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s3, 12(sp) -; RV32IA-NEXT: mv s0, a0 -; RV32IA-NEXT: lw a5, 4(a0) -; RV32IA-NEXT: lw a4, 0(a0) -; RV32IA-NEXT: mv s1, a2 +; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s2, a1 +; RV32IA-NEXT: mv s1, a0 +; RV32IA-NEXT: lw a1, 4(a0) +; RV32IA-NEXT: lw a2, 0(a0) ; RV32IA-NEXT: mv s3, sp -; RV32IA-NEXT: bne a5, s1, .LBB205_3 +; RV32IA-NEXT: bne a1, s0, .LBB205_3 ; RV32IA-NEXT: j .LBB205_4 ; RV32IA-NEXT: .LBB205_1: # %atomicrmw.start -; RV32IA-NEXT: sw a4, 0(sp) -; RV32IA-NEXT: sw a5, 4(sp) -; RV32IA-NEXT: mv a0, s0 +; RV32IA-NEXT: sw a1, 4(sp) +; RV32IA-NEXT: mv a0, s1 ; RV32IA-NEXT: mv a1, s3 ; RV32IA-NEXT: mv a4, zero ; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: call __atomic_compare_exchange_8 -; RV32IA-NEXT: lw a5, 4(sp) -; RV32IA-NEXT: lw a4, 0(sp) +; RV32IA-NEXT: lw a1, 4(sp) +; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: bnez a0, .LBB205_7 ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start -; RV32IA-NEXT: beq a5, s1, .LBB205_4 +; RV32IA-NEXT: beq a1, s0, .LBB205_4 ; RV32IA-NEXT: .LBB205_3: # %atomicrmw.start -; RV32IA-NEXT: slt a0, s1, a5 +; RV32IA-NEXT: slt a0, s0, a1 ; RV32IA-NEXT: j .LBB205_5 ; RV32IA-NEXT: .LBB205_4: -; RV32IA-NEXT: sltu a0, s2, a4 +; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: .LBB205_5: # %atomicrmw.start ; RV32IA-NEXT: xori a0, a0, 1 -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sw a2, 0(sp) +; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: bnez a0, .LBB205_1 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: mv a2, s2 -; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: j .LBB205_1 ; RV32IA-NEXT: .LBB205_7: # %atomicrmw.end -; RV32IA-NEXT: mv a0, a4 -; RV32IA-NEXT: mv a1, a5 +; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s1, 20(sp) @@ -15699,31 +15650,30 @@ define i64 @atomicrmw_min_i64_monotonic(i64 *%a, i64 %b) nounwind { ; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: ld a3, 0(a0) -; RV64I-NEXT: mv s1, a1 +; RV64I-NEXT: mv s0, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: addi s2, sp, 8 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: blt s1, a3, .LBB205_3 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: blt s0, a2, .LBB205_3 ; RV64I-NEXT: .LBB205_1: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sd a3, 8(sp) -; RV64I-NEXT: mv a0, s0 +; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: call __atomic_compare_exchange_8 -; RV64I-NEXT: ld a3, 8(sp) +; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: bnez a0, .LBB205_4 ; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB205_1 Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s1, a3, .LBB205_1 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: bge s0, a2, .LBB205_1 ; RV64I-NEXT: .LBB205_3: # %atomicrmw.start -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: j .LBB205_1 ; RV64I-NEXT: .LBB205_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 +; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s0, 32(sp) @@ -15748,44 +15698,42 @@ define i64 @atomicrmw_min_i64_acquire(i64 *%a, i64 %b) nounwind { ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s3, 12(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a5, 4(a0) -; RV32I-NEXT: lw a4, 0(a0) -; RV32I-NEXT: mv s1, a2 +; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s2, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a1, 4(a0) +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s3, sp -; RV32I-NEXT: bne a5, s1, .LBB206_3 +; RV32I-NEXT: bne a1, s0, .LBB206_3 ; RV32I-NEXT: j .LBB206_4 ; RV32I-NEXT: .LBB206_1: # %atomicrmw.start -; RV32I-NEXT: sw a4, 0(sp) -; RV32I-NEXT: sw a5, 4(sp) +; RV32I-NEXT: sw a1, 4(sp) +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a5, zero, 2 -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: call __atomic_compare_exchange_8 -; RV32I-NEXT: lw a5, 4(sp) -; RV32I-NEXT: lw a4, 0(sp) +; RV32I-NEXT: lw a1, 4(sp) +; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: bnez a0, .LBB206_7 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start -; RV32I-NEXT: beq a5, s1, .LBB206_4 +; RV32I-NEXT: beq a1, s0, .LBB206_4 ; RV32I-NEXT: .LBB206_3: # %atomicrmw.start -; RV32I-NEXT: slt a0, s1, a5 +; RV32I-NEXT: slt a0, s0, a1 ; RV32I-NEXT: j .LBB206_5 ; RV32I-NEXT: .LBB206_4: -; RV32I-NEXT: sltu a0, s2, a4 +; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: .LBB206_5: # %atomicrmw.start ; RV32I-NEXT: xori a0, a0, 1 -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 +; RV32I-NEXT: sw a2, 0(sp) +; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: bnez a0, .LBB206_1 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: mv a2, s2 -; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: j .LBB206_1 ; RV32I-NEXT: .LBB206_7: # %atomicrmw.end -; RV32I-NEXT: mv a0, a4 -; RV32I-NEXT: mv a1, a5 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -15802,44 +15750,42 @@ define i64 @atomicrmw_min_i64_acquire(i64 *%a, i64 %b) nounwind { ; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s3, 12(sp) -; RV32IA-NEXT: mv s0, a0 -; RV32IA-NEXT: lw a5, 4(a0) -; RV32IA-NEXT: lw a4, 0(a0) -; RV32IA-NEXT: mv s1, a2 +; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s2, a1 +; RV32IA-NEXT: mv s1, a0 +; RV32IA-NEXT: lw a1, 4(a0) +; RV32IA-NEXT: lw a2, 0(a0) ; RV32IA-NEXT: mv s3, sp -; RV32IA-NEXT: bne a5, s1, .LBB206_3 +; RV32IA-NEXT: bne a1, s0, .LBB206_3 ; RV32IA-NEXT: j .LBB206_4 ; RV32IA-NEXT: .LBB206_1: # %atomicrmw.start -; RV32IA-NEXT: sw a4, 0(sp) -; RV32IA-NEXT: sw a5, 4(sp) +; RV32IA-NEXT: sw a1, 4(sp) +; RV32IA-NEXT: mv a0, s1 +; RV32IA-NEXT: mv a1, s3 ; RV32IA-NEXT: addi a4, zero, 2 ; RV32IA-NEXT: addi a5, zero, 2 -; RV32IA-NEXT: mv a0, s0 -; RV32IA-NEXT: mv a1, s3 ; RV32IA-NEXT: call __atomic_compare_exchange_8 -; RV32IA-NEXT: lw a5, 4(sp) -; RV32IA-NEXT: lw a4, 0(sp) +; RV32IA-NEXT: lw a1, 4(sp) +; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: bnez a0, .LBB206_7 ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start -; RV32IA-NEXT: beq a5, s1, .LBB206_4 +; RV32IA-NEXT: beq a1, s0, .LBB206_4 ; RV32IA-NEXT: .LBB206_3: # %atomicrmw.start -; RV32IA-NEXT: slt a0, s1, a5 +; RV32IA-NEXT: slt a0, s0, a1 ; RV32IA-NEXT: j .LBB206_5 ; RV32IA-NEXT: .LBB206_4: -; RV32IA-NEXT: sltu a0, s2, a4 +; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: .LBB206_5: # %atomicrmw.start ; RV32IA-NEXT: xori a0, a0, 1 -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sw a2, 0(sp) +; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: bnez a0, .LBB206_1 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: mv a2, s2 -; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: j .LBB206_1 ; RV32IA-NEXT: .LBB206_7: # %atomicrmw.end -; RV32IA-NEXT: mv a0, a4 -; RV32IA-NEXT: mv a1, a5 +; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s1, 20(sp) @@ -15855,31 +15801,30 @@ define i64 @atomicrmw_min_i64_acquire(i64 *%a, i64 %b) nounwind { ; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: ld a3, 0(a0) -; RV64I-NEXT: mv s1, a1 +; RV64I-NEXT: mv s0, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: addi s2, sp, 8 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: blt s1, a3, .LBB206_3 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: blt s0, a2, .LBB206_3 ; RV64I-NEXT: .LBB206_1: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sd a3, 8(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a4, zero, 2 -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: call __atomic_compare_exchange_8 -; RV64I-NEXT: ld a3, 8(sp) +; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: bnez a0, .LBB206_4 ; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB206_1 Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s1, a3, .LBB206_1 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: bge s0, a2, .LBB206_1 ; RV64I-NEXT: .LBB206_3: # %atomicrmw.start -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: j .LBB206_1 ; RV64I-NEXT: .LBB206_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 +; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s0, 32(sp) @@ -15904,44 +15849,42 @@ define i64 @atomicrmw_min_i64_release(i64 *%a, i64 %b) nounwind { ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s3, 12(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a5, 4(a0) -; RV32I-NEXT: lw a4, 0(a0) -; RV32I-NEXT: mv s1, a2 +; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s2, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a1, 4(a0) +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s3, sp -; RV32I-NEXT: bne a5, s1, .LBB207_3 +; RV32I-NEXT: bne a1, s0, .LBB207_3 ; RV32I-NEXT: j .LBB207_4 ; RV32I-NEXT: .LBB207_1: # %atomicrmw.start -; RV32I-NEXT: sw a4, 0(sp) -; RV32I-NEXT: sw a5, 4(sp) -; RV32I-NEXT: addi a4, zero, 3 -; RV32I-NEXT: mv a0, s0 +; RV32I-NEXT: sw a1, 4(sp) +; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s3 +; RV32I-NEXT: addi a4, zero, 3 ; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: call __atomic_compare_exchange_8 -; RV32I-NEXT: lw a5, 4(sp) -; RV32I-NEXT: lw a4, 0(sp) +; RV32I-NEXT: lw a1, 4(sp) +; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: bnez a0, .LBB207_7 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start -; RV32I-NEXT: beq a5, s1, .LBB207_4 +; RV32I-NEXT: beq a1, s0, .LBB207_4 ; RV32I-NEXT: .LBB207_3: # %atomicrmw.start -; RV32I-NEXT: slt a0, s1, a5 +; RV32I-NEXT: slt a0, s0, a1 ; RV32I-NEXT: j .LBB207_5 ; RV32I-NEXT: .LBB207_4: -; RV32I-NEXT: sltu a0, s2, a4 +; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: .LBB207_5: # %atomicrmw.start ; RV32I-NEXT: xori a0, a0, 1 -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 +; RV32I-NEXT: sw a2, 0(sp) +; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: bnez a0, .LBB207_1 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: mv a2, s2 -; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: j .LBB207_1 ; RV32I-NEXT: .LBB207_7: # %atomicrmw.end -; RV32I-NEXT: mv a0, a4 -; RV32I-NEXT: mv a1, a5 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -15958,44 +15901,42 @@ define i64 @atomicrmw_min_i64_release(i64 *%a, i64 %b) nounwind { ; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s3, 12(sp) -; RV32IA-NEXT: mv s0, a0 -; RV32IA-NEXT: lw a5, 4(a0) -; RV32IA-NEXT: lw a4, 0(a0) -; RV32IA-NEXT: mv s1, a2 +; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s2, a1 +; RV32IA-NEXT: mv s1, a0 +; RV32IA-NEXT: lw a1, 4(a0) +; RV32IA-NEXT: lw a2, 0(a0) ; RV32IA-NEXT: mv s3, sp -; RV32IA-NEXT: bne a5, s1, .LBB207_3 +; RV32IA-NEXT: bne a1, s0, .LBB207_3 ; RV32IA-NEXT: j .LBB207_4 ; RV32IA-NEXT: .LBB207_1: # %atomicrmw.start -; RV32IA-NEXT: sw a4, 0(sp) -; RV32IA-NEXT: sw a5, 4(sp) -; RV32IA-NEXT: addi a4, zero, 3 -; RV32IA-NEXT: mv a0, s0 +; RV32IA-NEXT: sw a1, 4(sp) +; RV32IA-NEXT: mv a0, s1 ; RV32IA-NEXT: mv a1, s3 +; RV32IA-NEXT: addi a4, zero, 3 ; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: call __atomic_compare_exchange_8 -; RV32IA-NEXT: lw a5, 4(sp) -; RV32IA-NEXT: lw a4, 0(sp) +; RV32IA-NEXT: lw a1, 4(sp) +; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: bnez a0, .LBB207_7 ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start -; RV32IA-NEXT: beq a5, s1, .LBB207_4 +; RV32IA-NEXT: beq a1, s0, .LBB207_4 ; RV32IA-NEXT: .LBB207_3: # %atomicrmw.start -; RV32IA-NEXT: slt a0, s1, a5 +; RV32IA-NEXT: slt a0, s0, a1 ; RV32IA-NEXT: j .LBB207_5 ; RV32IA-NEXT: .LBB207_4: -; RV32IA-NEXT: sltu a0, s2, a4 +; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: .LBB207_5: # %atomicrmw.start ; RV32IA-NEXT: xori a0, a0, 1 -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sw a2, 0(sp) +; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: bnez a0, .LBB207_1 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: mv a2, s2 -; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: j .LBB207_1 ; RV32IA-NEXT: .LBB207_7: # %atomicrmw.end -; RV32IA-NEXT: mv a0, a4 -; RV32IA-NEXT: mv a1, a5 +; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s1, 20(sp) @@ -16011,31 +15952,30 @@ define i64 @atomicrmw_min_i64_release(i64 *%a, i64 %b) nounwind { ; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: ld a3, 0(a0) -; RV64I-NEXT: mv s1, a1 +; RV64I-NEXT: mv s0, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: addi s2, sp, 8 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: blt s1, a3, .LBB207_3 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: blt s0, a2, .LBB207_3 ; RV64I-NEXT: .LBB207_1: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sd a3, 8(sp) -; RV64I-NEXT: addi a3, zero, 3 -; RV64I-NEXT: mv a0, s0 +; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s2 +; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: call __atomic_compare_exchange_8 -; RV64I-NEXT: ld a3, 8(sp) +; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: bnez a0, .LBB207_4 ; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB207_1 Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s1, a3, .LBB207_1 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: bge s0, a2, .LBB207_1 ; RV64I-NEXT: .LBB207_3: # %atomicrmw.start -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: j .LBB207_1 ; RV64I-NEXT: .LBB207_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 +; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s0, 32(sp) @@ -16060,44 +16000,42 @@ define i64 @atomicrmw_min_i64_acq_rel(i64 *%a, i64 %b) nounwind { ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s3, 12(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a5, 4(a0) -; RV32I-NEXT: lw a4, 0(a0) -; RV32I-NEXT: mv s1, a2 +; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s2, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a1, 4(a0) +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s3, sp -; RV32I-NEXT: bne a5, s1, .LBB208_3 +; RV32I-NEXT: bne a1, s0, .LBB208_3 ; RV32I-NEXT: j .LBB208_4 ; RV32I-NEXT: .LBB208_1: # %atomicrmw.start -; RV32I-NEXT: sw a4, 0(sp) -; RV32I-NEXT: sw a5, 4(sp) +; RV32I-NEXT: sw a1, 4(sp) +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: addi a4, zero, 4 ; RV32I-NEXT: addi a5, zero, 2 -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: call __atomic_compare_exchange_8 -; RV32I-NEXT: lw a5, 4(sp) -; RV32I-NEXT: lw a4, 0(sp) +; RV32I-NEXT: lw a1, 4(sp) +; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: bnez a0, .LBB208_7 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start -; RV32I-NEXT: beq a5, s1, .LBB208_4 +; RV32I-NEXT: beq a1, s0, .LBB208_4 ; RV32I-NEXT: .LBB208_3: # %atomicrmw.start -; RV32I-NEXT: slt a0, s1, a5 +; RV32I-NEXT: slt a0, s0, a1 ; RV32I-NEXT: j .LBB208_5 ; RV32I-NEXT: .LBB208_4: -; RV32I-NEXT: sltu a0, s2, a4 +; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: .LBB208_5: # %atomicrmw.start ; RV32I-NEXT: xori a0, a0, 1 -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 +; RV32I-NEXT: sw a2, 0(sp) +; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: bnez a0, .LBB208_1 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: mv a2, s2 -; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: j .LBB208_1 ; RV32I-NEXT: .LBB208_7: # %atomicrmw.end -; RV32I-NEXT: mv a0, a4 -; RV32I-NEXT: mv a1, a5 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -16114,44 +16052,42 @@ define i64 @atomicrmw_min_i64_acq_rel(i64 *%a, i64 %b) nounwind { ; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s3, 12(sp) -; RV32IA-NEXT: mv s0, a0 -; RV32IA-NEXT: lw a5, 4(a0) -; RV32IA-NEXT: lw a4, 0(a0) -; RV32IA-NEXT: mv s1, a2 +; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s2, a1 +; RV32IA-NEXT: mv s1, a0 +; RV32IA-NEXT: lw a1, 4(a0) +; RV32IA-NEXT: lw a2, 0(a0) ; RV32IA-NEXT: mv s3, sp -; RV32IA-NEXT: bne a5, s1, .LBB208_3 +; RV32IA-NEXT: bne a1, s0, .LBB208_3 ; RV32IA-NEXT: j .LBB208_4 ; RV32IA-NEXT: .LBB208_1: # %atomicrmw.start -; RV32IA-NEXT: sw a4, 0(sp) -; RV32IA-NEXT: sw a5, 4(sp) +; RV32IA-NEXT: sw a1, 4(sp) +; RV32IA-NEXT: mv a0, s1 +; RV32IA-NEXT: mv a1, s3 ; RV32IA-NEXT: addi a4, zero, 4 ; RV32IA-NEXT: addi a5, zero, 2 -; RV32IA-NEXT: mv a0, s0 -; RV32IA-NEXT: mv a1, s3 ; RV32IA-NEXT: call __atomic_compare_exchange_8 -; RV32IA-NEXT: lw a5, 4(sp) -; RV32IA-NEXT: lw a4, 0(sp) +; RV32IA-NEXT: lw a1, 4(sp) +; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: bnez a0, .LBB208_7 ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start -; RV32IA-NEXT: beq a5, s1, .LBB208_4 +; RV32IA-NEXT: beq a1, s0, .LBB208_4 ; RV32IA-NEXT: .LBB208_3: # %atomicrmw.start -; RV32IA-NEXT: slt a0, s1, a5 +; RV32IA-NEXT: slt a0, s0, a1 ; RV32IA-NEXT: j .LBB208_5 ; RV32IA-NEXT: .LBB208_4: -; RV32IA-NEXT: sltu a0, s2, a4 +; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: .LBB208_5: # %atomicrmw.start ; RV32IA-NEXT: xori a0, a0, 1 -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sw a2, 0(sp) +; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: bnez a0, .LBB208_1 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: mv a2, s2 -; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: j .LBB208_1 ; RV32IA-NEXT: .LBB208_7: # %atomicrmw.end -; RV32IA-NEXT: mv a0, a4 -; RV32IA-NEXT: mv a1, a5 +; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s1, 20(sp) @@ -16167,31 +16103,30 @@ define i64 @atomicrmw_min_i64_acq_rel(i64 *%a, i64 %b) nounwind { ; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: ld a3, 0(a0) -; RV64I-NEXT: mv s1, a1 +; RV64I-NEXT: mv s0, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: addi s2, sp, 8 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: blt s1, a3, .LBB208_3 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: blt s0, a2, .LBB208_3 ; RV64I-NEXT: .LBB208_1: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sd a3, 8(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a4, zero, 2 -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: call __atomic_compare_exchange_8 -; RV64I-NEXT: ld a3, 8(sp) +; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: bnez a0, .LBB208_4 ; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB208_1 Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s1, a3, .LBB208_1 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: bge s0, a2, .LBB208_1 ; RV64I-NEXT: .LBB208_3: # %atomicrmw.start -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: j .LBB208_1 ; RV64I-NEXT: .LBB208_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 +; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s0, 32(sp) @@ -16216,44 +16151,42 @@ define i64 @atomicrmw_min_i64_seq_cst(i64 *%a, i64 %b) nounwind { ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s3, 12(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a5, 4(a0) -; RV32I-NEXT: lw a4, 0(a0) -; RV32I-NEXT: mv s1, a2 +; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s2, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a1, 4(a0) +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s3, sp -; RV32I-NEXT: bne a5, s1, .LBB209_3 +; RV32I-NEXT: bne a1, s0, .LBB209_3 ; RV32I-NEXT: j .LBB209_4 ; RV32I-NEXT: .LBB209_1: # %atomicrmw.start -; RV32I-NEXT: sw a4, 0(sp) -; RV32I-NEXT: sw a5, 4(sp) +; RV32I-NEXT: sw a1, 4(sp) +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a5, zero, 5 -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: call __atomic_compare_exchange_8 -; RV32I-NEXT: lw a5, 4(sp) -; RV32I-NEXT: lw a4, 0(sp) +; RV32I-NEXT: lw a1, 4(sp) +; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: bnez a0, .LBB209_7 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start -; RV32I-NEXT: beq a5, s1, .LBB209_4 +; RV32I-NEXT: beq a1, s0, .LBB209_4 ; RV32I-NEXT: .LBB209_3: # %atomicrmw.start -; RV32I-NEXT: slt a0, s1, a5 +; RV32I-NEXT: slt a0, s0, a1 ; RV32I-NEXT: j .LBB209_5 ; RV32I-NEXT: .LBB209_4: -; RV32I-NEXT: sltu a0, s2, a4 +; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: .LBB209_5: # %atomicrmw.start ; RV32I-NEXT: xori a0, a0, 1 -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 +; RV32I-NEXT: sw a2, 0(sp) +; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: bnez a0, .LBB209_1 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: mv a2, s2 -; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: j .LBB209_1 ; RV32I-NEXT: .LBB209_7: # %atomicrmw.end -; RV32I-NEXT: mv a0, a4 -; RV32I-NEXT: mv a1, a5 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -16270,44 +16203,42 @@ define i64 @atomicrmw_min_i64_seq_cst(i64 *%a, i64 %b) nounwind { ; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s3, 12(sp) -; RV32IA-NEXT: mv s0, a0 -; RV32IA-NEXT: lw a5, 4(a0) -; RV32IA-NEXT: lw a4, 0(a0) -; RV32IA-NEXT: mv s1, a2 +; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s2, a1 +; RV32IA-NEXT: mv s1, a0 +; RV32IA-NEXT: lw a1, 4(a0) +; RV32IA-NEXT: lw a2, 0(a0) ; RV32IA-NEXT: mv s3, sp -; RV32IA-NEXT: bne a5, s1, .LBB209_3 +; RV32IA-NEXT: bne a1, s0, .LBB209_3 ; RV32IA-NEXT: j .LBB209_4 ; RV32IA-NEXT: .LBB209_1: # %atomicrmw.start -; RV32IA-NEXT: sw a4, 0(sp) -; RV32IA-NEXT: sw a5, 4(sp) +; RV32IA-NEXT: sw a1, 4(sp) +; RV32IA-NEXT: mv a0, s1 +; RV32IA-NEXT: mv a1, s3 ; RV32IA-NEXT: addi a4, zero, 5 ; RV32IA-NEXT: addi a5, zero, 5 -; RV32IA-NEXT: mv a0, s0 -; RV32IA-NEXT: mv a1, s3 ; RV32IA-NEXT: call __atomic_compare_exchange_8 -; RV32IA-NEXT: lw a5, 4(sp) -; RV32IA-NEXT: lw a4, 0(sp) +; RV32IA-NEXT: lw a1, 4(sp) +; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: bnez a0, .LBB209_7 ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start -; RV32IA-NEXT: beq a5, s1, .LBB209_4 +; RV32IA-NEXT: beq a1, s0, .LBB209_4 ; RV32IA-NEXT: .LBB209_3: # %atomicrmw.start -; RV32IA-NEXT: slt a0, s1, a5 +; RV32IA-NEXT: slt a0, s0, a1 ; RV32IA-NEXT: j .LBB209_5 ; RV32IA-NEXT: .LBB209_4: -; RV32IA-NEXT: sltu a0, s2, a4 +; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: .LBB209_5: # %atomicrmw.start ; RV32IA-NEXT: xori a0, a0, 1 -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sw a2, 0(sp) +; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: bnez a0, .LBB209_1 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: mv a2, s2 -; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: j .LBB209_1 ; RV32IA-NEXT: .LBB209_7: # %atomicrmw.end -; RV32IA-NEXT: mv a0, a4 -; RV32IA-NEXT: mv a1, a5 +; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s1, 20(sp) @@ -16323,31 +16254,30 @@ define i64 @atomicrmw_min_i64_seq_cst(i64 *%a, i64 %b) nounwind { ; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: ld a3, 0(a0) -; RV64I-NEXT: mv s1, a1 +; RV64I-NEXT: mv s0, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: addi s2, sp, 8 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: blt s1, a3, .LBB209_3 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: blt s0, a2, .LBB209_3 ; RV64I-NEXT: .LBB209_1: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sd a3, 8(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a4, zero, 5 -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: call __atomic_compare_exchange_8 -; RV64I-NEXT: ld a3, 8(sp) +; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: bnez a0, .LBB209_4 ; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB209_1 Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bge s1, a3, .LBB209_1 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: bge s0, a2, .LBB209_1 ; RV64I-NEXT: .LBB209_3: # %atomicrmw.start -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: j .LBB209_1 ; RV64I-NEXT: .LBB209_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 +; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s0, 32(sp) @@ -16372,43 +16302,41 @@ define i64 @atomicrmw_umax_i64_monotonic(i64 *%a, i64 %b) nounwind { ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s3, 12(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a5, 4(a0) -; RV32I-NEXT: lw a4, 0(a0) -; RV32I-NEXT: mv s1, a2 +; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s2, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a1, 4(a0) +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s3, sp -; RV32I-NEXT: bne a5, s1, .LBB210_3 +; RV32I-NEXT: bne a1, s0, .LBB210_3 ; RV32I-NEXT: j .LBB210_4 ; RV32I-NEXT: .LBB210_1: # %atomicrmw.start -; RV32I-NEXT: sw a4, 0(sp) -; RV32I-NEXT: sw a5, 4(sp) -; RV32I-NEXT: mv a0, s0 +; RV32I-NEXT: sw a1, 4(sp) +; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: call __atomic_compare_exchange_8 -; RV32I-NEXT: lw a5, 4(sp) -; RV32I-NEXT: lw a4, 0(sp) +; RV32I-NEXT: lw a1, 4(sp) +; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: bnez a0, .LBB210_7 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start -; RV32I-NEXT: beq a5, s1, .LBB210_4 +; RV32I-NEXT: beq a1, s0, .LBB210_4 ; RV32I-NEXT: .LBB210_3: # %atomicrmw.start -; RV32I-NEXT: sltu a0, s1, a5 +; RV32I-NEXT: sltu a0, s0, a1 ; RV32I-NEXT: j .LBB210_5 ; RV32I-NEXT: .LBB210_4: -; RV32I-NEXT: sltu a0, s2, a4 +; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: .LBB210_5: # %atomicrmw.start -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 +; RV32I-NEXT: sw a2, 0(sp) +; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: bnez a0, .LBB210_1 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: mv a2, s2 -; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: j .LBB210_1 ; RV32I-NEXT: .LBB210_7: # %atomicrmw.end -; RV32I-NEXT: mv a0, a4 -; RV32I-NEXT: mv a1, a5 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -16425,43 +16353,41 @@ define i64 @atomicrmw_umax_i64_monotonic(i64 *%a, i64 %b) nounwind { ; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s3, 12(sp) -; RV32IA-NEXT: mv s0, a0 -; RV32IA-NEXT: lw a5, 4(a0) -; RV32IA-NEXT: lw a4, 0(a0) -; RV32IA-NEXT: mv s1, a2 +; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s2, a1 +; RV32IA-NEXT: mv s1, a0 +; RV32IA-NEXT: lw a1, 4(a0) +; RV32IA-NEXT: lw a2, 0(a0) ; RV32IA-NEXT: mv s3, sp -; RV32IA-NEXT: bne a5, s1, .LBB210_3 +; RV32IA-NEXT: bne a1, s0, .LBB210_3 ; RV32IA-NEXT: j .LBB210_4 ; RV32IA-NEXT: .LBB210_1: # %atomicrmw.start -; RV32IA-NEXT: sw a4, 0(sp) -; RV32IA-NEXT: sw a5, 4(sp) -; RV32IA-NEXT: mv a0, s0 +; RV32IA-NEXT: sw a1, 4(sp) +; RV32IA-NEXT: mv a0, s1 ; RV32IA-NEXT: mv a1, s3 ; RV32IA-NEXT: mv a4, zero ; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: call __atomic_compare_exchange_8 -; RV32IA-NEXT: lw a5, 4(sp) -; RV32IA-NEXT: lw a4, 0(sp) +; RV32IA-NEXT: lw a1, 4(sp) +; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: bnez a0, .LBB210_7 ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start -; RV32IA-NEXT: beq a5, s1, .LBB210_4 +; RV32IA-NEXT: beq a1, s0, .LBB210_4 ; RV32IA-NEXT: .LBB210_3: # %atomicrmw.start -; RV32IA-NEXT: sltu a0, s1, a5 +; RV32IA-NEXT: sltu a0, s0, a1 ; RV32IA-NEXT: j .LBB210_5 ; RV32IA-NEXT: .LBB210_4: -; RV32IA-NEXT: sltu a0, s2, a4 +; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: .LBB210_5: # %atomicrmw.start -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sw a2, 0(sp) +; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: bnez a0, .LBB210_1 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: mv a2, s2 -; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: j .LBB210_1 ; RV32IA-NEXT: .LBB210_7: # %atomicrmw.end -; RV32IA-NEXT: mv a0, a4 -; RV32IA-NEXT: mv a1, a5 +; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s1, 20(sp) @@ -16477,31 +16403,30 @@ define i64 @atomicrmw_umax_i64_monotonic(i64 *%a, i64 %b) nounwind { ; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: ld a3, 0(a0) -; RV64I-NEXT: mv s1, a1 +; RV64I-NEXT: mv s0, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: addi s2, sp, 8 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s1, a3, .LBB210_3 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: bgeu s0, a2, .LBB210_3 ; RV64I-NEXT: .LBB210_1: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sd a3, 8(sp) -; RV64I-NEXT: mv a0, s0 +; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: call __atomic_compare_exchange_8 -; RV64I-NEXT: ld a3, 8(sp) +; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: bnez a0, .LBB210_4 ; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB210_1 Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bltu s1, a3, .LBB210_1 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: bltu s0, a2, .LBB210_1 ; RV64I-NEXT: .LBB210_3: # %atomicrmw.start -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: j .LBB210_1 ; RV64I-NEXT: .LBB210_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 +; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s0, 32(sp) @@ -16526,43 +16451,41 @@ define i64 @atomicrmw_umax_i64_acquire(i64 *%a, i64 %b) nounwind { ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s3, 12(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a5, 4(a0) -; RV32I-NEXT: lw a4, 0(a0) -; RV32I-NEXT: mv s1, a2 +; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s2, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a1, 4(a0) +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s3, sp -; RV32I-NEXT: bne a5, s1, .LBB211_3 +; RV32I-NEXT: bne a1, s0, .LBB211_3 ; RV32I-NEXT: j .LBB211_4 ; RV32I-NEXT: .LBB211_1: # %atomicrmw.start -; RV32I-NEXT: sw a4, 0(sp) -; RV32I-NEXT: sw a5, 4(sp) +; RV32I-NEXT: sw a1, 4(sp) +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a5, zero, 2 -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: call __atomic_compare_exchange_8 -; RV32I-NEXT: lw a5, 4(sp) -; RV32I-NEXT: lw a4, 0(sp) +; RV32I-NEXT: lw a1, 4(sp) +; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: bnez a0, .LBB211_7 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start -; RV32I-NEXT: beq a5, s1, .LBB211_4 +; RV32I-NEXT: beq a1, s0, .LBB211_4 ; RV32I-NEXT: .LBB211_3: # %atomicrmw.start -; RV32I-NEXT: sltu a0, s1, a5 +; RV32I-NEXT: sltu a0, s0, a1 ; RV32I-NEXT: j .LBB211_5 ; RV32I-NEXT: .LBB211_4: -; RV32I-NEXT: sltu a0, s2, a4 +; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: .LBB211_5: # %atomicrmw.start -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 +; RV32I-NEXT: sw a2, 0(sp) +; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: bnez a0, .LBB211_1 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: mv a2, s2 -; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: j .LBB211_1 ; RV32I-NEXT: .LBB211_7: # %atomicrmw.end -; RV32I-NEXT: mv a0, a4 -; RV32I-NEXT: mv a1, a5 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -16579,43 +16502,41 @@ define i64 @atomicrmw_umax_i64_acquire(i64 *%a, i64 %b) nounwind { ; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s3, 12(sp) -; RV32IA-NEXT: mv s0, a0 -; RV32IA-NEXT: lw a5, 4(a0) -; RV32IA-NEXT: lw a4, 0(a0) -; RV32IA-NEXT: mv s1, a2 +; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s2, a1 +; RV32IA-NEXT: mv s1, a0 +; RV32IA-NEXT: lw a1, 4(a0) +; RV32IA-NEXT: lw a2, 0(a0) ; RV32IA-NEXT: mv s3, sp -; RV32IA-NEXT: bne a5, s1, .LBB211_3 +; RV32IA-NEXT: bne a1, s0, .LBB211_3 ; RV32IA-NEXT: j .LBB211_4 ; RV32IA-NEXT: .LBB211_1: # %atomicrmw.start -; RV32IA-NEXT: sw a4, 0(sp) -; RV32IA-NEXT: sw a5, 4(sp) +; RV32IA-NEXT: sw a1, 4(sp) +; RV32IA-NEXT: mv a0, s1 +; RV32IA-NEXT: mv a1, s3 ; RV32IA-NEXT: addi a4, zero, 2 ; RV32IA-NEXT: addi a5, zero, 2 -; RV32IA-NEXT: mv a0, s0 -; RV32IA-NEXT: mv a1, s3 ; RV32IA-NEXT: call __atomic_compare_exchange_8 -; RV32IA-NEXT: lw a5, 4(sp) -; RV32IA-NEXT: lw a4, 0(sp) +; RV32IA-NEXT: lw a1, 4(sp) +; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: bnez a0, .LBB211_7 ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start -; RV32IA-NEXT: beq a5, s1, .LBB211_4 +; RV32IA-NEXT: beq a1, s0, .LBB211_4 ; RV32IA-NEXT: .LBB211_3: # %atomicrmw.start -; RV32IA-NEXT: sltu a0, s1, a5 +; RV32IA-NEXT: sltu a0, s0, a1 ; RV32IA-NEXT: j .LBB211_5 ; RV32IA-NEXT: .LBB211_4: -; RV32IA-NEXT: sltu a0, s2, a4 +; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: .LBB211_5: # %atomicrmw.start -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sw a2, 0(sp) +; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: bnez a0, .LBB211_1 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: mv a2, s2 -; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: j .LBB211_1 ; RV32IA-NEXT: .LBB211_7: # %atomicrmw.end -; RV32IA-NEXT: mv a0, a4 -; RV32IA-NEXT: mv a1, a5 +; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s1, 20(sp) @@ -16631,31 +16552,30 @@ define i64 @atomicrmw_umax_i64_acquire(i64 *%a, i64 %b) nounwind { ; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: ld a3, 0(a0) -; RV64I-NEXT: mv s1, a1 +; RV64I-NEXT: mv s0, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: addi s2, sp, 8 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s1, a3, .LBB211_3 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: bgeu s0, a2, .LBB211_3 ; RV64I-NEXT: .LBB211_1: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sd a3, 8(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a4, zero, 2 -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: call __atomic_compare_exchange_8 -; RV64I-NEXT: ld a3, 8(sp) +; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: bnez a0, .LBB211_4 ; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB211_1 Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bltu s1, a3, .LBB211_1 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: bltu s0, a2, .LBB211_1 ; RV64I-NEXT: .LBB211_3: # %atomicrmw.start -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: j .LBB211_1 ; RV64I-NEXT: .LBB211_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 +; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s0, 32(sp) @@ -16680,43 +16600,41 @@ define i64 @atomicrmw_umax_i64_release(i64 *%a, i64 %b) nounwind { ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s3, 12(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a5, 4(a0) -; RV32I-NEXT: lw a4, 0(a0) -; RV32I-NEXT: mv s1, a2 +; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s2, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a1, 4(a0) +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s3, sp -; RV32I-NEXT: bne a5, s1, .LBB212_3 +; RV32I-NEXT: bne a1, s0, .LBB212_3 ; RV32I-NEXT: j .LBB212_4 ; RV32I-NEXT: .LBB212_1: # %atomicrmw.start -; RV32I-NEXT: sw a4, 0(sp) -; RV32I-NEXT: sw a5, 4(sp) -; RV32I-NEXT: addi a4, zero, 3 -; RV32I-NEXT: mv a0, s0 +; RV32I-NEXT: sw a1, 4(sp) +; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s3 +; RV32I-NEXT: addi a4, zero, 3 ; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: call __atomic_compare_exchange_8 -; RV32I-NEXT: lw a5, 4(sp) -; RV32I-NEXT: lw a4, 0(sp) +; RV32I-NEXT: lw a1, 4(sp) +; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: bnez a0, .LBB212_7 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start -; RV32I-NEXT: beq a5, s1, .LBB212_4 +; RV32I-NEXT: beq a1, s0, .LBB212_4 ; RV32I-NEXT: .LBB212_3: # %atomicrmw.start -; RV32I-NEXT: sltu a0, s1, a5 +; RV32I-NEXT: sltu a0, s0, a1 ; RV32I-NEXT: j .LBB212_5 ; RV32I-NEXT: .LBB212_4: -; RV32I-NEXT: sltu a0, s2, a4 +; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: .LBB212_5: # %atomicrmw.start -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 +; RV32I-NEXT: sw a2, 0(sp) +; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: bnez a0, .LBB212_1 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: mv a2, s2 -; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: j .LBB212_1 ; RV32I-NEXT: .LBB212_7: # %atomicrmw.end -; RV32I-NEXT: mv a0, a4 -; RV32I-NEXT: mv a1, a5 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -16733,43 +16651,41 @@ define i64 @atomicrmw_umax_i64_release(i64 *%a, i64 %b) nounwind { ; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s3, 12(sp) -; RV32IA-NEXT: mv s0, a0 -; RV32IA-NEXT: lw a5, 4(a0) -; RV32IA-NEXT: lw a4, 0(a0) -; RV32IA-NEXT: mv s1, a2 +; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s2, a1 +; RV32IA-NEXT: mv s1, a0 +; RV32IA-NEXT: lw a1, 4(a0) +; RV32IA-NEXT: lw a2, 0(a0) ; RV32IA-NEXT: mv s3, sp -; RV32IA-NEXT: bne a5, s1, .LBB212_3 +; RV32IA-NEXT: bne a1, s0, .LBB212_3 ; RV32IA-NEXT: j .LBB212_4 ; RV32IA-NEXT: .LBB212_1: # %atomicrmw.start -; RV32IA-NEXT: sw a4, 0(sp) -; RV32IA-NEXT: sw a5, 4(sp) -; RV32IA-NEXT: addi a4, zero, 3 -; RV32IA-NEXT: mv a0, s0 +; RV32IA-NEXT: sw a1, 4(sp) +; RV32IA-NEXT: mv a0, s1 ; RV32IA-NEXT: mv a1, s3 +; RV32IA-NEXT: addi a4, zero, 3 ; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: call __atomic_compare_exchange_8 -; RV32IA-NEXT: lw a5, 4(sp) -; RV32IA-NEXT: lw a4, 0(sp) +; RV32IA-NEXT: lw a1, 4(sp) +; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: bnez a0, .LBB212_7 ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start -; RV32IA-NEXT: beq a5, s1, .LBB212_4 +; RV32IA-NEXT: beq a1, s0, .LBB212_4 ; RV32IA-NEXT: .LBB212_3: # %atomicrmw.start -; RV32IA-NEXT: sltu a0, s1, a5 +; RV32IA-NEXT: sltu a0, s0, a1 ; RV32IA-NEXT: j .LBB212_5 ; RV32IA-NEXT: .LBB212_4: -; RV32IA-NEXT: sltu a0, s2, a4 +; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: .LBB212_5: # %atomicrmw.start -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sw a2, 0(sp) +; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: bnez a0, .LBB212_1 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: mv a2, s2 -; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: j .LBB212_1 ; RV32IA-NEXT: .LBB212_7: # %atomicrmw.end -; RV32IA-NEXT: mv a0, a4 -; RV32IA-NEXT: mv a1, a5 +; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s1, 20(sp) @@ -16785,31 +16701,30 @@ define i64 @atomicrmw_umax_i64_release(i64 *%a, i64 %b) nounwind { ; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: ld a3, 0(a0) -; RV64I-NEXT: mv s1, a1 +; RV64I-NEXT: mv s0, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: addi s2, sp, 8 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s1, a3, .LBB212_3 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: bgeu s0, a2, .LBB212_3 ; RV64I-NEXT: .LBB212_1: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sd a3, 8(sp) -; RV64I-NEXT: addi a3, zero, 3 -; RV64I-NEXT: mv a0, s0 +; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s2 +; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: call __atomic_compare_exchange_8 -; RV64I-NEXT: ld a3, 8(sp) +; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: bnez a0, .LBB212_4 ; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB212_1 Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bltu s1, a3, .LBB212_1 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: bltu s0, a2, .LBB212_1 ; RV64I-NEXT: .LBB212_3: # %atomicrmw.start -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: j .LBB212_1 ; RV64I-NEXT: .LBB212_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 +; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s0, 32(sp) @@ -16834,43 +16749,41 @@ define i64 @atomicrmw_umax_i64_acq_rel(i64 *%a, i64 %b) nounwind { ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s3, 12(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a5, 4(a0) -; RV32I-NEXT: lw a4, 0(a0) -; RV32I-NEXT: mv s1, a2 +; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s2, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a1, 4(a0) +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s3, sp -; RV32I-NEXT: bne a5, s1, .LBB213_3 +; RV32I-NEXT: bne a1, s0, .LBB213_3 ; RV32I-NEXT: j .LBB213_4 ; RV32I-NEXT: .LBB213_1: # %atomicrmw.start -; RV32I-NEXT: sw a4, 0(sp) -; RV32I-NEXT: sw a5, 4(sp) +; RV32I-NEXT: sw a1, 4(sp) +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: addi a4, zero, 4 ; RV32I-NEXT: addi a5, zero, 2 -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: call __atomic_compare_exchange_8 -; RV32I-NEXT: lw a5, 4(sp) -; RV32I-NEXT: lw a4, 0(sp) +; RV32I-NEXT: lw a1, 4(sp) +; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: bnez a0, .LBB213_7 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start -; RV32I-NEXT: beq a5, s1, .LBB213_4 +; RV32I-NEXT: beq a1, s0, .LBB213_4 ; RV32I-NEXT: .LBB213_3: # %atomicrmw.start -; RV32I-NEXT: sltu a0, s1, a5 +; RV32I-NEXT: sltu a0, s0, a1 ; RV32I-NEXT: j .LBB213_5 ; RV32I-NEXT: .LBB213_4: -; RV32I-NEXT: sltu a0, s2, a4 +; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: .LBB213_5: # %atomicrmw.start -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 +; RV32I-NEXT: sw a2, 0(sp) +; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: bnez a0, .LBB213_1 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: mv a2, s2 -; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: j .LBB213_1 ; RV32I-NEXT: .LBB213_7: # %atomicrmw.end -; RV32I-NEXT: mv a0, a4 -; RV32I-NEXT: mv a1, a5 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -16887,43 +16800,41 @@ define i64 @atomicrmw_umax_i64_acq_rel(i64 *%a, i64 %b) nounwind { ; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s3, 12(sp) -; RV32IA-NEXT: mv s0, a0 -; RV32IA-NEXT: lw a5, 4(a0) -; RV32IA-NEXT: lw a4, 0(a0) -; RV32IA-NEXT: mv s1, a2 +; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s2, a1 +; RV32IA-NEXT: mv s1, a0 +; RV32IA-NEXT: lw a1, 4(a0) +; RV32IA-NEXT: lw a2, 0(a0) ; RV32IA-NEXT: mv s3, sp -; RV32IA-NEXT: bne a5, s1, .LBB213_3 +; RV32IA-NEXT: bne a1, s0, .LBB213_3 ; RV32IA-NEXT: j .LBB213_4 ; RV32IA-NEXT: .LBB213_1: # %atomicrmw.start -; RV32IA-NEXT: sw a4, 0(sp) -; RV32IA-NEXT: sw a5, 4(sp) +; RV32IA-NEXT: sw a1, 4(sp) +; RV32IA-NEXT: mv a0, s1 +; RV32IA-NEXT: mv a1, s3 ; RV32IA-NEXT: addi a4, zero, 4 ; RV32IA-NEXT: addi a5, zero, 2 -; RV32IA-NEXT: mv a0, s0 -; RV32IA-NEXT: mv a1, s3 ; RV32IA-NEXT: call __atomic_compare_exchange_8 -; RV32IA-NEXT: lw a5, 4(sp) -; RV32IA-NEXT: lw a4, 0(sp) +; RV32IA-NEXT: lw a1, 4(sp) +; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: bnez a0, .LBB213_7 ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start -; RV32IA-NEXT: beq a5, s1, .LBB213_4 +; RV32IA-NEXT: beq a1, s0, .LBB213_4 ; RV32IA-NEXT: .LBB213_3: # %atomicrmw.start -; RV32IA-NEXT: sltu a0, s1, a5 +; RV32IA-NEXT: sltu a0, s0, a1 ; RV32IA-NEXT: j .LBB213_5 ; RV32IA-NEXT: .LBB213_4: -; RV32IA-NEXT: sltu a0, s2, a4 +; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: .LBB213_5: # %atomicrmw.start -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sw a2, 0(sp) +; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: bnez a0, .LBB213_1 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: mv a2, s2 -; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: j .LBB213_1 ; RV32IA-NEXT: .LBB213_7: # %atomicrmw.end -; RV32IA-NEXT: mv a0, a4 -; RV32IA-NEXT: mv a1, a5 +; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s1, 20(sp) @@ -16939,31 +16850,30 @@ define i64 @atomicrmw_umax_i64_acq_rel(i64 *%a, i64 %b) nounwind { ; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: ld a3, 0(a0) -; RV64I-NEXT: mv s1, a1 +; RV64I-NEXT: mv s0, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: addi s2, sp, 8 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s1, a3, .LBB213_3 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: bgeu s0, a2, .LBB213_3 ; RV64I-NEXT: .LBB213_1: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sd a3, 8(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a4, zero, 2 -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: call __atomic_compare_exchange_8 -; RV64I-NEXT: ld a3, 8(sp) +; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: bnez a0, .LBB213_4 ; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB213_1 Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bltu s1, a3, .LBB213_1 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: bltu s0, a2, .LBB213_1 ; RV64I-NEXT: .LBB213_3: # %atomicrmw.start -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: j .LBB213_1 ; RV64I-NEXT: .LBB213_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 +; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s0, 32(sp) @@ -16988,43 +16898,41 @@ define i64 @atomicrmw_umax_i64_seq_cst(i64 *%a, i64 %b) nounwind { ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s3, 12(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a5, 4(a0) -; RV32I-NEXT: lw a4, 0(a0) -; RV32I-NEXT: mv s1, a2 +; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s2, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a1, 4(a0) +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s3, sp -; RV32I-NEXT: bne a5, s1, .LBB214_3 +; RV32I-NEXT: bne a1, s0, .LBB214_3 ; RV32I-NEXT: j .LBB214_4 ; RV32I-NEXT: .LBB214_1: # %atomicrmw.start -; RV32I-NEXT: sw a4, 0(sp) -; RV32I-NEXT: sw a5, 4(sp) +; RV32I-NEXT: sw a1, 4(sp) +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a5, zero, 5 -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: call __atomic_compare_exchange_8 -; RV32I-NEXT: lw a5, 4(sp) -; RV32I-NEXT: lw a4, 0(sp) +; RV32I-NEXT: lw a1, 4(sp) +; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: bnez a0, .LBB214_7 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start -; RV32I-NEXT: beq a5, s1, .LBB214_4 +; RV32I-NEXT: beq a1, s0, .LBB214_4 ; RV32I-NEXT: .LBB214_3: # %atomicrmw.start -; RV32I-NEXT: sltu a0, s1, a5 +; RV32I-NEXT: sltu a0, s0, a1 ; RV32I-NEXT: j .LBB214_5 ; RV32I-NEXT: .LBB214_4: -; RV32I-NEXT: sltu a0, s2, a4 +; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: .LBB214_5: # %atomicrmw.start -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 +; RV32I-NEXT: sw a2, 0(sp) +; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: bnez a0, .LBB214_1 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: mv a2, s2 -; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: j .LBB214_1 ; RV32I-NEXT: .LBB214_7: # %atomicrmw.end -; RV32I-NEXT: mv a0, a4 -; RV32I-NEXT: mv a1, a5 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -17041,43 +16949,41 @@ define i64 @atomicrmw_umax_i64_seq_cst(i64 *%a, i64 %b) nounwind { ; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s3, 12(sp) -; RV32IA-NEXT: mv s0, a0 -; RV32IA-NEXT: lw a5, 4(a0) -; RV32IA-NEXT: lw a4, 0(a0) -; RV32IA-NEXT: mv s1, a2 +; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s2, a1 +; RV32IA-NEXT: mv s1, a0 +; RV32IA-NEXT: lw a1, 4(a0) +; RV32IA-NEXT: lw a2, 0(a0) ; RV32IA-NEXT: mv s3, sp -; RV32IA-NEXT: bne a5, s1, .LBB214_3 +; RV32IA-NEXT: bne a1, s0, .LBB214_3 ; RV32IA-NEXT: j .LBB214_4 ; RV32IA-NEXT: .LBB214_1: # %atomicrmw.start -; RV32IA-NEXT: sw a4, 0(sp) -; RV32IA-NEXT: sw a5, 4(sp) +; RV32IA-NEXT: sw a1, 4(sp) +; RV32IA-NEXT: mv a0, s1 +; RV32IA-NEXT: mv a1, s3 ; RV32IA-NEXT: addi a4, zero, 5 ; RV32IA-NEXT: addi a5, zero, 5 -; RV32IA-NEXT: mv a0, s0 -; RV32IA-NEXT: mv a1, s3 ; RV32IA-NEXT: call __atomic_compare_exchange_8 -; RV32IA-NEXT: lw a5, 4(sp) -; RV32IA-NEXT: lw a4, 0(sp) +; RV32IA-NEXT: lw a1, 4(sp) +; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: bnez a0, .LBB214_7 ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start -; RV32IA-NEXT: beq a5, s1, .LBB214_4 +; RV32IA-NEXT: beq a1, s0, .LBB214_4 ; RV32IA-NEXT: .LBB214_3: # %atomicrmw.start -; RV32IA-NEXT: sltu a0, s1, a5 +; RV32IA-NEXT: sltu a0, s0, a1 ; RV32IA-NEXT: j .LBB214_5 ; RV32IA-NEXT: .LBB214_4: -; RV32IA-NEXT: sltu a0, s2, a4 +; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: .LBB214_5: # %atomicrmw.start -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sw a2, 0(sp) +; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: bnez a0, .LBB214_1 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: mv a2, s2 -; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: j .LBB214_1 ; RV32IA-NEXT: .LBB214_7: # %atomicrmw.end -; RV32IA-NEXT: mv a0, a4 -; RV32IA-NEXT: mv a1, a5 +; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s1, 20(sp) @@ -17093,31 +16999,30 @@ define i64 @atomicrmw_umax_i64_seq_cst(i64 *%a, i64 %b) nounwind { ; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: ld a3, 0(a0) -; RV64I-NEXT: mv s1, a1 +; RV64I-NEXT: mv s0, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: addi s2, sp, 8 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s1, a3, .LBB214_3 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: bgeu s0, a2, .LBB214_3 ; RV64I-NEXT: .LBB214_1: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sd a3, 8(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a4, zero, 5 -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: call __atomic_compare_exchange_8 -; RV64I-NEXT: ld a3, 8(sp) +; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: bnez a0, .LBB214_4 ; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB214_1 Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bltu s1, a3, .LBB214_1 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: bltu s0, a2, .LBB214_1 ; RV64I-NEXT: .LBB214_3: # %atomicrmw.start -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: j .LBB214_1 ; RV64I-NEXT: .LBB214_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 +; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s0, 32(sp) @@ -17142,44 +17047,42 @@ define i64 @atomicrmw_umin_i64_monotonic(i64 *%a, i64 %b) nounwind { ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s3, 12(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a5, 4(a0) -; RV32I-NEXT: lw a4, 0(a0) -; RV32I-NEXT: mv s1, a2 +; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s2, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a1, 4(a0) +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s3, sp -; RV32I-NEXT: bne a5, s1, .LBB215_3 +; RV32I-NEXT: bne a1, s0, .LBB215_3 ; RV32I-NEXT: j .LBB215_4 ; RV32I-NEXT: .LBB215_1: # %atomicrmw.start -; RV32I-NEXT: sw a4, 0(sp) -; RV32I-NEXT: sw a5, 4(sp) -; RV32I-NEXT: mv a0, s0 +; RV32I-NEXT: sw a1, 4(sp) +; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: call __atomic_compare_exchange_8 -; RV32I-NEXT: lw a5, 4(sp) -; RV32I-NEXT: lw a4, 0(sp) +; RV32I-NEXT: lw a1, 4(sp) +; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: bnez a0, .LBB215_7 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start -; RV32I-NEXT: beq a5, s1, .LBB215_4 +; RV32I-NEXT: beq a1, s0, .LBB215_4 ; RV32I-NEXT: .LBB215_3: # %atomicrmw.start -; RV32I-NEXT: sltu a0, s1, a5 +; RV32I-NEXT: sltu a0, s0, a1 ; RV32I-NEXT: j .LBB215_5 ; RV32I-NEXT: .LBB215_4: -; RV32I-NEXT: sltu a0, s2, a4 +; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: .LBB215_5: # %atomicrmw.start ; RV32I-NEXT: xori a0, a0, 1 -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 +; RV32I-NEXT: sw a2, 0(sp) +; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: bnez a0, .LBB215_1 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: mv a2, s2 -; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: j .LBB215_1 ; RV32I-NEXT: .LBB215_7: # %atomicrmw.end -; RV32I-NEXT: mv a0, a4 -; RV32I-NEXT: mv a1, a5 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -17196,44 +17099,42 @@ define i64 @atomicrmw_umin_i64_monotonic(i64 *%a, i64 %b) nounwind { ; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s3, 12(sp) -; RV32IA-NEXT: mv s0, a0 -; RV32IA-NEXT: lw a5, 4(a0) -; RV32IA-NEXT: lw a4, 0(a0) -; RV32IA-NEXT: mv s1, a2 +; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s2, a1 +; RV32IA-NEXT: mv s1, a0 +; RV32IA-NEXT: lw a1, 4(a0) +; RV32IA-NEXT: lw a2, 0(a0) ; RV32IA-NEXT: mv s3, sp -; RV32IA-NEXT: bne a5, s1, .LBB215_3 +; RV32IA-NEXT: bne a1, s0, .LBB215_3 ; RV32IA-NEXT: j .LBB215_4 ; RV32IA-NEXT: .LBB215_1: # %atomicrmw.start -; RV32IA-NEXT: sw a4, 0(sp) -; RV32IA-NEXT: sw a5, 4(sp) -; RV32IA-NEXT: mv a0, s0 +; RV32IA-NEXT: sw a1, 4(sp) +; RV32IA-NEXT: mv a0, s1 ; RV32IA-NEXT: mv a1, s3 ; RV32IA-NEXT: mv a4, zero ; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: call __atomic_compare_exchange_8 -; RV32IA-NEXT: lw a5, 4(sp) -; RV32IA-NEXT: lw a4, 0(sp) +; RV32IA-NEXT: lw a1, 4(sp) +; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: bnez a0, .LBB215_7 ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start -; RV32IA-NEXT: beq a5, s1, .LBB215_4 +; RV32IA-NEXT: beq a1, s0, .LBB215_4 ; RV32IA-NEXT: .LBB215_3: # %atomicrmw.start -; RV32IA-NEXT: sltu a0, s1, a5 +; RV32IA-NEXT: sltu a0, s0, a1 ; RV32IA-NEXT: j .LBB215_5 ; RV32IA-NEXT: .LBB215_4: -; RV32IA-NEXT: sltu a0, s2, a4 +; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: .LBB215_5: # %atomicrmw.start ; RV32IA-NEXT: xori a0, a0, 1 -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sw a2, 0(sp) +; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: bnez a0, .LBB215_1 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: mv a2, s2 -; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: j .LBB215_1 ; RV32IA-NEXT: .LBB215_7: # %atomicrmw.end -; RV32IA-NEXT: mv a0, a4 -; RV32IA-NEXT: mv a1, a5 +; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s1, 20(sp) @@ -17249,31 +17150,30 @@ define i64 @atomicrmw_umin_i64_monotonic(i64 *%a, i64 %b) nounwind { ; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: ld a3, 0(a0) -; RV64I-NEXT: mv s1, a1 +; RV64I-NEXT: mv s0, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: addi s2, sp, 8 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bltu s1, a3, .LBB215_3 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: bltu s0, a2, .LBB215_3 ; RV64I-NEXT: .LBB215_1: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sd a3, 8(sp) -; RV64I-NEXT: mv a0, s0 +; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: mv a3, zero ; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: call __atomic_compare_exchange_8 -; RV64I-NEXT: ld a3, 8(sp) +; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: bnez a0, .LBB215_4 ; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB215_1 Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s1, a3, .LBB215_1 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: bgeu s0, a2, .LBB215_1 ; RV64I-NEXT: .LBB215_3: # %atomicrmw.start -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: j .LBB215_1 ; RV64I-NEXT: .LBB215_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 +; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s0, 32(sp) @@ -17298,44 +17198,42 @@ define i64 @atomicrmw_umin_i64_acquire(i64 *%a, i64 %b) nounwind { ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s3, 12(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a5, 4(a0) -; RV32I-NEXT: lw a4, 0(a0) -; RV32I-NEXT: mv s1, a2 +; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s2, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a1, 4(a0) +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s3, sp -; RV32I-NEXT: bne a5, s1, .LBB216_3 +; RV32I-NEXT: bne a1, s0, .LBB216_3 ; RV32I-NEXT: j .LBB216_4 ; RV32I-NEXT: .LBB216_1: # %atomicrmw.start -; RV32I-NEXT: sw a4, 0(sp) -; RV32I-NEXT: sw a5, 4(sp) +; RV32I-NEXT: sw a1, 4(sp) +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: addi a5, zero, 2 -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: call __atomic_compare_exchange_8 -; RV32I-NEXT: lw a5, 4(sp) -; RV32I-NEXT: lw a4, 0(sp) +; RV32I-NEXT: lw a1, 4(sp) +; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: bnez a0, .LBB216_7 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start -; RV32I-NEXT: beq a5, s1, .LBB216_4 +; RV32I-NEXT: beq a1, s0, .LBB216_4 ; RV32I-NEXT: .LBB216_3: # %atomicrmw.start -; RV32I-NEXT: sltu a0, s1, a5 +; RV32I-NEXT: sltu a0, s0, a1 ; RV32I-NEXT: j .LBB216_5 ; RV32I-NEXT: .LBB216_4: -; RV32I-NEXT: sltu a0, s2, a4 +; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: .LBB216_5: # %atomicrmw.start ; RV32I-NEXT: xori a0, a0, 1 -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 +; RV32I-NEXT: sw a2, 0(sp) +; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: bnez a0, .LBB216_1 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: mv a2, s2 -; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: j .LBB216_1 ; RV32I-NEXT: .LBB216_7: # %atomicrmw.end -; RV32I-NEXT: mv a0, a4 -; RV32I-NEXT: mv a1, a5 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -17352,44 +17250,42 @@ define i64 @atomicrmw_umin_i64_acquire(i64 *%a, i64 %b) nounwind { ; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s3, 12(sp) -; RV32IA-NEXT: mv s0, a0 -; RV32IA-NEXT: lw a5, 4(a0) -; RV32IA-NEXT: lw a4, 0(a0) -; RV32IA-NEXT: mv s1, a2 +; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s2, a1 +; RV32IA-NEXT: mv s1, a0 +; RV32IA-NEXT: lw a1, 4(a0) +; RV32IA-NEXT: lw a2, 0(a0) ; RV32IA-NEXT: mv s3, sp -; RV32IA-NEXT: bne a5, s1, .LBB216_3 +; RV32IA-NEXT: bne a1, s0, .LBB216_3 ; RV32IA-NEXT: j .LBB216_4 ; RV32IA-NEXT: .LBB216_1: # %atomicrmw.start -; RV32IA-NEXT: sw a4, 0(sp) -; RV32IA-NEXT: sw a5, 4(sp) +; RV32IA-NEXT: sw a1, 4(sp) +; RV32IA-NEXT: mv a0, s1 +; RV32IA-NEXT: mv a1, s3 ; RV32IA-NEXT: addi a4, zero, 2 ; RV32IA-NEXT: addi a5, zero, 2 -; RV32IA-NEXT: mv a0, s0 -; RV32IA-NEXT: mv a1, s3 ; RV32IA-NEXT: call __atomic_compare_exchange_8 -; RV32IA-NEXT: lw a5, 4(sp) -; RV32IA-NEXT: lw a4, 0(sp) +; RV32IA-NEXT: lw a1, 4(sp) +; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: bnez a0, .LBB216_7 ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start -; RV32IA-NEXT: beq a5, s1, .LBB216_4 +; RV32IA-NEXT: beq a1, s0, .LBB216_4 ; RV32IA-NEXT: .LBB216_3: # %atomicrmw.start -; RV32IA-NEXT: sltu a0, s1, a5 +; RV32IA-NEXT: sltu a0, s0, a1 ; RV32IA-NEXT: j .LBB216_5 ; RV32IA-NEXT: .LBB216_4: -; RV32IA-NEXT: sltu a0, s2, a4 +; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: .LBB216_5: # %atomicrmw.start ; RV32IA-NEXT: xori a0, a0, 1 -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sw a2, 0(sp) +; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: bnez a0, .LBB216_1 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: mv a2, s2 -; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: j .LBB216_1 ; RV32IA-NEXT: .LBB216_7: # %atomicrmw.end -; RV32IA-NEXT: mv a0, a4 -; RV32IA-NEXT: mv a1, a5 +; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s1, 20(sp) @@ -17405,31 +17301,30 @@ define i64 @atomicrmw_umin_i64_acquire(i64 *%a, i64 %b) nounwind { ; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: ld a3, 0(a0) -; RV64I-NEXT: mv s1, a1 +; RV64I-NEXT: mv s0, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: addi s2, sp, 8 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bltu s1, a3, .LBB216_3 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: bltu s0, a2, .LBB216_3 ; RV64I-NEXT: .LBB216_1: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sd a3, 8(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: addi a3, zero, 2 ; RV64I-NEXT: addi a4, zero, 2 -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: call __atomic_compare_exchange_8 -; RV64I-NEXT: ld a3, 8(sp) +; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: bnez a0, .LBB216_4 ; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB216_1 Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s1, a3, .LBB216_1 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: bgeu s0, a2, .LBB216_1 ; RV64I-NEXT: .LBB216_3: # %atomicrmw.start -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: j .LBB216_1 ; RV64I-NEXT: .LBB216_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 +; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s0, 32(sp) @@ -17454,44 +17349,42 @@ define i64 @atomicrmw_umin_i64_release(i64 *%a, i64 %b) nounwind { ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s3, 12(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a5, 4(a0) -; RV32I-NEXT: lw a4, 0(a0) -; RV32I-NEXT: mv s1, a2 +; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s2, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a1, 4(a0) +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s3, sp -; RV32I-NEXT: bne a5, s1, .LBB217_3 +; RV32I-NEXT: bne a1, s0, .LBB217_3 ; RV32I-NEXT: j .LBB217_4 ; RV32I-NEXT: .LBB217_1: # %atomicrmw.start -; RV32I-NEXT: sw a4, 0(sp) -; RV32I-NEXT: sw a5, 4(sp) -; RV32I-NEXT: addi a4, zero, 3 -; RV32I-NEXT: mv a0, s0 +; RV32I-NEXT: sw a1, 4(sp) +; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s3 +; RV32I-NEXT: addi a4, zero, 3 ; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: call __atomic_compare_exchange_8 -; RV32I-NEXT: lw a5, 4(sp) -; RV32I-NEXT: lw a4, 0(sp) +; RV32I-NEXT: lw a1, 4(sp) +; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: bnez a0, .LBB217_7 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start -; RV32I-NEXT: beq a5, s1, .LBB217_4 +; RV32I-NEXT: beq a1, s0, .LBB217_4 ; RV32I-NEXT: .LBB217_3: # %atomicrmw.start -; RV32I-NEXT: sltu a0, s1, a5 +; RV32I-NEXT: sltu a0, s0, a1 ; RV32I-NEXT: j .LBB217_5 ; RV32I-NEXT: .LBB217_4: -; RV32I-NEXT: sltu a0, s2, a4 +; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: .LBB217_5: # %atomicrmw.start ; RV32I-NEXT: xori a0, a0, 1 -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 +; RV32I-NEXT: sw a2, 0(sp) +; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: bnez a0, .LBB217_1 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: mv a2, s2 -; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: j .LBB217_1 ; RV32I-NEXT: .LBB217_7: # %atomicrmw.end -; RV32I-NEXT: mv a0, a4 -; RV32I-NEXT: mv a1, a5 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -17508,44 +17401,42 @@ define i64 @atomicrmw_umin_i64_release(i64 *%a, i64 %b) nounwind { ; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s3, 12(sp) -; RV32IA-NEXT: mv s0, a0 -; RV32IA-NEXT: lw a5, 4(a0) -; RV32IA-NEXT: lw a4, 0(a0) -; RV32IA-NEXT: mv s1, a2 +; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s2, a1 +; RV32IA-NEXT: mv s1, a0 +; RV32IA-NEXT: lw a1, 4(a0) +; RV32IA-NEXT: lw a2, 0(a0) ; RV32IA-NEXT: mv s3, sp -; RV32IA-NEXT: bne a5, s1, .LBB217_3 +; RV32IA-NEXT: bne a1, s0, .LBB217_3 ; RV32IA-NEXT: j .LBB217_4 ; RV32IA-NEXT: .LBB217_1: # %atomicrmw.start -; RV32IA-NEXT: sw a4, 0(sp) -; RV32IA-NEXT: sw a5, 4(sp) -; RV32IA-NEXT: addi a4, zero, 3 -; RV32IA-NEXT: mv a0, s0 +; RV32IA-NEXT: sw a1, 4(sp) +; RV32IA-NEXT: mv a0, s1 ; RV32IA-NEXT: mv a1, s3 +; RV32IA-NEXT: addi a4, zero, 3 ; RV32IA-NEXT: mv a5, zero ; RV32IA-NEXT: call __atomic_compare_exchange_8 -; RV32IA-NEXT: lw a5, 4(sp) -; RV32IA-NEXT: lw a4, 0(sp) +; RV32IA-NEXT: lw a1, 4(sp) +; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: bnez a0, .LBB217_7 ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start -; RV32IA-NEXT: beq a5, s1, .LBB217_4 +; RV32IA-NEXT: beq a1, s0, .LBB217_4 ; RV32IA-NEXT: .LBB217_3: # %atomicrmw.start -; RV32IA-NEXT: sltu a0, s1, a5 +; RV32IA-NEXT: sltu a0, s0, a1 ; RV32IA-NEXT: j .LBB217_5 ; RV32IA-NEXT: .LBB217_4: -; RV32IA-NEXT: sltu a0, s2, a4 +; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: .LBB217_5: # %atomicrmw.start ; RV32IA-NEXT: xori a0, a0, 1 -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sw a2, 0(sp) +; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: bnez a0, .LBB217_1 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: mv a2, s2 -; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: j .LBB217_1 ; RV32IA-NEXT: .LBB217_7: # %atomicrmw.end -; RV32IA-NEXT: mv a0, a4 -; RV32IA-NEXT: mv a1, a5 +; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s1, 20(sp) @@ -17561,31 +17452,30 @@ define i64 @atomicrmw_umin_i64_release(i64 *%a, i64 %b) nounwind { ; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: ld a3, 0(a0) -; RV64I-NEXT: mv s1, a1 +; RV64I-NEXT: mv s0, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: addi s2, sp, 8 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bltu s1, a3, .LBB217_3 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: bltu s0, a2, .LBB217_3 ; RV64I-NEXT: .LBB217_1: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sd a3, 8(sp) -; RV64I-NEXT: addi a3, zero, 3 -; RV64I-NEXT: mv a0, s0 +; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a1, s2 +; RV64I-NEXT: addi a3, zero, 3 ; RV64I-NEXT: mv a4, zero ; RV64I-NEXT: call __atomic_compare_exchange_8 -; RV64I-NEXT: ld a3, 8(sp) +; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: bnez a0, .LBB217_4 ; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB217_1 Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s1, a3, .LBB217_1 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: bgeu s0, a2, .LBB217_1 ; RV64I-NEXT: .LBB217_3: # %atomicrmw.start -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: j .LBB217_1 ; RV64I-NEXT: .LBB217_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 +; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s0, 32(sp) @@ -17610,44 +17500,42 @@ define i64 @atomicrmw_umin_i64_acq_rel(i64 *%a, i64 %b) nounwind { ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s3, 12(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a5, 4(a0) -; RV32I-NEXT: lw a4, 0(a0) -; RV32I-NEXT: mv s1, a2 +; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s2, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a1, 4(a0) +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s3, sp -; RV32I-NEXT: bne a5, s1, .LBB218_3 +; RV32I-NEXT: bne a1, s0, .LBB218_3 ; RV32I-NEXT: j .LBB218_4 ; RV32I-NEXT: .LBB218_1: # %atomicrmw.start -; RV32I-NEXT: sw a4, 0(sp) -; RV32I-NEXT: sw a5, 4(sp) +; RV32I-NEXT: sw a1, 4(sp) +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: addi a4, zero, 4 ; RV32I-NEXT: addi a5, zero, 2 -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: call __atomic_compare_exchange_8 -; RV32I-NEXT: lw a5, 4(sp) -; RV32I-NEXT: lw a4, 0(sp) +; RV32I-NEXT: lw a1, 4(sp) +; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: bnez a0, .LBB218_7 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start -; RV32I-NEXT: beq a5, s1, .LBB218_4 +; RV32I-NEXT: beq a1, s0, .LBB218_4 ; RV32I-NEXT: .LBB218_3: # %atomicrmw.start -; RV32I-NEXT: sltu a0, s1, a5 +; RV32I-NEXT: sltu a0, s0, a1 ; RV32I-NEXT: j .LBB218_5 ; RV32I-NEXT: .LBB218_4: -; RV32I-NEXT: sltu a0, s2, a4 +; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: .LBB218_5: # %atomicrmw.start ; RV32I-NEXT: xori a0, a0, 1 -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 +; RV32I-NEXT: sw a2, 0(sp) +; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: bnez a0, .LBB218_1 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: mv a2, s2 -; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: j .LBB218_1 ; RV32I-NEXT: .LBB218_7: # %atomicrmw.end -; RV32I-NEXT: mv a0, a4 -; RV32I-NEXT: mv a1, a5 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -17664,44 +17552,42 @@ define i64 @atomicrmw_umin_i64_acq_rel(i64 *%a, i64 %b) nounwind { ; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s3, 12(sp) -; RV32IA-NEXT: mv s0, a0 -; RV32IA-NEXT: lw a5, 4(a0) -; RV32IA-NEXT: lw a4, 0(a0) -; RV32IA-NEXT: mv s1, a2 +; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s2, a1 +; RV32IA-NEXT: mv s1, a0 +; RV32IA-NEXT: lw a1, 4(a0) +; RV32IA-NEXT: lw a2, 0(a0) ; RV32IA-NEXT: mv s3, sp -; RV32IA-NEXT: bne a5, s1, .LBB218_3 +; RV32IA-NEXT: bne a1, s0, .LBB218_3 ; RV32IA-NEXT: j .LBB218_4 ; RV32IA-NEXT: .LBB218_1: # %atomicrmw.start -; RV32IA-NEXT: sw a4, 0(sp) -; RV32IA-NEXT: sw a5, 4(sp) +; RV32IA-NEXT: sw a1, 4(sp) +; RV32IA-NEXT: mv a0, s1 +; RV32IA-NEXT: mv a1, s3 ; RV32IA-NEXT: addi a4, zero, 4 ; RV32IA-NEXT: addi a5, zero, 2 -; RV32IA-NEXT: mv a0, s0 -; RV32IA-NEXT: mv a1, s3 ; RV32IA-NEXT: call __atomic_compare_exchange_8 -; RV32IA-NEXT: lw a5, 4(sp) -; RV32IA-NEXT: lw a4, 0(sp) +; RV32IA-NEXT: lw a1, 4(sp) +; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: bnez a0, .LBB218_7 ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start -; RV32IA-NEXT: beq a5, s1, .LBB218_4 +; RV32IA-NEXT: beq a1, s0, .LBB218_4 ; RV32IA-NEXT: .LBB218_3: # %atomicrmw.start -; RV32IA-NEXT: sltu a0, s1, a5 +; RV32IA-NEXT: sltu a0, s0, a1 ; RV32IA-NEXT: j .LBB218_5 ; RV32IA-NEXT: .LBB218_4: -; RV32IA-NEXT: sltu a0, s2, a4 +; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: .LBB218_5: # %atomicrmw.start ; RV32IA-NEXT: xori a0, a0, 1 -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sw a2, 0(sp) +; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: bnez a0, .LBB218_1 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: mv a2, s2 -; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: j .LBB218_1 ; RV32IA-NEXT: .LBB218_7: # %atomicrmw.end -; RV32IA-NEXT: mv a0, a4 -; RV32IA-NEXT: mv a1, a5 +; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s1, 20(sp) @@ -17717,31 +17603,30 @@ define i64 @atomicrmw_umin_i64_acq_rel(i64 *%a, i64 %b) nounwind { ; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: ld a3, 0(a0) -; RV64I-NEXT: mv s1, a1 +; RV64I-NEXT: mv s0, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: addi s2, sp, 8 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bltu s1, a3, .LBB218_3 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: bltu s0, a2, .LBB218_3 ; RV64I-NEXT: .LBB218_1: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sd a3, 8(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: addi a3, zero, 4 ; RV64I-NEXT: addi a4, zero, 2 -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: call __atomic_compare_exchange_8 -; RV64I-NEXT: ld a3, 8(sp) +; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: bnez a0, .LBB218_4 ; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB218_1 Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s1, a3, .LBB218_1 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: bgeu s0, a2, .LBB218_1 ; RV64I-NEXT: .LBB218_3: # %atomicrmw.start -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: j .LBB218_1 ; RV64I-NEXT: .LBB218_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 +; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s0, 32(sp) @@ -17766,44 +17651,42 @@ define i64 @atomicrmw_umin_i64_seq_cst(i64 *%a, i64 %b) nounwind { ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s3, 12(sp) -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lw a5, 4(a0) -; RV32I-NEXT: lw a4, 0(a0) -; RV32I-NEXT: mv s1, a2 +; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s2, a1 +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lw a1, 4(a0) +; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: mv s3, sp -; RV32I-NEXT: bne a5, s1, .LBB219_3 +; RV32I-NEXT: bne a1, s0, .LBB219_3 ; RV32I-NEXT: j .LBB219_4 ; RV32I-NEXT: .LBB219_1: # %atomicrmw.start -; RV32I-NEXT: sw a4, 0(sp) -; RV32I-NEXT: sw a5, 4(sp) +; RV32I-NEXT: sw a1, 4(sp) +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: addi a4, zero, 5 ; RV32I-NEXT: addi a5, zero, 5 -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: call __atomic_compare_exchange_8 -; RV32I-NEXT: lw a5, 4(sp) -; RV32I-NEXT: lw a4, 0(sp) +; RV32I-NEXT: lw a1, 4(sp) +; RV32I-NEXT: lw a2, 0(sp) ; RV32I-NEXT: bnez a0, .LBB219_7 ; RV32I-NEXT: # %bb.2: # %atomicrmw.start -; RV32I-NEXT: beq a5, s1, .LBB219_4 +; RV32I-NEXT: beq a1, s0, .LBB219_4 ; RV32I-NEXT: .LBB219_3: # %atomicrmw.start -; RV32I-NEXT: sltu a0, s1, a5 +; RV32I-NEXT: sltu a0, s0, a1 ; RV32I-NEXT: j .LBB219_5 ; RV32I-NEXT: .LBB219_4: -; RV32I-NEXT: sltu a0, s2, a4 +; RV32I-NEXT: sltu a0, s2, a2 ; RV32I-NEXT: .LBB219_5: # %atomicrmw.start ; RV32I-NEXT: xori a0, a0, 1 -; RV32I-NEXT: mv a2, a4 -; RV32I-NEXT: mv a3, a5 +; RV32I-NEXT: sw a2, 0(sp) +; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: bnez a0, .LBB219_1 ; RV32I-NEXT: # %bb.6: # %atomicrmw.start ; RV32I-NEXT: mv a2, s2 -; RV32I-NEXT: mv a3, s1 +; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: j .LBB219_1 ; RV32I-NEXT: .LBB219_7: # %atomicrmw.end -; RV32I-NEXT: mv a0, a4 -; RV32I-NEXT: mv a1, a5 +; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) @@ -17820,44 +17703,42 @@ define i64 @atomicrmw_umin_i64_seq_cst(i64 *%a, i64 %b) nounwind { ; RV32IA-NEXT: sw s1, 20(sp) ; RV32IA-NEXT: sw s2, 16(sp) ; RV32IA-NEXT: sw s3, 12(sp) -; RV32IA-NEXT: mv s0, a0 -; RV32IA-NEXT: lw a5, 4(a0) -; RV32IA-NEXT: lw a4, 0(a0) -; RV32IA-NEXT: mv s1, a2 +; RV32IA-NEXT: mv s0, a2 ; RV32IA-NEXT: mv s2, a1 +; RV32IA-NEXT: mv s1, a0 +; RV32IA-NEXT: lw a1, 4(a0) +; RV32IA-NEXT: lw a2, 0(a0) ; RV32IA-NEXT: mv s3, sp -; RV32IA-NEXT: bne a5, s1, .LBB219_3 +; RV32IA-NEXT: bne a1, s0, .LBB219_3 ; RV32IA-NEXT: j .LBB219_4 ; RV32IA-NEXT: .LBB219_1: # %atomicrmw.start -; RV32IA-NEXT: sw a4, 0(sp) -; RV32IA-NEXT: sw a5, 4(sp) +; RV32IA-NEXT: sw a1, 4(sp) +; RV32IA-NEXT: mv a0, s1 +; RV32IA-NEXT: mv a1, s3 ; RV32IA-NEXT: addi a4, zero, 5 ; RV32IA-NEXT: addi a5, zero, 5 -; RV32IA-NEXT: mv a0, s0 -; RV32IA-NEXT: mv a1, s3 ; RV32IA-NEXT: call __atomic_compare_exchange_8 -; RV32IA-NEXT: lw a5, 4(sp) -; RV32IA-NEXT: lw a4, 0(sp) +; RV32IA-NEXT: lw a1, 4(sp) +; RV32IA-NEXT: lw a2, 0(sp) ; RV32IA-NEXT: bnez a0, .LBB219_7 ; RV32IA-NEXT: # %bb.2: # %atomicrmw.start -; RV32IA-NEXT: beq a5, s1, .LBB219_4 +; RV32IA-NEXT: beq a1, s0, .LBB219_4 ; RV32IA-NEXT: .LBB219_3: # %atomicrmw.start -; RV32IA-NEXT: sltu a0, s1, a5 +; RV32IA-NEXT: sltu a0, s0, a1 ; RV32IA-NEXT: j .LBB219_5 ; RV32IA-NEXT: .LBB219_4: -; RV32IA-NEXT: sltu a0, s2, a4 +; RV32IA-NEXT: sltu a0, s2, a2 ; RV32IA-NEXT: .LBB219_5: # %atomicrmw.start ; RV32IA-NEXT: xori a0, a0, 1 -; RV32IA-NEXT: mv a2, a4 -; RV32IA-NEXT: mv a3, a5 +; RV32IA-NEXT: sw a2, 0(sp) +; RV32IA-NEXT: mv a3, a1 ; RV32IA-NEXT: bnez a0, .LBB219_1 ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: mv a2, s2 -; RV32IA-NEXT: mv a3, s1 +; RV32IA-NEXT: mv a3, s0 ; RV32IA-NEXT: j .LBB219_1 ; RV32IA-NEXT: .LBB219_7: # %atomicrmw.end -; RV32IA-NEXT: mv a0, a4 -; RV32IA-NEXT: mv a1, a5 +; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: lw s3, 12(sp) ; RV32IA-NEXT: lw s2, 16(sp) ; RV32IA-NEXT: lw s1, 20(sp) @@ -17873,31 +17754,30 @@ define i64 @atomicrmw_umin_i64_seq_cst(i64 *%a, i64 %b) nounwind { ; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) -; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: ld a3, 0(a0) -; RV64I-NEXT: mv s1, a1 +; RV64I-NEXT: mv s0, a1 +; RV64I-NEXT: mv s1, a0 +; RV64I-NEXT: ld a2, 0(a0) ; RV64I-NEXT: addi s2, sp, 8 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bltu s1, a3, .LBB219_3 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: bltu s0, a2, .LBB219_3 ; RV64I-NEXT: .LBB219_1: # %atomicrmw.start ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sd a3, 8(sp) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: addi a3, zero, 5 ; RV64I-NEXT: addi a4, zero, 5 -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: call __atomic_compare_exchange_8 -; RV64I-NEXT: ld a3, 8(sp) +; RV64I-NEXT: ld a2, 8(sp) ; RV64I-NEXT: bnez a0, .LBB219_4 ; RV64I-NEXT: # %bb.2: # %atomicrmw.start ; RV64I-NEXT: # in Loop: Header=BB219_1 Depth=1 -; RV64I-NEXT: mv a2, a3 -; RV64I-NEXT: bgeu s1, a3, .LBB219_1 +; RV64I-NEXT: sd a2, 8(sp) +; RV64I-NEXT: bgeu s0, a2, .LBB219_1 ; RV64I-NEXT: .LBB219_3: # %atomicrmw.start -; RV64I-NEXT: mv a2, s1 +; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: j .LBB219_1 ; RV64I-NEXT: .LBB219_4: # %atomicrmw.end -; RV64I-NEXT: mv a0, a3 +; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s0, 32(sp) |
