diff options
Diffstat (limited to 'llvm/test/CodeGen/RISCV/arith-with-overflow.ll')
| -rw-r--r-- | llvm/test/CodeGen/RISCV/arith-with-overflow.ll | 46 |
1 files changed, 23 insertions, 23 deletions
diff --git a/llvm/test/CodeGen/RISCV/arith-with-overflow.ll b/llvm/test/CodeGen/RISCV/arith-with-overflow.ll index 3fb6342133e..8d720824119 100644 --- a/llvm/test/CodeGen/RISCV/arith-with-overflow.ll +++ b/llvm/test/CodeGen/RISCV/arith-with-overflow.ll @@ -10,17 +10,17 @@ declare {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b) define i1 @sadd(i32 %a, i32 %b, i32* %c) nounwind { ; RV32I-LABEL: sadd: ; RV32I: # %bb.0: # %entry -; RV32I-NEXT: add a3, a0, a1 -; RV32I-NEXT: sw a3, 0(a2) -; RV32I-NEXT: addi a2, zero, -1 -; RV32I-NEXT: slt a1, a2, a1 -; RV32I-NEXT: slt a0, a2, a0 -; RV32I-NEXT: slt a2, a2, a3 -; RV32I-NEXT: xor a2, a0, a2 -; RV32I-NEXT: xor a0, a0, a1 -; RV32I-NEXT: seqz a0, a0 -; RV32I-NEXT: snez a1, a2 -; RV32I-NEXT: and a0, a0, a1 +; RV32I-NEXT: addi a3, zero, -1 +; RV32I-NEXT: slt a4, a3, a1 +; RV32I-NEXT: slt a5, a3, a0 +; RV32I-NEXT: xor a4, a5, a4 +; RV32I-NEXT: seqz a4, a4 +; RV32I-NEXT: add a1, a0, a1 +; RV32I-NEXT: slt a0, a3, a1 +; RV32I-NEXT: xor a0, a5, a0 +; RV32I-NEXT: snez a0, a0 +; RV32I-NEXT: and a0, a4, a0 +; RV32I-NEXT: sw a1, 0(a2) ; RV32I-NEXT: ret entry: %x = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a, i32 %b) @@ -33,17 +33,17 @@ entry: define i1 @ssub(i32 %a, i32 %b, i32* %c) nounwind { ; RV32I-LABEL: ssub: ; RV32I: # %bb.0: # %entry -; RV32I-NEXT: sub a3, a0, a1 -; RV32I-NEXT: sw a3, 0(a2) -; RV32I-NEXT: addi a2, zero, -1 -; RV32I-NEXT: slt a1, a2, a1 -; RV32I-NEXT: slt a0, a2, a0 -; RV32I-NEXT: slt a2, a2, a3 -; RV32I-NEXT: xor a2, a0, a2 -; RV32I-NEXT: xor a0, a0, a1 +; RV32I-NEXT: addi a3, zero, -1 +; RV32I-NEXT: slt a4, a3, a1 +; RV32I-NEXT: slt a5, a3, a0 +; RV32I-NEXT: xor a4, a5, a4 +; RV32I-NEXT: snez a4, a4 +; RV32I-NEXT: sub a1, a0, a1 +; RV32I-NEXT: slt a0, a3, a1 +; RV32I-NEXT: xor a0, a5, a0 ; RV32I-NEXT: snez a0, a0 -; RV32I-NEXT: snez a1, a2 -; RV32I-NEXT: and a0, a0, a1 +; RV32I-NEXT: and a0, a4, a0 +; RV32I-NEXT: sw a1, 0(a2) ; RV32I-NEXT: ret entry: %x = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %a, i32 %b) @@ -57,8 +57,8 @@ define i1 @uadd(i32 %a, i32 %b, i32* %c) nounwind { ; RV32I-LABEL: uadd: ; RV32I: # %bb.0: # %entry ; RV32I-NEXT: add a1, a0, a1 -; RV32I-NEXT: sw a1, 0(a2) ; RV32I-NEXT: sltu a0, a1, a0 +; RV32I-NEXT: sw a1, 0(a2) ; RV32I-NEXT: ret entry: %x = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b) @@ -72,8 +72,8 @@ define i1 @usub(i32 %a, i32 %b, i32* %c) nounwind { ; RV32I-LABEL: usub: ; RV32I: # %bb.0: # %entry ; RV32I-NEXT: sub a1, a0, a1 -; RV32I-NEXT: sw a1, 0(a2) ; RV32I-NEXT: sltu a0, a0, a1 +; RV32I-NEXT: sw a1, 0(a2) ; RV32I-NEXT: ret entry: %x = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b) |
