diff options
Diffstat (limited to 'llvm/test/CodeGen/R600/or.ll')
| -rw-r--r-- | llvm/test/CodeGen/R600/or.ll | 64 |
1 files changed, 32 insertions, 32 deletions
diff --git a/llvm/test/CodeGen/R600/or.ll b/llvm/test/CodeGen/R600/or.ll index dbe3326fb24..99dedac809e 100644 --- a/llvm/test/CodeGen/R600/or.ll +++ b/llvm/test/CodeGen/R600/or.ll @@ -6,8 +6,8 @@ ; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; SI-LABEL: {{^}}or_v2i32: -; SI: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -; SI: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} define void @or_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1 @@ -25,10 +25,10 @@ define void @or_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) ; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; SI-LABEL: {{^}}or_v4i32: -; SI: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -; SI: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -; SI: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -; SI: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} define void @or_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 @@ -40,7 +40,7 @@ define void @or_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) } ; SI-LABEL: {{^}}scalar_or_i32: -; SI: S_OR_B32 +; SI: s_or_b32 define void @scalar_or_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) { %or = or i32 %a, %b store i32 %or, i32 addrspace(1)* %out @@ -48,7 +48,7 @@ define void @scalar_or_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) { } ; SI-LABEL: {{^}}vector_or_i32: -; SI: V_OR_B32_e32 v{{[0-9]}} +; SI: v_or_b32_e32 v{{[0-9]}} define void @vector_or_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 %b) { %loada = load i32 addrspace(1)* %a %or = or i32 %loada, %b @@ -57,7 +57,7 @@ define void @vector_or_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 %b) } ; SI-LABEL: {{^}}scalar_or_literal_i32: -; SI: S_OR_B32 s{{[0-9]+}}, s{{[0-9]+}}, 0x1869f +; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x1869f define void @scalar_or_literal_i32(i32 addrspace(1)* %out, i32 %a) { %or = or i32 %a, 99999 store i32 %or, i32 addrspace(1)* %out, align 4 @@ -65,7 +65,7 @@ define void @scalar_or_literal_i32(i32 addrspace(1)* %out, i32 %a) { } ; SI-LABEL: {{^}}vector_or_literal_i32: -; SI: V_OR_B32_e32 v{{[0-9]+}}, 0xffff, v{{[0-9]+}} +; SI: v_or_b32_e32 v{{[0-9]+}}, 0xffff, v{{[0-9]+}} define void @vector_or_literal_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 addrspace(1)* %b) { %loada = load i32 addrspace(1)* %a, align 4 %or = or i32 %loada, 65535 @@ -74,7 +74,7 @@ define void @vector_or_literal_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, } ; SI-LABEL: {{^}}vector_or_inline_immediate_i32: -; SI: V_OR_B32_e32 v{{[0-9]+}}, 4, v{{[0-9]+}} +; SI: v_or_b32_e32 v{{[0-9]+}}, 4, v{{[0-9]+}} define void @vector_or_inline_immediate_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 addrspace(1)* %b) { %loada = load i32 addrspace(1)* %a, align 4 %or = or i32 %loada, 4 @@ -86,7 +86,7 @@ define void @vector_or_inline_immediate_i32(i32 addrspace(1)* %out, i32 addrspac ; EG-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y ; EG-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[3].X, KC0[3].Z ; SI-LABEL: {{^}}scalar_or_i64: -; SI: S_OR_B64 +; SI: s_or_b64 define void @scalar_or_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) { %or = or i64 %a, %b store i64 %or, i64 addrspace(1)* %out @@ -94,8 +94,8 @@ define void @scalar_or_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) { } ; SI-LABEL: {{^}}vector_or_i64: -; SI: V_OR_B32_e32 v{{[0-9]}} -; SI: V_OR_B32_e32 v{{[0-9]}} +; SI: v_or_b32_e32 v{{[0-9]}} +; SI: v_or_b32_e32 v{{[0-9]}} define void @vector_or_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) { %loada = load i64 addrspace(1)* %a, align 8 %loadb = load i64 addrspace(1)* %a, align 8 @@ -105,8 +105,8 @@ define void @vector_or_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 add } ; SI-LABEL: {{^}}scalar_vector_or_i64: -; SI: V_OR_B32_e32 v{{[0-9]}} -; SI: V_OR_B32_e32 v{{[0-9]}} +; SI: v_or_b32_e32 v{{[0-9]}} +; SI: v_or_b32_e32 v{{[0-9]}} define void @scalar_vector_or_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 %b) { %loada = load i64 addrspace(1)* %a %or = or i64 %loada, %b @@ -115,12 +115,12 @@ define void @scalar_vector_or_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a, } ; SI-LABEL: {{^}}vector_or_i64_loadimm: -; SI-DAG: S_MOV_B32 [[LO_S_IMM:s[0-9]+]], 0xdf77987f -; SI-DAG: S_MOV_B32 [[HI_S_IMM:s[0-9]+]], 0x146f -; SI-DAG: BUFFER_LOAD_DWORDX2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, -; SI-DAG: V_OR_B32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]] -; SI-DAG: V_OR_B32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]] -; SI: S_ENDPGM +; SI-DAG: s_mov_b32 [[LO_S_IMM:s[0-9]+]], 0xdf77987f +; SI-DAG: s_mov_b32 [[HI_S_IMM:s[0-9]+]], 0x146f +; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, +; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]] +; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]] +; SI: s_endpgm define void @vector_or_i64_loadimm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) { %loada = load i64 addrspace(1)* %a, align 8 %or = or i64 %loada, 22470723082367 @@ -130,10 +130,10 @@ define void @vector_or_i64_loadimm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, ; FIXME: The or 0 should really be removed. ; SI-LABEL: {{^}}vector_or_i64_imm: -; SI: BUFFER_LOAD_DWORDX2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, -; SI: V_OR_B32_e32 {{v[0-9]+}}, 8, v[[LO_VREG]] -; SI: V_OR_B32_e32 {{v[0-9]+}}, 0, {{.*}} -; SI: S_ENDPGM +; SI: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, +; SI: v_or_b32_e32 {{v[0-9]+}}, 8, v[[LO_VREG]] +; SI: v_or_b32_e32 {{v[0-9]+}}, 0, {{.*}} +; SI: s_endpgm define void @vector_or_i64_imm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) { %loada = load i64 addrspace(1)* %a, align 8 %or = or i64 %loada, 8 @@ -142,11 +142,11 @@ define void @vector_or_i64_imm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 } ; SI-LABEL: {{^}}trunc_i64_or_to_i32: -; SI: S_LOAD_DWORD s[[SREG0:[0-9]+]] -; SI: S_LOAD_DWORD s[[SREG1:[0-9]+]] -; SI: S_OR_B32 s[[SRESULT:[0-9]+]], s[[SREG1]], s[[SREG0]] -; SI: V_MOV_B32_e32 [[VRESULT:v[0-9]+]], s[[SRESULT]] -; SI: BUFFER_STORE_DWORD [[VRESULT]], +; SI: s_load_dword s[[SREG0:[0-9]+]] +; SI: s_load_dword s[[SREG1:[0-9]+]] +; SI: s_or_b32 s[[SRESULT:[0-9]+]], s[[SREG1]], s[[SREG0]] +; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], s[[SRESULT]] +; SI: buffer_store_dword [[VRESULT]], define void @trunc_i64_or_to_i32(i32 addrspace(1)* %out, i64 %a, i64 %b) { %add = or i64 %b, %a %trunc = trunc i64 %add to i32 @@ -158,7 +158,7 @@ define void @trunc_i64_or_to_i32(i32 addrspace(1)* %out, i64 %a, i64 %b) { ; EG-CHECK: OR_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], PS}} ; SI-CHECK: {{^}}or_i1: -; SI-CHECK: S_OR_B64 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] +; SI-CHECK: s_or_b64 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] define void @or_i1(float addrspace(1)* %out, float addrspace(1)* %in0, float addrspace(1)* %in1) { %a = load float addrspace(1) * %in0 %b = load float addrspace(1) * %in1 |
