diff options
Diffstat (limited to 'llvm/test/CodeGen/PowerPC')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/byval-agg-info.ll | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/combine_loads_from_build_pair.ll | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/unal-vec-negarith.ll | 4 |
3 files changed, 8 insertions, 8 deletions
diff --git a/llvm/test/CodeGen/PowerPC/byval-agg-info.ll b/llvm/test/CodeGen/PowerPC/byval-agg-info.ll index ec53dee3155..21aa5821c88 100644 --- a/llvm/test/CodeGen/PowerPC/byval-agg-info.ll +++ b/llvm/test/CodeGen/PowerPC/byval-agg-info.ll @@ -12,6 +12,6 @@ entry: } ; Make sure that the MMO on the store has no offset from the byval -; variable itself (we used to have mem:ST8[%v+64]). -; CHECK: STD killed renamable $x5, 176, $x1; mem:ST8[%v](align=16) +; variable itself (we used to have (store 8 into %ir.v + 64)). +; CHECK: STD killed renamable $x5, 176, $x1 :: (store 8 into %ir.v, align 16) diff --git a/llvm/test/CodeGen/PowerPC/combine_loads_from_build_pair.ll b/llvm/test/CodeGen/PowerPC/combine_loads_from_build_pair.ll index 45cc740d1ea..37240c575fa 100644 --- a/llvm/test/CodeGen/PowerPC/combine_loads_from_build_pair.ll +++ b/llvm/test/CodeGen/PowerPC/combine_loads_from_build_pair.ll @@ -9,13 +9,13 @@ define i64 @func1(i64 %p1, i64 %p2, i64 %p3, i64 %p4, { i64, i8* } %struct) { ; so we expect the LD8 to load from the address used in the original HIBITS ; load. ; CHECK-LABEL: Initial selection DAG: -; CHECK-DAG: [[LOBITS:t[0-9]+]]: i32,ch = load<LD4[FixedStack-2]> -; CHECK-DAG: [[HIBITS:t[0-9]+]]: i32,ch = load<LD4[FixedStack-1]> +; CHECK-DAG: [[LOBITS:t[0-9]+]]: i32,ch = load<(load 4 from %fixed-stack.1)> +; CHECK-DAG: [[HIBITS:t[0-9]+]]: i32,ch = load<(load 4 from %fixed-stack.2)> ; CHECK: Combining: t{{[0-9]+}}: i64 = build_pair [[LOBITS]], [[HIBITS]] ; CHECK-NEXT: Creating new node -; CHECK-SAME: load<LD8[FixedStack-1] +; CHECK-SAME: load<(load 8 from %fixed-stack.2, align 4)> ; CHECK-NEXT: into -; CHECK-SAME: load<LD8[FixedStack-1] +; CHECK-SAME: load<(load 8 from %fixed-stack.2, align 4)> ; CHECK-LABEL: Optimized lowered selection DAG: %result = extractvalue {i64, i8* } %struct, 0 ret i64 %result diff --git a/llvm/test/CodeGen/PowerPC/unal-vec-negarith.ll b/llvm/test/CodeGen/PowerPC/unal-vec-negarith.ll index 98bf2bc4794..625b9b4b41d 100644 --- a/llvm/test/CodeGen/PowerPC/unal-vec-negarith.ll +++ b/llvm/test/CodeGen/PowerPC/unal-vec-negarith.ll @@ -9,8 +9,8 @@ entry: %r = load <16 x i8>, <16 x i8>* %p, align 1 ret <16 x i8> %r -; CHECK-NOT: v4i32,ch = llvm.ppc.altivec.lvx{{.*}}<LD31[%p+4294967281](align=1)> -; CHECK: v4i32,ch = llvm.ppc.altivec.lvx{{.*}}<LD31[%p+-15](align=1)> +; CHECK-NOT: v4i32,ch = llvm.ppc.altivec.lvx{{.*}}<(load 31 from %ir.p + 4294967281, align 1)> +; CHECK: v4i32,ch = llvm.ppc.altivec.lvx{{.*}}<(load 31 from %ir.p - 15, align 1)> } attributes #0 = { nounwind "target-cpu"="pwr7" } |
