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-rw-r--r--llvm/test/CodeGen/PowerPC/addi-licm.ll4
-rw-r--r--llvm/test/CodeGen/PowerPC/ctrloop-ne.ll36
-rw-r--r--llvm/test/CodeGen/PowerPC/ctrloop-shortLoops.ll6
-rw-r--r--llvm/test/CodeGen/PowerPC/lsr-ctrloop.ll49
-rw-r--r--llvm/test/CodeGen/PowerPC/negctr.ll10
-rw-r--r--llvm/test/CodeGen/PowerPC/stwu-sched.ll14
-rw-r--r--llvm/test/CodeGen/PowerPC/unal-altivec.ll13
7 files changed, 62 insertions, 70 deletions
diff --git a/llvm/test/CodeGen/PowerPC/addi-licm.ll b/llvm/test/CodeGen/PowerPC/addi-licm.ll
index d0178a8aec0..e0314d19bd3 100644
--- a/llvm/test/CodeGen/PowerPC/addi-licm.ll
+++ b/llvm/test/CodeGen/PowerPC/addi-licm.ll
@@ -18,8 +18,8 @@ entry:
; CHECK: addi [[REG1:[0-9]+]], 1,
; CHECK: addi [[REG2:[0-9]+]], 1,
; CHECK: %for.body.i
-; CHECK-DAG: lfsx {{[0-9]+}}, [[REG1]],
-; CHECK-DAG: lfsx {{[0-9]+}}, [[REG2]],
+; CHECK-DAG: lfs {{[0-9]+}}, 0([[REG1]])
+; CHECK-DAG: lfs {{[0-9]+}}, 0([[REG2]])
; CHECK: blr
; PIP-LABEL: @foo
diff --git a/llvm/test/CodeGen/PowerPC/ctrloop-ne.ll b/llvm/test/CodeGen/PowerPC/ctrloop-ne.ll
index 253b8d020ad..2cf95329019 100644
--- a/llvm/test/CodeGen/PowerPC/ctrloop-ne.ll
+++ b/llvm/test/CodeGen/PowerPC/ctrloop-ne.ll
@@ -32,8 +32,7 @@ for.end: ; preds = %for.body, %entry
; CHECK: test_pos2_ir_ne
-; FIXME: Support this loop!
-; CHECK-NOT: bdnz
+; CHECK: bdnz
; a < b
define void @test_pos2_ir_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
entry:
@@ -62,8 +61,7 @@ for.end: ; preds = %for.body, %entry
; CHECK: test_pos4_ir_ne
-; FIXME: Support this loop!
-; CHECK-NOT: bdnz
+; CHECK: bdnz
; a < b
define void @test_pos4_ir_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
entry:
@@ -92,8 +90,7 @@ for.end: ; preds = %for.body, %entry
; CHECK: test_pos8_ir_ne
-; FIXME: Support this loop!
-; CHECK-NOT: bdnz
+; CHECK: bdnz
; a < b
define void @test_pos8_ir_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
entry:
@@ -122,8 +119,7 @@ for.end: ; preds = %for.body, %entry
; CHECK: test_pos16_ir_ne
-; FIXME: Support this loop!
-; CHECK-NOT: bdnz
+; CHECK: bdnz
; a < b
define void @test_pos16_ir_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
entry:
@@ -181,8 +177,7 @@ for.end: ; preds = %for.body, %entry
; CHECK: test_pos2_ri_ne
-; FIXME: Support this loop!
-; CHECK-NOT: bdnz
+; CHECK: bdnz
; a < b
define void @test_pos2_ri_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
entry:
@@ -211,8 +206,7 @@ for.end: ; preds = %for.body, %entry
; CHECK: test_pos4_ri_ne
-; FIXME: Support this loop!
-; CHECK-NOT: bdnz
+; CHECK: bdnz
; a < b
define void @test_pos4_ri_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
entry:
@@ -241,8 +235,7 @@ for.end: ; preds = %for.body, %entry
; CHECK: test_pos8_ri_ne
-; FIXME: Support this loop!
-; CHECK-NOT: bdnz
+; CHECK: bdnz
; a < b
define void @test_pos8_ri_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
entry:
@@ -271,8 +264,7 @@ for.end: ; preds = %for.body, %entry
; CHECK: test_pos16_ri_ne
-; FIXME: Support this loop!
-; CHECK-NOT: bdnz
+; CHECK: bdnz
; a < b
define void @test_pos16_ri_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
entry:
@@ -330,8 +322,7 @@ for.end: ; preds = %for.body, %entry
; CHECK: test_pos2_rr_ne
-; FIXME: Support this loop!
-; CHECK-NOT: bdnz
+; CHECK: bdnz
; a < b
define void @test_pos2_rr_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
entry:
@@ -360,8 +351,7 @@ for.end: ; preds = %for.body, %entry
; CHECK: test_pos4_rr_ne
-; FIXME: Support this loop!
-; CHECK-NOT: bdnz
+; CHECK: bdnz
; a < b
define void @test_pos4_rr_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
entry:
@@ -390,8 +380,7 @@ for.end: ; preds = %for.body, %entry
; CHECK: test_pos8_rr_ne
-; FIXME: Support this loop!
-; CHECK-NOT: bdnz
+; CHECK: bdnz
; a < b
define void @test_pos8_rr_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
entry:
@@ -420,8 +409,7 @@ for.end: ; preds = %for.body, %entry
; CHECK: test_pos16_rr_ne
-; FIXME: Support this loop!
-; CHECK-NOT: bdnz
+; CHECK: bdnz
; a < b
define void @test_pos16_rr_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
entry:
diff --git a/llvm/test/CodeGen/PowerPC/ctrloop-shortLoops.ll b/llvm/test/CodeGen/PowerPC/ctrloop-shortLoops.ll
index 7681be96c5e..4f904d6fe09 100644
--- a/llvm/test/CodeGen/PowerPC/ctrloop-shortLoops.ll
+++ b/llvm/test/CodeGen/PowerPC/ctrloop-shortLoops.ll
@@ -86,10 +86,12 @@ for.body: ; preds = %entry, %for.body
}
; Function Attrs: norecurse nounwind
+; On core a2q, IssueWidth is 1. On core pwr8, IssueWidth is 8.
+; a2q should use mtctr, but pwr8 should not use mtctr.
define signext i32 @testTripCount2NonSmallLoop() {
; CHECK-LABEL: testTripCount2NonSmallLoop:
-; CHECK: blt
-; CHECK: beq
+; CHECK-A2Q: mtctr
+; CHECK-PWR8-NOT: mtctr
; CHECK: blr
entry:
diff --git a/llvm/test/CodeGen/PowerPC/lsr-ctrloop.ll b/llvm/test/CodeGen/PowerPC/lsr-ctrloop.ll
index 14fd4c96dea..72e17f820ad 100644
--- a/llvm/test/CodeGen/PowerPC/lsr-ctrloop.ll
+++ b/llvm/test/CodeGen/PowerPC/lsr-ctrloop.ll
@@ -14,32 +14,31 @@
define void @foo(float* nocapture %data, float %d) {
; CHECK-LABEL: foo:
; CHECK: .LBB0_1: # %vector.body
-; CHECK: add 5, 3, 4
-; CHECK-NEXT: stxvx 0, 3, 4
+; CHECK: stxv 0, -192(4)
+; CHECK-NEXT: stxv 0, -176(4)
+; CHECK-NEXT: stxv 0, -160(4)
+; CHECK-NEXT: stxv 0, -144(4)
+; CHECK-NEXT: stxv 0, -128(4)
+; CHECK-NEXT: stxv 0, -112(4)
+; CHECK-NEXT: stxv 0, -96(4)
+; CHECK-NEXT: stxv 0, -80(4)
+; CHECK-NEXT: stxv 0, -64(4)
+; CHECK-NEXT: stxv 0, -48(4)
+; CHECK-NEXT: stxv 0, -32(4)
+; CHECK-NEXT: stxv 0, -16(4)
+; CHECK-NEXT: stxv 0, 0(4)
+; CHECK-NEXT: stxv 0, 16(4)
+; CHECK-NEXT: stxv 0, 32(4)
+; CHECK-NEXT: stxv 0, 48(4)
+; CHECK-NEXT: stxv 0, 64(4)
+; CHECK-NEXT: stxv 0, 80(4)
+; CHECK-NEXT: stxv 0, 96(4)
+; CHECK-NEXT: stxv 0, 112(4)
+; CHECK-NEXT: stxv 0, 128(4)
+; CHECK-NEXT: stxv 0, 144(4)
+; CHECK-NEXT: stxv 0, 160(4)
+; CHECK-NEXT: stxv 0, 176(4)
; CHECK-NEXT: addi 4, 4, 384
-; CHECK-NEXT: stxv 0, 16(5)
-; CHECK-NEXT: stxv 0, 32(5)
-; CHECK-NEXT: stxv 0, 48(5)
-; CHECK-NEXT: stxv 0, 64(5)
-; CHECK-NEXT: stxv 0, 80(5)
-; CHECK-NEXT: stxv 0, 96(5)
-; CHECK-NEXT: stxv 0, 112(5)
-; CHECK-NEXT: stxv 0, 128(5)
-; CHECK-NEXT: stxv 0, 144(5)
-; CHECK-NEXT: stxv 0, 160(5)
-; CHECK-NEXT: stxv 0, 176(5)
-; CHECK-NEXT: stxv 0, 192(5)
-; CHECK-NEXT: stxv 0, 208(5)
-; CHECK-NEXT: stxv 0, 224(5)
-; CHECK-NEXT: stxv 0, 240(5)
-; CHECK-NEXT: stxv 0, 256(5)
-; CHECK-NEXT: stxv 0, 272(5)
-; CHECK-NEXT: stxv 0, 288(5)
-; CHECK-NEXT: stxv 0, 304(5)
-; CHECK-NEXT: stxv 0, 320(5)
-; CHECK-NEXT: stxv 0, 336(5)
-; CHECK-NEXT: stxv 0, 352(5)
-; CHECK-NEXT: stxv 0, 368(5)
; CHECK-NEXT: bdnz .LBB0_1
entry:
diff --git a/llvm/test/CodeGen/PowerPC/negctr.ll b/llvm/test/CodeGen/PowerPC/negctr.ll
index 7ed4b6ae4b8..5aa5bd1fa69 100644
--- a/llvm/test/CodeGen/PowerPC/negctr.ll
+++ b/llvm/test/CodeGen/PowerPC/negctr.ll
@@ -35,10 +35,14 @@ for.body: ; preds = %for.body, %entry
%exitcond = icmp eq i64 %indvars.iv.next, 0
br i1 %exitcond, label %for.end, label %for.body
+; FIXME: This should be a hardware loop.
+; cmp is optimized to uadd intrinsic in CGP pass which can not be recognized in
+; later HardwareLoops Pass.
; CHECK: @main1
-; CHECK: li [[REG:[0-9]+]], -1
-; CHECK: mtctr [[REG]]
-; CHECK: bdnz
+; CHECK: li [[REG:[0-9]+]], 1
+; CHECK: addi [[REG2:[0-9]+]], [[REG]], 1
+; CHECK: cmpld
+; CHECK: bge
for.end: ; preds = %for.body, %entry
ret void
diff --git a/llvm/test/CodeGen/PowerPC/stwu-sched.ll b/llvm/test/CodeGen/PowerPC/stwu-sched.ll
index 1c5cf0b1739..f88869b1923 100644
--- a/llvm/test/CodeGen/PowerPC/stwu-sched.ll
+++ b/llvm/test/CodeGen/PowerPC/stwu-sched.ll
@@ -1,9 +1,9 @@
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu < %s -verify-machineinstrs | FileCheck %s
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s -verify-machineinstrs | FileCheck %s
-; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu < %s -verify-machineinstrs | FileCheck %s \
-; RUN: --check-prefix=CHECK-ITIN
-; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s -verify-machineinstrs | FileCheck %s \
-; RUN: --check-prefix=CHECK-ITIN
+; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -disable-ppc-ctrloops < %s -verify-machineinstrs \
+; RUN: | FileCheck %s --check-prefix=CHECK-ITIN
+; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu -disable-ppc-ctrloops < %s -verify-machineinstrs \
+; RUN: | FileCheck %s --check-prefix=CHECK-ITIN
%0 = type { i32, i32 }
@@ -12,11 +12,11 @@
define void @initCombList(%0* nocapture, i32 signext) local_unnamed_addr #0 {
; CHECK-LABEL: initCombList:
; CHECK: addi 4, 4, -8
-; CHECK: stwu 5, 64(3)
+; CHECK: stwu [[REG:[0-9]+]], 64(3)
; CHECK-ITIN-LABEL: initCombList:
-; CHECK-ITIN: stwu 5, 64(4)
-; CHECK-ITIN-NEXT: addi 3, 3, -8
+; CHECK-ITIN: stwu [[REG:[0-9]+]], 64(3)
+; CHECK-ITIN-NEXT: addi [[REG2:[0-9]+]], [[REG2]], 8
%3 = zext i32 %1 to i64
diff --git a/llvm/test/CodeGen/PowerPC/unal-altivec.ll b/llvm/test/CodeGen/PowerPC/unal-altivec.ll
index a804b35052b..081d582b741 100644
--- a/llvm/test/CodeGen/PowerPC/unal-altivec.ll
+++ b/llvm/test/CodeGen/PowerPC/unal-altivec.ll
@@ -29,15 +29,14 @@ vector.body: ; preds = %vector.body, %vecto
br i1 %10, label %for.end, label %vector.body
; CHECK: @foo
-; CHECK-DAG: li [[C0:[0-9]+]], 0
+; CHECK-DAG: li [[C16:[0-9]+]], 16
; CHECK-DAG: lvx [[CNST:[0-9]+]],
; CHECK: .LBB0_1:
-; CHECK-DAG: lvsl [[MASK1:[0-9]+]], [[B1:[0-9]+]], [[C0]]
-; CHECK-DAG: add [[B3:[0-9]+]], [[B1]], [[C0]]
-; CHECK-DAG: lvx [[LD1:[0-9]+]], [[B1]], [[C0]]
-; CHECK-DAG: lvx [[LD2:[0-9]+]], [[B3]],
-; CHECK-DAG: vperm [[R1:[0-9]+]], [[LD1]], [[LD2]], [[MASK1]]
-; CHECK-DAG: vaddfp {{[0-9]+}}, [[R1]], [[CNST]]
+; CHECK-DAG: lvx [[LD1:[0-9]+]], 0, [[C0:[0-9]+]]
+; CHECK-DAG: lvx [[LD2:[0-9]+]], [[C0]], [[C16]]
+; CHECK-DAG: lvsl [[MASK1:[0-9]+]], 0, [[C0]]
+; CHECK-DAG: vperm [[VR1:[0-9]+]], [[LD1]], [[LD2]], [[MASK1]]
+; CHECK-DAG: vaddfp {{[0-9]+}}, [[VR1]], [[CNST]]
; CHECK: blr
for.end: ; preds = %vector.body
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