diff options
Diffstat (limited to 'llvm/test/CodeGen/PowerPC')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/atomics-regression.ll | 312 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/block-placement-1.mir | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/cmp_elimination.ll | 11 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/licm-remat.ll | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/machine-pre.ll | 36 |
5 files changed, 173 insertions, 197 deletions
diff --git a/llvm/test/CodeGen/PowerPC/atomics-regression.ll b/llvm/test/CodeGen/PowerPC/atomics-regression.ll index 448f254aa88..7cfa4d2f6f0 100644 --- a/llvm/test/CodeGen/PowerPC/atomics-regression.ll +++ b/llvm/test/CodeGen/PowerPC/atomics-regression.ll @@ -401,16 +401,15 @@ define void @test40(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test40: ; PPC64LE: # %bb.0: ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 -; PPC64LE-NEXT: b .LBB40_2 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB40_1: -; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: .LBB40_2: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 -; PPC64LE-NEXT: beq 0, .LBB40_1 -; PPC64LE-NEXT: # %bb.3: +; PPC64LE-NEXT: bne 0, .LBB40_3 +; PPC64LE-NEXT: # %bb.2: +; PPC64LE-NEXT: stbcx. 5, 0, 3 +; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: b .LBB40_1 +; PPC64LE-NEXT: .LBB40_3: ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val monotonic monotonic @@ -466,16 +465,15 @@ define void @test43(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE: # %bb.0: ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: lwsync -; PPC64LE-NEXT: b .LBB43_2 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB43_1: -; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: .LBB43_2: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 -; PPC64LE-NEXT: beq 0, .LBB43_1 -; PPC64LE-NEXT: # %bb.3: +; PPC64LE-NEXT: bne 0, .LBB43_3 +; PPC64LE-NEXT: # %bb.2: +; PPC64LE-NEXT: stbcx. 5, 0, 3 +; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: b .LBB43_1 +; PPC64LE-NEXT: .LBB43_3: ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release monotonic @@ -487,16 +485,15 @@ define void @test44(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE: # %bb.0: ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: lwsync -; PPC64LE-NEXT: b .LBB44_2 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB44_1: -; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: .LBB44_2: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 -; PPC64LE-NEXT: beq 0, .LBB44_1 -; PPC64LE-NEXT: # %bb.3: +; PPC64LE-NEXT: bne 0, .LBB44_3 +; PPC64LE-NEXT: # %bb.2: +; PPC64LE-NEXT: stbcx. 5, 0, 3 +; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: b .LBB44_1 +; PPC64LE-NEXT: .LBB44_3: ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release acquire @@ -622,16 +619,15 @@ define void @test50(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test50: ; PPC64LE: # %bb.0: ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 -; PPC64LE-NEXT: b .LBB50_2 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB50_1: -; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: .LBB50_2: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 -; PPC64LE-NEXT: beq 0, .LBB50_1 -; PPC64LE-NEXT: # %bb.3: +; PPC64LE-NEXT: bne 0, .LBB50_3 +; PPC64LE-NEXT: # %bb.2: +; PPC64LE-NEXT: sthcx. 5, 0, 3 +; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: b .LBB50_1 +; PPC64LE-NEXT: .LBB50_3: ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val monotonic monotonic @@ -687,16 +683,15 @@ define void @test53(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE: # %bb.0: ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: lwsync -; PPC64LE-NEXT: b .LBB53_2 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB53_1: -; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: .LBB53_2: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 -; PPC64LE-NEXT: beq 0, .LBB53_1 -; PPC64LE-NEXT: # %bb.3: +; PPC64LE-NEXT: bne 0, .LBB53_3 +; PPC64LE-NEXT: # %bb.2: +; PPC64LE-NEXT: sthcx. 5, 0, 3 +; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: b .LBB53_1 +; PPC64LE-NEXT: .LBB53_3: ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release monotonic @@ -708,16 +703,15 @@ define void @test54(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE: # %bb.0: ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: lwsync -; PPC64LE-NEXT: b .LBB54_2 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB54_1: -; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: .LBB54_2: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 -; PPC64LE-NEXT: beq 0, .LBB54_1 -; PPC64LE-NEXT: # %bb.3: +; PPC64LE-NEXT: bne 0, .LBB54_3 +; PPC64LE-NEXT: # %bb.2: +; PPC64LE-NEXT: sthcx. 5, 0, 3 +; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: b .LBB54_1 +; PPC64LE-NEXT: .LBB54_3: ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release acquire @@ -842,16 +836,15 @@ define void @test59(i16* %ptr, i16 %cmp, i16 %val) { define void @test60(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test60: ; PPC64LE: # %bb.0: -; PPC64LE-NEXT: b .LBB60_2 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB60_1: -; PPC64LE-NEXT: stwcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: .LBB60_2: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 -; PPC64LE-NEXT: beq 0, .LBB60_1 -; PPC64LE-NEXT: # %bb.3: +; PPC64LE-NEXT: bne 0, .LBB60_3 +; PPC64LE-NEXT: # %bb.2: +; PPC64LE-NEXT: stwcx. 5, 0, 3 +; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: b .LBB60_1 +; PPC64LE-NEXT: .LBB60_3: ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val monotonic monotonic @@ -904,16 +897,15 @@ define void @test63(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test63: ; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync -; PPC64LE-NEXT: b .LBB63_2 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB63_1: -; PPC64LE-NEXT: stwcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: .LBB63_2: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 -; PPC64LE-NEXT: beq 0, .LBB63_1 -; PPC64LE-NEXT: # %bb.3: +; PPC64LE-NEXT: bne 0, .LBB63_3 +; PPC64LE-NEXT: # %bb.2: +; PPC64LE-NEXT: stwcx. 5, 0, 3 +; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: b .LBB63_1 +; PPC64LE-NEXT: .LBB63_3: ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release monotonic @@ -924,16 +916,15 @@ define void @test64(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test64: ; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync -; PPC64LE-NEXT: b .LBB64_2 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB64_1: -; PPC64LE-NEXT: stwcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: .LBB64_2: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 -; PPC64LE-NEXT: beq 0, .LBB64_1 -; PPC64LE-NEXT: # %bb.3: +; PPC64LE-NEXT: bne 0, .LBB64_3 +; PPC64LE-NEXT: # %bb.2: +; PPC64LE-NEXT: stwcx. 5, 0, 3 +; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: b .LBB64_1 +; PPC64LE-NEXT: .LBB64_3: ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release acquire @@ -1053,16 +1044,15 @@ define void @test69(i32* %ptr, i32 %cmp, i32 %val) { define void @test70(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test70: ; PPC64LE: # %bb.0: -; PPC64LE-NEXT: b .LBB70_2 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB70_1: -; PPC64LE-NEXT: stdcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: .LBB70_2: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 -; PPC64LE-NEXT: beq 0, .LBB70_1 -; PPC64LE-NEXT: # %bb.3: +; PPC64LE-NEXT: bne 0, .LBB70_3 +; PPC64LE-NEXT: # %bb.2: +; PPC64LE-NEXT: stdcx. 5, 0, 3 +; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: b .LBB70_1 +; PPC64LE-NEXT: .LBB70_3: ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val monotonic monotonic @@ -1115,16 +1105,15 @@ define void @test73(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test73: ; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync -; PPC64LE-NEXT: b .LBB73_2 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB73_1: -; PPC64LE-NEXT: stdcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: .LBB73_2: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 -; PPC64LE-NEXT: beq 0, .LBB73_1 -; PPC64LE-NEXT: # %bb.3: +; PPC64LE-NEXT: bne 0, .LBB73_3 +; PPC64LE-NEXT: # %bb.2: +; PPC64LE-NEXT: stdcx. 5, 0, 3 +; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: b .LBB73_1 +; PPC64LE-NEXT: .LBB73_3: ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release monotonic @@ -1135,16 +1124,15 @@ define void @test74(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test74: ; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync -; PPC64LE-NEXT: b .LBB74_2 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB74_1: -; PPC64LE-NEXT: stdcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: .LBB74_2: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 -; PPC64LE-NEXT: beq 0, .LBB74_1 -; PPC64LE-NEXT: # %bb.3: +; PPC64LE-NEXT: bne 0, .LBB74_3 +; PPC64LE-NEXT: # %bb.2: +; PPC64LE-NEXT: stdcx. 5, 0, 3 +; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: b .LBB74_1 +; PPC64LE-NEXT: .LBB74_3: ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release acquire @@ -1265,16 +1253,15 @@ define void @test80(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test80: ; PPC64LE: # %bb.0: ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 -; PPC64LE-NEXT: b .LBB80_2 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB80_1: -; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: .LBB80_2: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 -; PPC64LE-NEXT: beq 0, .LBB80_1 -; PPC64LE-NEXT: # %bb.3: +; PPC64LE-NEXT: bne 0, .LBB80_3 +; PPC64LE-NEXT: # %bb.2: +; PPC64LE-NEXT: stbcx. 5, 0, 3 +; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: b .LBB80_1 +; PPC64LE-NEXT: .LBB80_3: ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") monotonic monotonic @@ -1330,16 +1317,15 @@ define void @test83(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE: # %bb.0: ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: lwsync -; PPC64LE-NEXT: b .LBB83_2 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB83_1: -; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: .LBB83_2: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 -; PPC64LE-NEXT: beq 0, .LBB83_1 -; PPC64LE-NEXT: # %bb.3: +; PPC64LE-NEXT: bne 0, .LBB83_3 +; PPC64LE-NEXT: # %bb.2: +; PPC64LE-NEXT: stbcx. 5, 0, 3 +; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: b .LBB83_1 +; PPC64LE-NEXT: .LBB83_3: ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") release monotonic @@ -1351,16 +1337,15 @@ define void @test84(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE: # %bb.0: ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: lwsync -; PPC64LE-NEXT: b .LBB84_2 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB84_1: -; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: .LBB84_2: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 -; PPC64LE-NEXT: beq 0, .LBB84_1 -; PPC64LE-NEXT: # %bb.3: +; PPC64LE-NEXT: bne 0, .LBB84_3 +; PPC64LE-NEXT: # %bb.2: +; PPC64LE-NEXT: stbcx. 5, 0, 3 +; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: b .LBB84_1 +; PPC64LE-NEXT: .LBB84_3: ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") release acquire @@ -1486,16 +1471,15 @@ define void @test90(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test90: ; PPC64LE: # %bb.0: ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 -; PPC64LE-NEXT: b .LBB90_2 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB90_1: -; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: .LBB90_2: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 -; PPC64LE-NEXT: beq 0, .LBB90_1 -; PPC64LE-NEXT: # %bb.3: +; PPC64LE-NEXT: bne 0, .LBB90_3 +; PPC64LE-NEXT: # %bb.2: +; PPC64LE-NEXT: sthcx. 5, 0, 3 +; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: b +; PPC64LE-NEXT: .LBB90_3: ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") monotonic monotonic @@ -1551,16 +1535,15 @@ define void @test93(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE: # %bb.0: ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: lwsync -; PPC64LE-NEXT: b .LBB93_2 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB93_1: -; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: .LBB93_2: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 -; PPC64LE-NEXT: beq 0, .LBB93_1 -; PPC64LE-NEXT: # %bb.3: +; PPC64LE-NEXT: bne 0, .LBB93_3 +; PPC64LE-NEXT: # %bb.2: +; PPC64LE-NEXT: sthcx. 5, 0, 3 +; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: b .LBB93_1 +; PPC64LE-NEXT: .LBB93_3: ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") release monotonic @@ -1572,16 +1555,15 @@ define void @test94(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE: # %bb.0: ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: lwsync -; PPC64LE-NEXT: b .LBB94_2 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB94_1: -; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: .LBB94_2: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 -; PPC64LE-NEXT: beq 0, .LBB94_1 -; PPC64LE-NEXT: # %bb.3: +; PPC64LE-NEXT: bne 0, .LBB94_3 +; PPC64LE-NEXT: # %bb.2: +; PPC64LE-NEXT: sthcx. 5, 0, 3 +; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: b .LBB94_1 +; PPC64LE-NEXT: .LBB94_3: ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") release acquire @@ -1706,16 +1688,15 @@ define void @test99(i16* %ptr, i16 %cmp, i16 %val) { define void @test100(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test100: ; PPC64LE: # %bb.0: -; PPC64LE-NEXT: b .LBB100_2 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB100_1: -; PPC64LE-NEXT: stwcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: .LBB100_2: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 -; PPC64LE-NEXT: beq 0, .LBB100_1 -; PPC64LE-NEXT: # %bb.3: +; PPC64LE-NEXT: bne 0, .LBB100_3 +; PPC64LE-NEXT: # %bb.2: +; PPC64LE-NEXT: stwcx. 5, 0, 3 +; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: b .LBB100_1 +; PPC64LE-NEXT: .LBB100_3: ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") monotonic monotonic @@ -1768,16 +1749,15 @@ define void @test103(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test103: ; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync -; PPC64LE-NEXT: b .LBB103_2 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB103_1: -; PPC64LE-NEXT: stwcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: .LBB103_2: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 -; PPC64LE-NEXT: beq 0, .LBB103_1 -; PPC64LE-NEXT: # %bb.3: +; PPC64LE-NEXT: bne 0, .LBB103_3 +; PPC64LE-NEXT: # %bb.2: +; PPC64LE-NEXT: stwcx. 5, 0, 3 +; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: b .LBB103_1 +; PPC64LE-NEXT: .LBB103_3: ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") release monotonic @@ -1788,16 +1768,15 @@ define void @test104(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test104: ; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync -; PPC64LE-NEXT: b .LBB104_2 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB104_1: -; PPC64LE-NEXT: stwcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: .LBB104_2: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 -; PPC64LE-NEXT: beq 0, .LBB104_1 -; PPC64LE-NEXT: # %bb.3: +; PPC64LE-NEXT: bne 0, .LBB104_3 +; PPC64LE-NEXT: # %bb.2: +; PPC64LE-NEXT: stwcx. 5, 0, 3 +; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: b .LBB104_1 +; PPC64LE-NEXT: .LBB104_3: ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") release acquire @@ -1917,16 +1896,15 @@ define void @test109(i32* %ptr, i32 %cmp, i32 %val) { define void @test110(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test110: ; PPC64LE: # %bb.0: -; PPC64LE-NEXT: b .LBB110_2 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB110_1: -; PPC64LE-NEXT: stdcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: .LBB110_2: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 -; PPC64LE-NEXT: beq 0, .LBB110_1 -; PPC64LE-NEXT: # %bb.3: +; PPC64LE-NEXT: bne 0, .LBB110_3 +; PPC64LE-NEXT: # %bb.2: +; PPC64LE-NEXT: stdcx. 5, 0, 3 +; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: b .LBB110_1 +; PPC64LE-NEXT: .LBB110_3: ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") monotonic monotonic @@ -1979,16 +1957,15 @@ define void @test113(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test113: ; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync -; PPC64LE-NEXT: b .LBB113_2 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB113_1: -; PPC64LE-NEXT: stdcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: .LBB113_2: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 -; PPC64LE-NEXT: beq 0, .LBB113_1 -; PPC64LE-NEXT: # %bb.3: +; PPC64LE-NEXT: bne 0, .LBB113_3 +; PPC64LE-NEXT: # %bb.2: +; PPC64LE-NEXT: stdcx. 5, 0, 3 +; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: b .LBB113_1 +; PPC64LE-NEXT: .LBB113_3: ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") release monotonic @@ -1999,16 +1976,15 @@ define void @test114(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test114: ; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync -; PPC64LE-NEXT: b .LBB114_2 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB114_1: -; PPC64LE-NEXT: stdcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: .LBB114_2: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 -; PPC64LE-NEXT: beq 0, .LBB114_1 -; PPC64LE-NEXT: # %bb.3: +; PPC64LE-NEXT: bne 0, .LBB114_3 +; PPC64LE-NEXT: # %bb.2: +; PPC64LE-NEXT: stdcx. 5, 0, 3 +; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: b .LBB114_1 +; PPC64LE-NEXT: .LBB114_3: ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") release acquire diff --git a/llvm/test/CodeGen/PowerPC/block-placement-1.mir b/llvm/test/CodeGen/PowerPC/block-placement-1.mir index e756ba3aa46..01967e46da9 100644 --- a/llvm/test/CodeGen/PowerPC/block-placement-1.mir +++ b/llvm/test/CodeGen/PowerPC/block-placement-1.mir @@ -298,14 +298,14 @@ body: | bb.11.unreachable: + ; CHECK: bb.1.for.body: + ; CHECK: successors: %bb.2(0x7ffff800), %bb.3(0x00000800) + ; CHECK: B %bb.2 + ; CHECK: bb.4.catch4: ; CHECK: successors: %bb.11(0x7ffff800), %bb.6(0x00000800) ; CHECK: B %bb.11 - ; CHECK: bb.1.for.body (align 4): - ; CHECK: successors: %bb.2(0x7ffff800), %bb.3(0x00000800) - ; CHECK: B %bb.2 - ; CHECK: bb.2..noexc: ; CHECK: bb.11.unreachable: diff --git a/llvm/test/CodeGen/PowerPC/cmp_elimination.ll b/llvm/test/CodeGen/PowerPC/cmp_elimination.ll index 6bc8b8a041c..95fcb1796c8 100644 --- a/llvm/test/CodeGen/PowerPC/cmp_elimination.ll +++ b/llvm/test/CodeGen/PowerPC/cmp_elimination.ll @@ -718,13 +718,14 @@ if.end: define void @func28(i32 signext %a) { ; CHECK-LABEL: @func28 ; CHECK: cmplwi [[REG1:[0-9]+]], [[REG2:[0-9]+]] -; CHECK: .[[LABEL1:[A-Z0-9_]+]]: +; CHECK: .[[LABEL2:[A-Z0-9_]+]]: +; CHECK: cmpwi [[REG1]], [[REG2]] +; CHECK: ble 0, .[[LABEL1:[A-Z0-9_]+]] ; CHECK-NOT: cmp -; CHECK: bne 0, .[[LABEL2:[A-Z0-9_]+]] +; CHECK: bne 0, .[[LABEL2]] ; CHECK: bl dummy1 -; CHECK: .[[LABEL2]]: -; CHECK: cmpwi [[REG1]], [[REG2]] -; CHECK: bgt 0, .[[LABEL1]] +; CHECK: b .[[LABEL2]] +; CHECK: .[[LABEL1]]: ; CHECK: blr entry: br label %do.body diff --git a/llvm/test/CodeGen/PowerPC/licm-remat.ll b/llvm/test/CodeGen/PowerPC/licm-remat.ll index 045f7a4c07c..9fab26b6222 100644 --- a/llvm/test/CodeGen/PowerPC/licm-remat.ll +++ b/llvm/test/CodeGen/PowerPC/licm-remat.ll @@ -24,8 +24,7 @@ define linkonce_odr void @ZN6snappyDecompressor_(%"class.snappy::SnappyDecompres ; CHECK-DAG: addi 25, 3, _ZN6snappy8internalL8wordmaskE@toc@l ; CHECK-DAG: addis 5, 2, _ZN6snappy8internalL10char_tableE@toc@ha ; CHECK-DAG: addi 24, 5, _ZN6snappy8internalL10char_tableE@toc@l -; CHECK: b .[[LABEL1:[A-Z0-9_]+]] -; CHECK: .[[LABEL1]]: # %for.cond +; CHECK: .LBB0_2: # %for.cond ; CHECK-NOT: addis {{[0-9]+}}, 2, _ZN6snappy8internalL8wordmaskE@toc@ha ; CHECK-NOT: addis {{[0-9]+}}, 2, _ZN6snappy8internalL10char_tableE@toc@ha ; CHECK: bctrl diff --git a/llvm/test/CodeGen/PowerPC/machine-pre.ll b/llvm/test/CodeGen/PowerPC/machine-pre.ll index 2d7a5619c63..596c0a4624c 100644 --- a/llvm/test/CodeGen/PowerPC/machine-pre.ll +++ b/llvm/test/CodeGen/PowerPC/machine-pre.ll @@ -75,8 +75,19 @@ define dso_local signext i32 @foo(i32 signext %x, i32 signext %y) local_unnamed_ ; CHECK-P9-NEXT: lis r3, 21845 ; CHECK-P9-NEXT: add r28, r30, r29 ; CHECK-P9-NEXT: ori r27, r3, 21846 +; CHECK-P9-NEXT: b .LBB1_4 ; CHECK-P9-NEXT: .p2align 4 -; CHECK-P9-NEXT: .LBB1_1: # %while.cond +; CHECK-P9-NEXT: .LBB1_1: # %sw.bb3 +; CHECK-P9-NEXT: # +; CHECK-P9-NEXT: mulli r3, r30, 23 +; CHECK-P9-NEXT: .LBB1_2: # %sw.epilog +; CHECK-P9-NEXT: # +; CHECK-P9-NEXT: add r28, r3, r28 +; CHECK-P9-NEXT: .LBB1_3: # %sw.epilog +; CHECK-P9-NEXT: # +; CHECK-P9-NEXT: cmpwi r28, 1025 +; CHECK-P9-NEXT: bge cr0, .LBB1_7 +; CHECK-P9-NEXT: .LBB1_4: # %while.cond ; CHECK-P9-NEXT: # ; CHECK-P9-NEXT: extsw r3, r29 ; CHECK-P9-NEXT: bl bar @@ -95,27 +106,16 @@ define dso_local signext i32 @foo(i32 signext %x, i32 signext %y) local_unnamed_ ; CHECK-P9-NEXT: add r4, r4, r5 ; CHECK-P9-NEXT: subf r3, r4, r3 ; CHECK-P9-NEXT: cmplwi r3, 1 -; CHECK-P9-NEXT: beq cr0, .LBB1_4 -; CHECK-P9-NEXT: # %bb.2: # %while.cond +; CHECK-P9-NEXT: beq cr0, .LBB1_1 +; CHECK-P9-NEXT: # %bb.5: # %while.cond ; CHECK-P9-NEXT: # ; CHECK-P9-NEXT: cmplwi r3, 0 -; CHECK-P9-NEXT: bne cr0, .LBB1_6 -; CHECK-P9-NEXT: # %bb.3: # %sw.bb +; CHECK-P9-NEXT: bne cr0, .LBB1_3 +; CHECK-P9-NEXT: # %bb.6: # %sw.bb ; CHECK-P9-NEXT: # ; CHECK-P9-NEXT: mulli r3, r29, 13 -; CHECK-P9-NEXT: b .LBB1_5 -; CHECK-P9-NEXT: .p2align 4 -; CHECK-P9-NEXT: .LBB1_4: # %sw.bb3 -; CHECK-P9-NEXT: # -; CHECK-P9-NEXT: mulli r3, r30, 23 -; CHECK-P9-NEXT: .LBB1_5: # %sw.epilog -; CHECK-P9-NEXT: # -; CHECK-P9-NEXT: add r28, r3, r28 -; CHECK-P9-NEXT: .LBB1_6: # %sw.epilog -; CHECK-P9-NEXT: # -; CHECK-P9-NEXT: cmpwi r28, 1025 -; CHECK-P9-NEXT: blt cr0, .LBB1_1 -; CHECK-P9-NEXT: # %bb.7: # %while.end +; CHECK-P9-NEXT: b .LBB1_2 +; CHECK-P9-NEXT: .LBB1_7: # %while.end ; CHECK-P9-NEXT: lis r3, -13108 ; CHECK-P9-NEXT: ori r3, r3, 52429 ; CHECK-P9-NEXT: mullw r3, r28, r3 |
