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-rw-r--r--llvm/test/CodeGen/PowerPC/build-vector-tests.ll62
-rw-r--r--llvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll153
-rw-r--r--llvm/test/CodeGen/PowerPC/vsx_shuffle_le.ll6
3 files changed, 168 insertions, 53 deletions
diff --git a/llvm/test/CodeGen/PowerPC/build-vector-tests.ll b/llvm/test/CodeGen/PowerPC/build-vector-tests.ll
index a67fdf3e8f6..adbd7622a80 100644
--- a/llvm/test/CodeGen/PowerPC/build-vector-tests.ll
+++ b/llvm/test/CodeGen/PowerPC/build-vector-tests.ll
@@ -986,7 +986,11 @@ define <4 x i32> @fromDiffMemConsDi(i32* nocapture readonly %arr) {
;
; P9LE-LABEL: fromDiffMemConsDi:
; P9LE: # %bb.0: # %entry
-; P9LE-NEXT: lxvw4x v2, 0, r3
+; P9LE-NEXT: lxv v2, 0(r3)
+; P9LE-NEXT: addis r3, r2, .LCPI8_0@toc@ha
+; P9LE-NEXT: addi r3, r3, .LCPI8_0@toc@l
+; P9LE-NEXT: lxvx v3, 0, r3
+; P9LE-NEXT: vperm v2, v2, v2, v3
; P9LE-NEXT: blr
;
; P8BE-LABEL: fromDiffMemConsDi:
@@ -1000,7 +1004,12 @@ define <4 x i32> @fromDiffMemConsDi(i32* nocapture readonly %arr) {
;
; P8LE-LABEL: fromDiffMemConsDi:
; P8LE: # %bb.0: # %entry
-; P8LE-NEXT: lxvw4x v2, 0, r3
+; P8LE-NEXT: lxvd2x vs0, 0, r3
+; P8LE-NEXT: addis r4, r2, .LCPI8_0@toc@ha
+; P8LE-NEXT: addi r3, r4, .LCPI8_0@toc@l
+; P8LE-NEXT: lvx v2, 0, r3
+; P8LE-NEXT: xxswapd v3, vs0
+; P8LE-NEXT: vperm v2, v3, v3, v2
; P8LE-NEXT: blr
entry:
%arrayidx = getelementptr inbounds i32, i32* %arr, i64 3
@@ -2561,7 +2570,11 @@ define <4 x i32> @fromDiffMemConsDui(i32* nocapture readonly %arr) {
;
; P9LE-LABEL: fromDiffMemConsDui:
; P9LE: # %bb.0: # %entry
-; P9LE-NEXT: lxvw4x v2, 0, r3
+; P9LE-NEXT: lxv v2, 0(r3)
+; P9LE-NEXT: addis r3, r2, .LCPI41_0@toc@ha
+; P9LE-NEXT: addi r3, r3, .LCPI41_0@toc@l
+; P9LE-NEXT: lxvx v3, 0, r3
+; P9LE-NEXT: vperm v2, v2, v2, v3
; P9LE-NEXT: blr
;
; P8BE-LABEL: fromDiffMemConsDui:
@@ -2575,7 +2588,12 @@ define <4 x i32> @fromDiffMemConsDui(i32* nocapture readonly %arr) {
;
; P8LE-LABEL: fromDiffMemConsDui:
; P8LE: # %bb.0: # %entry
-; P8LE-NEXT: lxvw4x v2, 0, r3
+; P8LE-NEXT: lxvd2x vs0, 0, r3
+; P8LE-NEXT: addis r4, r2, .LCPI41_0@toc@ha
+; P8LE-NEXT: addi r3, r4, .LCPI41_0@toc@l
+; P8LE-NEXT: lvx v2, 0, r3
+; P8LE-NEXT: xxswapd v3, vs0
+; P8LE-NEXT: vperm v2, v3, v3, v2
; P8LE-NEXT: blr
entry:
%arrayidx = getelementptr inbounds i32, i32* %arr, i64 3
@@ -4137,8 +4155,8 @@ define <2 x i64> @fromDiffMemConsDll(i64* nocapture readonly %arr) {
;
; P9LE-LABEL: fromDiffMemConsDll:
; P9LE: # %bb.0: # %entry
-; P9LE-NEXT: addi r3, r3, 16
-; P9LE-NEXT: lxvd2x v2, 0, r3
+; P9LE-NEXT: lxv v2, 16(r3)
+; P9LE-NEXT: xxswapd v2, v2
; P9LE-NEXT: blr
;
; P8BE-LABEL: fromDiffMemConsDll:
@@ -4217,8 +4235,9 @@ define <2 x i64> @fromDiffMemVarDll(i64* nocapture readonly %arr, i32 signext %e
; P9LE: # %bb.0: # %entry
; P9LE-NEXT: sldi r4, r4, 3
; P9LE-NEXT: add r3, r3, r4
-; P9LE-NEXT: addi r3, r3, -8
-; P9LE-NEXT: lxvd2x v2, 0, r3
+; P9LE-NEXT: li r4, -8
+; P9LE-NEXT: lxvx v2, r3, r4
+; P9LE-NEXT: xxswapd v2, v2
; P9LE-NEXT: blr
;
; P8BE-LABEL: fromDiffMemVarDll:
@@ -4929,8 +4948,8 @@ define <2 x i64> @fromDiffMemConsDConvdtoll(double* nocapture readonly %ptr) {
;
; P9LE-LABEL: fromDiffMemConsDConvdtoll:
; P9LE: # %bb.0: # %entry
-; P9LE-NEXT: addi r3, r3, 16
-; P9LE-NEXT: lxvd2x vs0, 0, r3
+; P9LE-NEXT: lxv vs0, 16(r3)
+; P9LE-NEXT: xxswapd vs0, vs0
; P9LE-NEXT: xvcvdpsxds v2, vs0
; P9LE-NEXT: blr
;
@@ -5021,8 +5040,9 @@ define <2 x i64> @fromDiffMemVarDConvdtoll(double* nocapture readonly %arr, i32
; P9LE: # %bb.0: # %entry
; P9LE-NEXT: sldi r4, r4, 3
; P9LE-NEXT: add r3, r3, r4
-; P9LE-NEXT: addi r3, r3, -8
-; P9LE-NEXT: lxvd2x vs0, 0, r3
+; P9LE-NEXT: li r4, -8
+; P9LE-NEXT: lxvx vs0, r3, r4
+; P9LE-NEXT: xxswapd vs0, vs0
; P9LE-NEXT: xvcvdpsxds v2, vs0
; P9LE-NEXT: blr
;
@@ -5382,8 +5402,8 @@ define <2 x i64> @fromDiffMemConsDull(i64* nocapture readonly %arr) {
;
; P9LE-LABEL: fromDiffMemConsDull:
; P9LE: # %bb.0: # %entry
-; P9LE-NEXT: addi r3, r3, 16
-; P9LE-NEXT: lxvd2x v2, 0, r3
+; P9LE-NEXT: lxv v2, 16(r3)
+; P9LE-NEXT: xxswapd v2, v2
; P9LE-NEXT: blr
;
; P8BE-LABEL: fromDiffMemConsDull:
@@ -5462,8 +5482,9 @@ define <2 x i64> @fromDiffMemVarDull(i64* nocapture readonly %arr, i32 signext %
; P9LE: # %bb.0: # %entry
; P9LE-NEXT: sldi r4, r4, 3
; P9LE-NEXT: add r3, r3, r4
-; P9LE-NEXT: addi r3, r3, -8
-; P9LE-NEXT: lxvd2x v2, 0, r3
+; P9LE-NEXT: li r4, -8
+; P9LE-NEXT: lxvx v2, r3, r4
+; P9LE-NEXT: xxswapd v2, v2
; P9LE-NEXT: blr
;
; P8BE-LABEL: fromDiffMemVarDull:
@@ -6174,8 +6195,8 @@ define <2 x i64> @fromDiffMemConsDConvdtoull(double* nocapture readonly %ptr) {
;
; P9LE-LABEL: fromDiffMemConsDConvdtoull:
; P9LE: # %bb.0: # %entry
-; P9LE-NEXT: addi r3, r3, 16
-; P9LE-NEXT: lxvd2x vs0, 0, r3
+; P9LE-NEXT: lxv vs0, 16(r3)
+; P9LE-NEXT: xxswapd vs0, vs0
; P9LE-NEXT: xvcvdpuxds v2, vs0
; P9LE-NEXT: blr
;
@@ -6266,8 +6287,9 @@ define <2 x i64> @fromDiffMemVarDConvdtoull(double* nocapture readonly %arr, i32
; P9LE: # %bb.0: # %entry
; P9LE-NEXT: sldi r4, r4, 3
; P9LE-NEXT: add r3, r3, r4
-; P9LE-NEXT: addi r3, r3, -8
-; P9LE-NEXT: lxvd2x vs0, 0, r3
+; P9LE-NEXT: li r4, -8
+; P9LE-NEXT: lxvx vs0, r3, r4
+; P9LE-NEXT: xxswapd vs0, vs0
; P9LE-NEXT: xvcvdpuxds v2, vs0
; P9LE-NEXT: blr
;
diff --git a/llvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll b/llvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll
index dc2ead88f12..ebbce70409c 100644
--- a/llvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll
+++ b/llvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll
@@ -19,7 +19,8 @@ define <2 x i64> @load_swap00(<2 x i64>* %vp1, <2 x i64>* %vp2) {
;
; CHECK-P9-LABEL: load_swap00:
; CHECK-P9: # %bb.0:
-; CHECK-P9-NEXT: lxvd2x v2, 0, r3
+; CHECK-P9-NEXT: lxv v2, 0(r3)
+; CHECK-P9-NEXT: xxswapd v2, v2
; CHECK-P9-NEXT: blr
;
; CHECK-P8-BE-LABEL: load_swap00:
@@ -47,7 +48,8 @@ define <2 x i64> @load_swap01(<2 x i64>* %vp1, <2 x i64>* %vp2) {
;
; CHECK-P9-LABEL: load_swap01:
; CHECK-P9: # %bb.0:
-; CHECK-P9-NEXT: lxvd2x v2, 0, r4
+; CHECK-P9-NEXT: lxv v2, 0(r4)
+; CHECK-P9-NEXT: xxswapd v2, v2
; CHECK-P9-NEXT: blr
;
; CHECK-P8-BE-LABEL: load_swap01:
@@ -70,12 +72,20 @@ define <2 x i64> @load_swap01(<2 x i64>* %vp1, <2 x i64>* %vp2) {
define <4 x i32> @load_swap10(<4 x i32>* %vp1, <4 x i32>* %vp2) {
; CHECK-P8-LABEL: load_swap10:
; CHECK-P8: # %bb.0:
-; CHECK-P8-NEXT: lxvw4x v2, 0, r3
+; CHECK-P8-NEXT: addis r4, r2, .LCPI2_0@toc@ha
+; CHECK-P8-NEXT: lvx v3, 0, r3
+; CHECK-P8-NEXT: addi r4, r4, .LCPI2_0@toc@l
+; CHECK-P8-NEXT: lvx v2, 0, r4
+; CHECK-P8-NEXT: vperm v2, v3, v3, v2
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: load_swap10:
; CHECK-P9: # %bb.0:
-; CHECK-P9-NEXT: lxvw4x v2, 0, r3
+; CHECK-P9-NEXT: lxv v2, 0(r3)
+; CHECK-P9-NEXT: addis r3, r2, .LCPI2_0@toc@ha
+; CHECK-P9-NEXT: addi r3, r3, .LCPI2_0@toc@l
+; CHECK-P9-NEXT: lxvx v3, 0, r3
+; CHECK-P9-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-BE-LABEL: load_swap10:
@@ -104,12 +114,20 @@ define <4 x i32> @load_swap10(<4 x i32>* %vp1, <4 x i32>* %vp2) {
define <4 x i32> @load_swap11(<4 x i32>* %vp1, <4 x i32>* %vp2) {
; CHECK-P8-LABEL: load_swap11:
; CHECK-P8: # %bb.0:
-; CHECK-P8-NEXT: lxvw4x v2, 0, r4
+; CHECK-P8-NEXT: addis r3, r2, .LCPI3_0@toc@ha
+; CHECK-P8-NEXT: lvx v3, 0, r4
+; CHECK-P8-NEXT: addi r3, r3, .LCPI3_0@toc@l
+; CHECK-P8-NEXT: lvx v2, 0, r3
+; CHECK-P8-NEXT: vperm v2, v3, v3, v2
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: load_swap11:
; CHECK-P9: # %bb.0:
-; CHECK-P9-NEXT: lxvw4x v2, 0, r4
+; CHECK-P9-NEXT: addis r3, r2, .LCPI3_0@toc@ha
+; CHECK-P9-NEXT: addi r3, r3, .LCPI3_0@toc@l
+; CHECK-P9-NEXT: lxv v2, 0(r4)
+; CHECK-P9-NEXT: lxvx v3, 0, r3
+; CHECK-P9-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-BE-LABEL: load_swap11:
@@ -147,7 +165,11 @@ define <8 x i16> @load_swap20(<8 x i16>* %vp1, <8 x i16>* %vp2){
;
; CHECK-P9-LABEL: load_swap20:
; CHECK-P9: # %bb.0:
-; CHECK-P9-NEXT: lxvh8x v2, 0, r3
+; CHECK-P9-NEXT: lxv v2, 0(r3)
+; CHECK-P9-NEXT: addis r3, r2, .LCPI4_0@toc@ha
+; CHECK-P9-NEXT: addi r3, r3, .LCPI4_0@toc@l
+; CHECK-P9-NEXT: lxvx v3, 0, r3
+; CHECK-P9-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-BE-LABEL: load_swap20:
@@ -185,7 +207,11 @@ define <8 x i16> @load_swap21(<8 x i16>* %vp1, <8 x i16>* %vp2){
;
; CHECK-P9-LABEL: load_swap21:
; CHECK-P9: # %bb.0:
-; CHECK-P9-NEXT: lxvh8x v2, 0, r4
+; CHECK-P9-NEXT: addis r3, r2, .LCPI5_0@toc@ha
+; CHECK-P9-NEXT: addi r3, r3, .LCPI5_0@toc@l
+; CHECK-P9-NEXT: lxv v2, 0(r4)
+; CHECK-P9-NEXT: lxvx v3, 0, r3
+; CHECK-P9-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-BE-LABEL: load_swap21:
@@ -223,7 +249,8 @@ define <16 x i8> @load_swap30(<16 x i8>* %vp1, <16 x i8>* %vp2){
;
; CHECK-P9-LABEL: load_swap30:
; CHECK-P9: # %bb.0:
-; CHECK-P9-NEXT: lxvb16x v2, 0, r3
+; CHECK-P9-NEXT: lxv vs0, 0(r3)
+; CHECK-P9-NEXT: xxbrq v2, vs0
; CHECK-P9-NEXT: blr
;
; CHECK-P8-BE-LABEL: load_swap30:
@@ -258,7 +285,8 @@ define <16 x i8> @load_swap31(<16 x i8>* %vp1, <16 x i8>* %vp2){
;
; CHECK-P9-LABEL: load_swap31:
; CHECK-P9: # %bb.0:
-; CHECK-P9-NEXT: lxvb16x v2, 0, r4
+; CHECK-P9-NEXT: lxv vs0, 0(r4)
+; CHECK-P9-NEXT: xxbrq v2, vs0
; CHECK-P9-NEXT: blr
;
; CHECK-P8-BE-LABEL: load_swap31:
@@ -289,7 +317,8 @@ define <2 x double> @load_swap40(<2 x double>* %vp1, <2 x double>* %vp2) {
;
; CHECK-P9-LABEL: load_swap40:
; CHECK-P9: # %bb.0:
-; CHECK-P9-NEXT: lxvd2x v2, 0, r4
+; CHECK-P9-NEXT: lxv vs0, 0(r4)
+; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: blr
;
; CHECK-P8-BE-LABEL: load_swap40:
@@ -312,12 +341,20 @@ define <2 x double> @load_swap40(<2 x double>* %vp1, <2 x double>* %vp2) {
define <4 x float> @load_swap50(<4 x float>* %vp1, <4 x float>* %vp2) {
; CHECK-P8-LABEL: load_swap50:
; CHECK-P8: # %bb.0:
-; CHECK-P8-NEXT: lxvw4x v2, 0, r3
+; CHECK-P8-NEXT: addis r4, r2, .LCPI9_0@toc@ha
+; CHECK-P8-NEXT: lvx v3, 0, r3
+; CHECK-P8-NEXT: addi r4, r4, .LCPI9_0@toc@l
+; CHECK-P8-NEXT: lvx v2, 0, r4
+; CHECK-P8-NEXT: vperm v2, v3, v3, v2
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: load_swap50:
; CHECK-P9: # %bb.0:
-; CHECK-P9-NEXT: lxvw4x v2, 0, r3
+; CHECK-P9-NEXT: lxv v2, 0(r3)
+; CHECK-P9-NEXT: addis r3, r2, .LCPI9_0@toc@ha
+; CHECK-P9-NEXT: addi r3, r3, .LCPI9_0@toc@l
+; CHECK-P9-NEXT: lxvx v3, 0, r3
+; CHECK-P9-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-BE-LABEL: load_swap50:
@@ -346,12 +383,20 @@ define <4 x float> @load_swap50(<4 x float>* %vp1, <4 x float>* %vp2) {
define <4 x float> @load_swap51(<4 x float>* %vp1, <4 x float>* %vp2) {
; CHECK-P8-LABEL: load_swap51:
; CHECK-P8: # %bb.0:
-; CHECK-P8-NEXT: lxvw4x v2, 0, r4
+; CHECK-P8-NEXT: addis r3, r2, .LCPI10_0@toc@ha
+; CHECK-P8-NEXT: lvx v3, 0, r4
+; CHECK-P8-NEXT: addi r3, r3, .LCPI10_0@toc@l
+; CHECK-P8-NEXT: lvx v2, 0, r3
+; CHECK-P8-NEXT: vperm v2, v3, v3, v2
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: load_swap51:
; CHECK-P9: # %bb.0:
-; CHECK-P9-NEXT: lxvw4x v2, 0, r4
+; CHECK-P9-NEXT: addis r3, r2, .LCPI10_0@toc@ha
+; CHECK-P9-NEXT: addi r3, r3, .LCPI10_0@toc@l
+; CHECK-P9-NEXT: lxv v2, 0(r4)
+; CHECK-P9-NEXT: lxvx v3, 0, r3
+; CHECK-P9-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-BE-LABEL: load_swap51:
@@ -385,7 +430,8 @@ define void @swap_store00(<2 x i64> %v1, <2 x i64> %v2, <2 x i64>* %vp) {
;
; CHECK-P9-LABEL: swap_store00:
; CHECK-P9: # %bb.0:
-; CHECK-P9-NEXT: stxvd2x v2, 0, r7
+; CHECK-P9-NEXT: xxswapd vs0, v2
+; CHECK-P9-NEXT: stxv vs0, 0(r7)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-BE-LABEL: swap_store00:
@@ -412,7 +458,8 @@ define void @swap_store01(<2 x i64> %v1, <2 x i64> %v2, <2 x i64>* %vp) {
;
; CHECK-P9-LABEL: swap_store01:
; CHECK-P9: # %bb.0:
-; CHECK-P9-NEXT: stxvd2x v3, 0, r7
+; CHECK-P9-NEXT: xxswapd vs0, v3
+; CHECK-P9-NEXT: stxv vs0, 0(r7)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-BE-LABEL: swap_store01:
@@ -434,12 +481,20 @@ define void @swap_store01(<2 x i64> %v1, <2 x i64> %v2, <2 x i64>* %vp) {
define void @swap_store10(<4 x i32> %v1, <4 x i32> %v2, <4 x i32>* %vp) {
; CHECK-P8-LABEL: swap_store10:
; CHECK-P8: # %bb.0:
-; CHECK-P8-NEXT: stxvw4x v2, 0, r7
+; CHECK-P8-NEXT: addis r3, r2, .LCPI13_0@toc@ha
+; CHECK-P8-NEXT: addi r3, r3, .LCPI13_0@toc@l
+; CHECK-P8-NEXT: lvx v3, 0, r3
+; CHECK-P8-NEXT: vperm v2, v2, v2, v3
+; CHECK-P8-NEXT: stvx v2, 0, r7
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: swap_store10:
; CHECK-P9: # %bb.0:
-; CHECK-P9-NEXT: stxvw4x v2, 0, r7
+; CHECK-P9-NEXT: addis r3, r2, .LCPI13_0@toc@ha
+; CHECK-P9-NEXT: addi r3, r3, .LCPI13_0@toc@l
+; CHECK-P9-NEXT: lxvx v3, 0, r3
+; CHECK-P9-NEXT: vperm v2, v2, v2, v3
+; CHECK-P9-NEXT: stxv v2, 0(r7)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-BE-LABEL: swap_store10:
@@ -467,12 +522,20 @@ define void @swap_store10(<4 x i32> %v1, <4 x i32> %v2, <4 x i32>* %vp) {
define void @swap_store11(<4 x i32> %v1, <4 x i32> %v2, <4 x i32>* %vp) {
; CHECK-P8-LABEL: swap_store11:
; CHECK-P8: # %bb.0:
-; CHECK-P8-NEXT: stxvw4x v3, 0, r7
+; CHECK-P8-NEXT: addis r3, r2, .LCPI14_0@toc@ha
+; CHECK-P8-NEXT: addi r3, r3, .LCPI14_0@toc@l
+; CHECK-P8-NEXT: lvx v2, 0, r3
+; CHECK-P8-NEXT: vperm v2, v3, v3, v2
+; CHECK-P8-NEXT: stvx v2, 0, r7
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: swap_store11:
; CHECK-P9: # %bb.0:
-; CHECK-P9-NEXT: stxvw4x v3, 0, r7
+; CHECK-P9-NEXT: addis r3, r2, .LCPI14_0@toc@ha
+; CHECK-P9-NEXT: addi r3, r3, .LCPI14_0@toc@l
+; CHECK-P9-NEXT: lxvx v2, 0, r3
+; CHECK-P9-NEXT: vperm v2, v3, v3, v2
+; CHECK-P9-NEXT: stxv v2, 0(r7)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-BE-LABEL: swap_store11:
@@ -509,7 +572,11 @@ define void @swap_store20(<8 x i16> %v1, <8 x i16> %v2, <8 x i16>* %vp) {
;
; CHECK-P9-LABEL: swap_store20:
; CHECK-P9: # %bb.0:
-; CHECK-P9-NEXT: stxvh8x v2, 0, r7
+; CHECK-P9-NEXT: addis r3, r2, .LCPI15_0@toc@ha
+; CHECK-P9-NEXT: addi r3, r3, .LCPI15_0@toc@l
+; CHECK-P9-NEXT: lxvx v3, 0, r3
+; CHECK-P9-NEXT: vperm v2, v2, v2, v3
+; CHECK-P9-NEXT: stxv v2, 0(r7)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-BE-LABEL: swap_store20:
@@ -546,7 +613,11 @@ define void @swap_store21(<8 x i16> %v1, <8 x i16> %v2, <8 x i16>* %vp) {
;
; CHECK-P9-LABEL: swap_store21:
; CHECK-P9: # %bb.0:
-; CHECK-P9-NEXT: stxvh8x v3, 0, r7
+; CHECK-P9-NEXT: addis r3, r2, .LCPI16_0@toc@ha
+; CHECK-P9-NEXT: addi r3, r3, .LCPI16_0@toc@l
+; CHECK-P9-NEXT: lxvx v2, 0, r3
+; CHECK-P9-NEXT: vperm v2, v3, v3, v2
+; CHECK-P9-NEXT: stxv v2, 0(r7)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-BE-LABEL: swap_store21:
@@ -583,7 +654,8 @@ define void @swap_store30(<16 x i8> %v1, <16 x i8> %v2, <16 x i8>* %vp) {
;
; CHECK-P9-LABEL: swap_store30:
; CHECK-P9: # %bb.0:
-; CHECK-P9-NEXT: stxvb16x v2, 0, r7
+; CHECK-P9-NEXT: xxbrq vs0, v2
+; CHECK-P9-NEXT: stxv vs0, 0(r7)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-BE-LABEL: swap_store30:
@@ -617,7 +689,8 @@ define void @swap_store31(<16 x i8> %v1, <16 x i8> %v2, <16 x i8>* %vp) {
;
; CHECK-P9-LABEL: swap_store31:
; CHECK-P9: # %bb.0:
-; CHECK-P9-NEXT: stxvb16x v3, 0, r7
+; CHECK-P9-NEXT: xxbrq vs0, v3
+; CHECK-P9-NEXT: stxv vs0, 0(r7)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-BE-LABEL: swap_store31:
@@ -647,7 +720,8 @@ define void @swap_store40(<2 x double> %v1, <2 x double> %v2, <2 x double>* %vp)
;
; CHECK-P9-LABEL: swap_store40:
; CHECK-P9: # %bb.0:
-; CHECK-P9-NEXT: stxvd2x v2, 0, r7
+; CHECK-P9-NEXT: xxswapd vs0, v2
+; CHECK-P9-NEXT: stxv vs0, 0(r7)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-BE-LABEL: swap_store40:
@@ -674,7 +748,8 @@ define void @swap_store41(<2 x double> %v1, <2 x double> %v2, <2 x double>* %vp)
;
; CHECK-P9-LABEL: swap_store41:
; CHECK-P9: # %bb.0:
-; CHECK-P9-NEXT: stxvd2x v3, 0, r7
+; CHECK-P9-NEXT: xxswapd vs0, v3
+; CHECK-P9-NEXT: stxv vs0, 0(r7)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-BE-LABEL: swap_store41:
@@ -696,12 +771,20 @@ define void @swap_store41(<2 x double> %v1, <2 x double> %v2, <2 x double>* %vp)
define void @swap_store50(<4 x float> %v1, <4 x float> %v2, <4 x float>* %vp) {
; CHECK-P8-LABEL: swap_store50:
; CHECK-P8: # %bb.0:
-; CHECK-P8-NEXT: stxvw4x v2, 0, r7
+; CHECK-P8-NEXT: addis r3, r2, .LCPI21_0@toc@ha
+; CHECK-P8-NEXT: addi r3, r3, .LCPI21_0@toc@l
+; CHECK-P8-NEXT: lvx v3, 0, r3
+; CHECK-P8-NEXT: vperm v2, v2, v2, v3
+; CHECK-P8-NEXT: stvx v2, 0, r7
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: swap_store50:
; CHECK-P9: # %bb.0:
-; CHECK-P9-NEXT: stxvw4x v2, 0, r7
+; CHECK-P9-NEXT: addis r3, r2, .LCPI21_0@toc@ha
+; CHECK-P9-NEXT: addi r3, r3, .LCPI21_0@toc@l
+; CHECK-P9-NEXT: lxvx v3, 0, r3
+; CHECK-P9-NEXT: vperm v2, v2, v2, v3
+; CHECK-P9-NEXT: stxv v2, 0(r7)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-BE-LABEL: swap_store50:
@@ -729,12 +812,20 @@ define void @swap_store50(<4 x float> %v1, <4 x float> %v2, <4 x float>* %vp) {
define void @swap_store51(<4 x float> %v1, <4 x float> %v2, <4 x float>* %vp) {
; CHECK-P8-LABEL: swap_store51:
; CHECK-P8: # %bb.0:
-; CHECK-P8-NEXT: stxvw4x v3, 0, r7
+; CHECK-P8-NEXT: addis r3, r2, .LCPI22_0@toc@ha
+; CHECK-P8-NEXT: addi r3, r3, .LCPI22_0@toc@l
+; CHECK-P8-NEXT: lvx v2, 0, r3
+; CHECK-P8-NEXT: vperm v2, v3, v3, v2
+; CHECK-P8-NEXT: stvx v2, 0, r7
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: swap_store51:
; CHECK-P9: # %bb.0:
-; CHECK-P9-NEXT: stxvw4x v3, 0, r7
+; CHECK-P9-NEXT: addis r3, r2, .LCPI22_0@toc@ha
+; CHECK-P9-NEXT: addi r3, r3, .LCPI22_0@toc@l
+; CHECK-P9-NEXT: lxvx v2, 0, r3
+; CHECK-P9-NEXT: vperm v2, v3, v3, v2
+; CHECK-P9-NEXT: stxv v2, 0(r7)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-BE-LABEL: swap_store51:
diff --git a/llvm/test/CodeGen/PowerPC/vsx_shuffle_le.ll b/llvm/test/CodeGen/PowerPC/vsx_shuffle_le.ll
index c2b886d6055..cfe20199928 100644
--- a/llvm/test/CodeGen/PowerPC/vsx_shuffle_le.ll
+++ b/llvm/test/CodeGen/PowerPC/vsx_shuffle_le.ll
@@ -85,7 +85,8 @@ define <2 x double> @test10(<2 x double>* %p1, <2 x double>* %p2) {
; CHECK: lxvd2x 34, 0, 3
; CHECK-P9-LABEL: @test10
-; CHECK-P9: lxvd2x 34, 0, 3
+; CHECK-P9: lxv 0, 0(3)
+; CHECK-P9: xxswapd 34, 0
}
define <2 x double> @test11(<2 x double>* %p1, <2 x double>* %p2) {
@@ -256,7 +257,8 @@ define <2 x double> @test32(<2 x double>* %p1, <2 x double>* %p2) {
; CHECK: lxvd2x 34, 0, 4
; CHECK-P9-LABEL: @test32
-; CHECK-P9: lxvd2x 34, 0, 4
+; CHECK-P9: lxv 0, 0(4)
+; CHECK-P9: xxswapd 34, 0
}
define <2 x double> @test33(<2 x double>* %p1, <2 x double>* %p2) {
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