diff options
Diffstat (limited to 'llvm/test/CodeGen/PowerPC')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/fma.ll | 83 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/vsx-fma-sp.ll | 167 |
2 files changed, 250 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/PowerPC/fma.ll b/llvm/test/CodeGen/PowerPC/fma.ll index ab5251b2a55..9cfef398edf 100644 --- a/llvm/test/CodeGen/PowerPC/fma.ll +++ b/llvm/test/CodeGen/PowerPC/fma.ll @@ -1,9 +1,12 @@ ; RUN: llc < %s -march=ppc32 -fp-contract=fast -mattr=-vsx | FileCheck %s ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -fp-contract=fast -mattr=+vsx -mcpu=pwr7 | FileCheck -check-prefix=CHECK-VSX %s +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -fp-contract=fast -mcpu=pwr8 | FileCheck -check-prefix=CHECK-P8 %s +; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -fp-contract=fast -mcpu=pwr8 | FileCheck -check-prefix=CHECK-P8 %s declare double @dummy1(double) #0 declare double @dummy2(double, double) #0 declare double @dummy3(double, double, double) #0 +declare float @dummy4(float, float) #0 define double @test_FMADD1(double %A, double %B, double %C) { %D = fmul double %A, %B ; <double> [#uses=1] @@ -126,3 +129,83 @@ define float @test_FNMSUBS(float %A, float %B, float %C) { ; CHECK-VSX: fnmsubs ; CHECK-VSX-NEXT: blr } + +define float @test_XSMADDMSP(float %A, float %B, float %C) { + %D = fmul float %A, %B ; <float> [#uses=1] + %E = fadd float %C, %D ; <float> [#uses=1] + ret float %E +; CHECK-P8-LABEL: test_XSMADDMSP: +; CHECK-P8: xsmaddmsp +; CHECK-P8-NEXT: blr +} + +define float @test_XSMSUBMSP(float %A, float %B, float %C) { + %D = fmul float %A, %B ; <float> [#uses=1] + %E = fsub float %D, %C ; <float> [#uses=1] + ret float %E +; CHECK-P8-LABEL: test_XSMSUBMSP: +; CHECK-P8: xsmsubmsp +; CHECK-P8-NEXT: blr +} + +define float @test_XSMADDASP(float %A, float %B, float %C, float %D) { + %E = fmul float %A, %B ; <float> [#uses=2] + %F = fadd float %E, %C ; <float> [#uses=1] + %G = fsub float %E, %D ; <float> [#uses=1] + %H = call float @dummy4(float %F, float %G) ; <float> [#uses=1] + ret float %H +; CHECK-P8-LABEL: test_XSMADDASP: +; CHECK-P8: xsmaddasp +; CHECK-P8-NEXT: xsmsubmsp +} + +define float @test_XSMSUBASP(float %A, float %B, float %C, float %D) { + %E = fmul float %A, %B ; <float> [#uses=2] + %F = fsub float %E, %C ; <float> [#uses=1] + %G = fsub float %E, %D ; <float> [#uses=1] + %H = call float @dummy4(float %F, float %G) ; <float> [#uses=1] + ret float %H +; CHECK-P8-LABEL: test_XSMSUBASP: +; CHECK-P8: xsmsubasp +; CHECK-P8-NEXT: xsmsubmsp +} + +define float @test_XSNMADDMSP(float %A, float %B, float %C) { + %D = fmul float %A, %B ; <float> [#uses=1] + %E = fadd float %D, %C ; <float> [#uses=1] + %F = fsub float -0.000000e+00, %E ; <float> [#uses=1] + ret float %F +; CHECK-P8-LABEL: test_XSNMADDMSP: +; CHECK-P8: xsnmaddmsp +; CHECK-P8-NEXT: blr +} + +define float @test_XSNMSUBMSP(float %A, float %B, float %C) { + %D = fmul float %A, %B ; <float> [#uses=1] + %E = fsub float %D, %C ; <float> [#uses=1] + %F = fsub float -0.000000e+00, %E ; <float> [#uses=1] + ret float %F +; CHECK-P8-LABEL: test_XSNMSUBMSP: +; CHECK-P8: xsnmsubmsp +; CHECK-P8-NEXT: blr +} + +define float @test_XSNMADDASP(float %A, float %B, float %C) { + %D = fmul float %A, %B ; <float> [#uses=1] + %E = fadd float %D, %C ; <float> [#uses=1] + %F = fsub float -0.000000e+00, %E ; <float> [#uses=1] + %H = call float @dummy4(float %E, float %F) ; <float> [#uses=1] + ret float %F +; CHECK-P8-LABEL: test_XSNMADDASP: +; CHECK-P8: xsnmaddasp +} + +define float @test_XSNMSUBASP(float %A, float %B, float %C) { + %D = fmul float %A, %B ; <float> [#uses=1] + %E = fsub float %D, %C ; <float> [#uses=1] + %F = fsub float -0.000000e+00, %E ; <float> [#uses=1] + %H = call float @dummy4(float %E, float %F) ; <float> [#uses=1] + ret float %F +; CHECK-P8-LABEL: test_XSNMSUBASP: +; CHECK-P8: xsnmsubasp +} diff --git a/llvm/test/CodeGen/PowerPC/vsx-fma-sp.ll b/llvm/test/CodeGen/PowerPC/vsx-fma-sp.ll new file mode 100644 index 00000000000..1c3e457f92c --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/vsx-fma-sp.ll @@ -0,0 +1,167 @@ +; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=+vsx | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=+vsx -fast-isel -O0 | FileCheck -check-prefix=CHECK-FISL %s +define void @test1sp(float %a, float %b, float %c, float %e, float* nocapture %d) #0 { +entry: + %0 = tail call float @llvm.fma.f32(float %b, float %c, float %a) + store float %0, float* %d, align 4 + %1 = tail call float @llvm.fma.f32(float %b, float %e, float %a) + %arrayidx1 = getelementptr inbounds float, float* %d, i64 1 + store float %1, float* %arrayidx1, align 4 + ret void + +; CHECK-LABEL: @test1sp +; CHECK-DAG: li [[C1:[0-9]+]], 4 +; CHECK-DAG: xsmaddmsp 3, 2, 1 +; CHECK-DAG: xsmaddasp 1, 2, 4 +; CHECK-DAG: stxsspx 3, 0, 7 +; CHECK-DAG: stxsspx 1, 7, [[C1]] +; CHECK: blr + +; CHECK-FISL-LABEL: @test1sp +; CHECK-FISL-DAG: fmr 0, 1 +; CHECK-FISL-DAG: xsmaddasp 0, 2, 3 +; CHECK-FISL-DAG: stxsspx 0, 0, 7 +; CHECK-FISL-DAG: xsmaddasp 1, 2, 4 +; CHECK-FISL-DAG: li [[C1:[0-9]+]], 4 +; CHECK-FISL-DAG: stxsspx 1, 7, [[C1]] +; CHECK-FISL: blr +} + +define void @test2sp(float %a, float %b, float %c, float %e, float %f, float* nocapture %d) #0 { +entry: + %0 = tail call float @llvm.fma.f32(float %b, float %c, float %a) + store float %0, float* %d, align 4 + %1 = tail call float @llvm.fma.f32(float %b, float %e, float %a) + %arrayidx1 = getelementptr inbounds float, float* %d, i64 1 + store float %1, float* %arrayidx1, align 4 + %2 = tail call float @llvm.fma.f32(float %b, float %f, float %a) + %arrayidx2 = getelementptr inbounds float, float* %d, i64 2 + store float %2, float* %arrayidx2, align 4 + ret void + +; CHECK-LABEL: @test2sp +; CHECK-DAG: li [[C1:[0-9]+]], 4 +; CHECK-DAG: li [[C2:[0-9]+]], 8 +; CHECK-DAG: xsmaddmsp 3, 2, 1 +; CHECK-DAG: xsmaddmsp 4, 2, 1 +; CHECK-DAG: xsmaddasp 1, 2, 5 +; CHECK-DAG: stxsspx 3, 0, 8 +; CHECK-DAG: stxsspx 4, 8, [[C1]] +; CHECK-DAG: stxsspx 1, 8, [[C2]] +; CHECK: blr + +; CHECK-FISL-LABEL: @test2sp +; CHECK-FISL-DAG: fmr 0, 1 +; CHECK-FISL-DAG: xsmaddasp 0, 2, 3 +; CHECK-FISL-DAG: stxsspx 0, 0, 8 +; CHECK-FISL-DAG: fmr 0, 1 +; CHECK-FISL-DAG: xsmaddasp 0, 2, 4 +; CHECK-FISL-DAG: li [[C1:[0-9]+]], 4 +; CHECK-FISL-DAG: stxsspx 0, 8, [[C1]] +; CHECK-FISL-DAG: xsmaddasp 1, 2, 5 +; CHECK-FISL-DAG: li [[C2:[0-9]+]], 8 +; CHECK-FISL-DAG: stxsspx 1, 8, [[C2]] +; CHECK-FISL: blr +} + +define void @test3sp(float %a, float %b, float %c, float %e, float %f, float* nocapture %d) #0 { +entry: + %0 = tail call float @llvm.fma.f32(float %b, float %c, float %a) + store float %0, float* %d, align 4 + %1 = tail call float @llvm.fma.f32(float %b, float %e, float %a) + %2 = tail call float @llvm.fma.f32(float %b, float %c, float %1) + %arrayidx1 = getelementptr inbounds float, float* %d, i64 3 + store float %2, float* %arrayidx1, align 4 + %3 = tail call float @llvm.fma.f32(float %b, float %f, float %a) + %arrayidx2 = getelementptr inbounds float, float* %d, i64 2 + store float %3, float* %arrayidx2, align 4 + %arrayidx3 = getelementptr inbounds float, float* %d, i64 1 + store float %1, float* %arrayidx3, align 4 + ret void + +; CHECK-LABEL: @test3sp +; CHECK-DAG: fmr [[F1:[0-9]+]], 1 +; CHECK-DAG: li [[C1:[0-9]+]], 12 +; CHECK-DAG: li [[C2:[0-9]+]], 8 +; CHECK-DAG: li [[C3:[0-9]+]], 4 +; CHECK-DAG: xsmaddmsp 4, 2, 1 +; CHECK-DAG: xsmaddasp 1, 2, 5 + +; Note: We could convert this next FMA to M-type as well, but it would require +; re-ordering the instructions. +; CHECK-DAG: xsmaddasp [[F1]], 2, 3 + +; CHECK-DAG: xsmaddmsp 3, 2, 4 +; CHECK-DAG: stxsspx [[F1]], 0, 8 +; CHECK-DAG: stxsspx 3, 8, [[C1]] +; CHECK-DAG: stxsspx 1, 8, [[C2]] +; CHECK-DAG: stxsspx 4, 8, [[C3]] +; CHECK: blr + +; CHECK-FISL-LABEL: @test3sp +; CHECK-FISL-DAG: fmr [[F1:[0-9]+]], 1 +; CHECK-FISL-DAG: xsmaddasp [[F1]], 2, 4 +; CHECK-FISL-DAG: fmr 4, [[F1]] +; CHECK-FISL-DAG: xsmaddasp 4, 2, 3 +; CHECK-FISL-DAG: li [[C1:[0-9]+]], 12 +; CHECK-FISL-DAG: stxsspx 4, 8, [[C1]] +; CHECK-FISL-DAG: xsmaddasp 1, 2, 5 +; CHECK-FISL-DAG: li [[C2:[0-9]+]], 8 +; CHECK-FISL-DAG: stxsspx 1, 8, [[C2]] +; CHECK-FISL-DAG: li [[C3:[0-9]+]], 4 +; CHECK-FISL-DAG: stxsspx 0, 8, [[C3]] +; CHECK-FISL: blr +} + +define void @test4sp(float %a, float %b, float %c, float %e, float %f, float* nocapture %d) #0 { +entry: + %0 = tail call float @llvm.fma.f32(float %b, float %c, float %a) + store float %0, float* %d, align 4 + %1 = tail call float @llvm.fma.f32(float %b, float %e, float %a) + %arrayidx1 = getelementptr inbounds float, float* %d, i64 1 + store float %1, float* %arrayidx1, align 4 + %2 = tail call float @llvm.fma.f32(float %b, float %c, float %1) + %arrayidx3 = getelementptr inbounds float, float* %d, i64 3 + store float %2, float* %arrayidx3, align 4 + %3 = tail call float @llvm.fma.f32(float %b, float %f, float %a) + %arrayidx4 = getelementptr inbounds float, float* %d, i64 2 + store float %3, float* %arrayidx4, align 4 + ret void + +; CHECK-LABEL: @test4sp +; CHECK-DAG: fmr [[F1:[0-9]+]], 1 +; CHECK-DAG: li [[C1:[0-9]+]], 4 +; CHECK-DAG: li [[C2:[0-9]+]], 8 +; CHECK-DAG: xsmaddmsp 4, 2, 1 + +; Note: We could convert this next FMA to M-type as well, but it would require +; re-ordering the instructions. +; CHECK-DAG: xsmaddasp 1, 2, 5 + +; CHECK-DAG: xsmaddasp [[F1]], 2, 3 +; CHECK-DAG: stxsspx [[F1]], 0, 8 +; CHECK-DAG: stxsspx 4, 8, [[C1]] +; CHECK-DAG: li [[C3:[0-9]+]], 12 +; CHECK-DAG: xsmaddasp 4, 2, 3 +; CHECK-DAG: stxsspx 4, 8, [[C3]] +; CHECK-DAG: stxsspx 1, 8, [[C2]] +; CHECK: blr + +; CHECK-FISL-LABEL: @test4sp +; CHECK-FISL-DAG: fmr [[F1:[0-9]+]], 1 +; CHECK-FISL-DAG: xsmaddasp [[F1]], 2, 3 +; CHECK-FISL-DAG: stxsspx 0, 0, 8 +; CHECK-FISL-DAG: fmr [[F1]], 1 +; CHECK-FISL-DAG: xsmaddasp [[F1]], 2, 4 +; CHECK-FISL-DAG: li [[C3:[0-9]+]], 4 +; CHECK-FISL-DAG: stxsspx 0, 8, [[C3]] +; CHECK-FISL-DAG: xsmaddasp 0, 2, 3 +; CHECK-FISL-DAG: li [[C1:[0-9]+]], 12 +; CHECK-FISL-DAG: stxsspx 0, 8, [[C1]] +; CHECK-FISL-DAG: xsmaddasp 1, 2, 5 +; CHECK-FISL-DAG: li [[C2:[0-9]+]], 8 +; CHECK-FISL-DAG: stxsspx 1, 8, [[C2]] +; CHECK-FISL: blr +} + +declare float @llvm.fma.f32(float, float, float) #0 |
