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-rw-r--r--llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir1
-rw-r--r--llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir1
-rw-r--r--llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir1
3 files changed, 0 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir b/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir
index a49251bde35..cf6ab35d8db 100644
--- a/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir
+++ b/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir
@@ -44,7 +44,6 @@
name: mm_update_next_owner
alignment: 4
exposesReturnsTwice: false
-allVRegsAllocated: true
tracksRegLiveness: true
liveins:
- { reg: '%x3' }
diff --git a/llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir b/llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir
index 45ff51dc958..bd0e7383d52 100644
--- a/llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir
+++ b/llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir
@@ -26,7 +26,6 @@
name: test1
alignment: 4
exposesReturnsTwice: false
-allVRegsAllocated: true
tracksRegLiveness: true
frameInfo:
isFrameAddressTaken: false
diff --git a/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir b/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir
index d4b83b9a499..bba3e152699 100644
--- a/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir
+++ b/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir
@@ -32,7 +32,6 @@
name: fn1
alignment: 2
exposesReturnsTwice: false
-allVRegsAllocated: false
tracksRegLiveness: true
registers:
- { id: 0, class: g8rc }
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