diff options
Diffstat (limited to 'llvm/test/CodeGen/PowerPC/testComparesigesll.ll')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/testComparesigesll.ll | 28 |
1 files changed, 15 insertions, 13 deletions
diff --git a/llvm/test/CodeGen/PowerPC/testComparesigesll.ll b/llvm/test/CodeGen/PowerPC/testComparesigesll.ll index ecfe5b70da0..0926d9eb212 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesigesll.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesigesll.ll @@ -1,10 +1,10 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @glob = common local_unnamed_addr global i64 0, align 8 define signext i32 @test_igesll(i64 %a, i64 %b) { @@ -63,12 +63,11 @@ entry: define void @test_igesll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_igesll_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: sradi r6, r3, 63 -; CHECK-NEXT: addis r5, r2, glob@toc@ha -; CHECK-NEXT: subfc r3, r4, r3 -; CHECK-NEXT: rldicl r3, r4, 1, 63 -; CHECK-NEXT: adde r3, r6, r3 -; CHECK-NEXT: std r3, glob@toc@l(r5) +; CHECK: sradi r6, r3, 63 +; CHECK: subfc r3, r4, r3 +; CHECK: rldicl r3, r4, 1, 63 +; CHECK: adde r3, r6, r3 +; CHECK: std r3 ; CHECK-NEXT: blr entry: %cmp = icmp sge i64 %a, %b @@ -81,12 +80,13 @@ define void @test_igesll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_igesll_sext_store: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sradi r6, r3, 63 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: subfc r3, r4, r3 ; CHECK-NEXT: rldicl r3, r4, 1, 63 +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: adde r3, r6, r3 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: std r3, glob@toc@l(r5) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp sge i64 %a, %b @@ -98,10 +98,11 @@ entry: define void @test_igesll_z_store(i64 %a) { ; CHECK-LABEL: test_igesll_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: not r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: rldicl r3, r3, 1, 63 -; CHECK-NEXT: std r3, glob@toc@l(r4) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp sgt i64 %a, -1 @@ -113,10 +114,11 @@ entry: define void @test_igesll_sext_z_store(i64 %a) { ; CHECK-LABEL: test_igesll_sext_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: not r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: sradi r3, r3, 63 -; CHECK-NEXT: std r3, glob@toc@l(r4) +; CHECK-NEXT: std r3, ; CHECK-NEXT: blr entry: %cmp = icmp sgt i64 %a, -1 |
