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-rw-r--r--llvm/test/CodeGen/PowerPC/testComparesiequs.ll148
1 files changed, 134 insertions, 14 deletions
diff --git a/llvm/test/CodeGen/PowerPC/testComparesiequs.ll b/llvm/test/CodeGen/PowerPC/testComparesiequs.ll
index 710eaf5e232..99b388313e1 100644
--- a/llvm/test/CodeGen/PowerPC/testComparesiequs.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesiequs.ll
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; ModuleID = 'ComparisonTestCases/testComparesiequs.c'
@@ -17,6 +17,19 @@ define signext i32 @test_iequs(i16 zeroext %a, i16 zeroext %b) {
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequs:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequs:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%conv2 = zext i1 %cmp to i32
@@ -32,6 +45,21 @@ define signext i32 @test_iequs_sext(i16 zeroext %a, i16 zeroext %b) {
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequs_sext:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequs_sext:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%sub = sext i1 %cmp to i32
@@ -45,6 +73,17 @@ define signext i32 @test_iequs_z(i16 zeroext %a) {
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequs_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequs_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%conv1 = zext i1 %cmp to i32
@@ -59,6 +98,19 @@ define signext i32 @test_iequs_sext_z(i16 zeroext %a) {
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequs_sext_z:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequs_sext_z:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%sub = sext i1 %cmp to i32
@@ -69,13 +121,30 @@ entry:
define void @test_iequs_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_iequs_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
-; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
+; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: sth r3, 0(r4)
+; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequs_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: sth r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequs_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: sth r3, glob@toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%conv3 = zext i1 %cmp to i16
@@ -87,14 +156,33 @@ entry:
define void @test_iequs_sext_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_iequs_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
+; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
-; CHECK-NEXT: sth r3, 0(r4)
+; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequs_sext_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
+; CHECK-BE-NEXT: xor r3, r3, r4
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: sth r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequs_sext_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xor r3, r3, r4
+; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: sth r3, glob@toc@l(r5)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%conv3 = sext i1 %cmp to i16
@@ -106,12 +194,27 @@ entry:
define void @test_iequs_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_iequs_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: sth r3, 0(r4)
+; CHECK-NEXT: sth r3, glob@toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequs_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: sth r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequs_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: sth r3, glob@toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%conv2 = zext i1 %cmp to i16
@@ -123,13 +226,30 @@ entry:
define void @test_iequs_sext_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_iequs_sext_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
-; CHECK-NEXT: sth r3, 0(r4)
+; CHECK-NEXT: sth r3, glob@toc@l(r4)
; CHECK-NEXT: blr
+; CHECK-BE-LABEL: test_iequs_sext_z_store:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
+; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
+; CHECK-BE-NEXT: srwi r3, r3, 5
+; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: sth r3, 0(r4)
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LE-LABEL: test_iequs_sext_z_store:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
+; CHECK-LE-NEXT: srwi r3, r3, 5
+; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: sth r3, glob@toc@l(r4)
+; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%conv2 = sext i1 %cmp to i16
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