diff options
Diffstat (limited to 'llvm/test/CodeGen/PowerPC/stack-realign.ll')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/stack-realign.ll | 37 |
1 files changed, 21 insertions, 16 deletions
diff --git a/llvm/test/CodeGen/PowerPC/stack-realign.ll b/llvm/test/CodeGen/PowerPC/stack-realign.ll index 1c93d665c16..00cd61df7ed 100644 --- a/llvm/test/CodeGen/PowerPC/stack-realign.ll +++ b/llvm/test/CodeGen/PowerPC/stack-realign.ll @@ -77,22 +77,24 @@ entry: ; CHECK-FP: blr ; CHECK-32-LABEL: @goo -; CHECK-32-DAG: mflr {{[0-9]+}} +; CHECK-32-DAG: mflr [[LR:[0-9]+]] ; CHECK-32-DAG: clrlwi [[REG:[0-9]+]], 1, 27 -; CHECK-32-DAG: stw 30, -8(1) -; CHECK-32-DAG: mr 30, 1 -; CHECK-32-DAG: stw 0, 4(1) +; CHECK-32-DAG: stw [[LR]], 4(1) ; CHECK-32-DAG: subfic 0, [[REG]], -64 ; CHECK-32: stwux 1, 1, 0 +; CHECK-32: subf 0, 0, 1 +; CHECK-32: stw 30, -8(0) +; CHECK-32: mr 30, 0 ; CHECK-32-PIC-LABEL: @goo -; CHECK-32-PIC-DAG: mflr {{[0-9]+}} +; CHECK-32-PIC-DAG: mflr [[LR:[0-9]+]] ; CHECK-32-PIC-DAG: clrlwi [[REG:[0-9]+]], 1, 27 -; CHECK-32-PIC-DAG: stw 29, -12(1) -; CHECK-32-PIC-DAG: mr 29, 1 -; CHECK-32-PIC-DAG: stw 0, 4(1) +; CHECK-32-PIC-DAG: stw [[LR]], 4(1) ; CHECK-32-PIC-DAG: subfic 0, [[REG]], -64 ; CHECK-32-PIC: stwux 1, 1, 0 +; CHECK-32-PIC: subf 0, 0, 1 +; CHECK-32-PIC: stw 29, -12(0) +; CHECK-32-PIC-DAG: mr 29, 0 ; The large-frame-size case. define void @hoo(%struct.s* byval nocapture readonly %a) { @@ -130,13 +132,15 @@ entry: ; CHECK-32-DAG: lis [[REG1:[0-9]+]], -13 ; CHECK-32-DAG: clrlwi [[REG3:[0-9]+]], 1, 27 -; CHECK-32-DAG: mflr {{[0-9]+}} +; CHECK-32-DAG: mflr [[LR:[0-9]+]] ; CHECK-32-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51904 -; CHECK-32-DAG: stw 30, -8(1) -; CHECK-32-DAG: mr 30, 1 -; CHECK-32-DAG: stw 0, 4(1) +; CHECK-32-DAG: stw [[LR]], 4(1) ; CHECK-32-DAG: subfc 0, [[REG3]], [[REG2]] -; CHECK-32: stwux 1, 1, 0 +; CHECK-32: stwux 1, 1, 0 +; CHECK-32: subf 0, 0, 1 +; CHECK-32-DAG: stw 31, -4(0) +; CHECK-32-DAG: stw 30, -8(0) +; CHECK-32: mr 30, 0 ; CHECK-32: blr @@ -146,11 +150,12 @@ entry: ; CHECK-32-PIC-DAG: clrlwi [[REG3:[0-9]+]], 1, 27 ; CHECK-32-PIC-DAG: mflr {{[0-9]+}} ; CHECK-32-PIC-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51904 -; CHECK-32-PIC-DAG: stw 29, -12(1) -; CHECK-32-PIC-DAG: mr 29, 1 ; CHECK-32-PIC-DAG: stw 0, 4(1) ; CHECK-32-PIC-DAG: subfc 0, [[REG3]], [[REG2]] -; CHECK-32: stwux 1, 1, 0 +; CHECK-32-PIC: stwux 1, 1, 0 +; CHECK-32-PIC: stw 29, -12(0) +; CHECK-32-PIC: subf 0, 0, 1 +; CHECK-32-PIC: mr 29, 0 ; CHECK-32: blr |
