diff options
Diffstat (limited to 'llvm/test/CodeGen/PowerPC/float-vector-gather.ll')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/float-vector-gather.ll | 35 |
1 files changed, 15 insertions, 20 deletions
diff --git a/llvm/test/CodeGen/PowerPC/float-vector-gather.ll b/llvm/test/CodeGen/PowerPC/float-vector-gather.ll index 02d4967aae5..b7bb622a1f9 100644 --- a/llvm/test/CodeGen/PowerPC/float-vector-gather.ll +++ b/llvm/test/CodeGen/PowerPC/float-vector-gather.ll @@ -1,6 +1,5 @@ ; NOTE: This test ensures that for both Big and Little Endian cases a set of -; NOTE: 4 floats is gathered into a v4f32 register using xxmrghd, xvcvdpsp, -; NOTE: and vmrgew. +; NOTE: 4 floats is gathered into a v4f32 register using xxmrghw and xxmrgld ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr \ ; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu < %s \ ; RUN: | FileCheck %s -check-prefix=CHECK-LE @@ -16,28 +15,24 @@ float* nocapture readonly %d) { ; } ; CHECK-LE-LABEL: vector_gatherf: ; CHECK-LE: # %bb.0: # %entry -; CHECK-LE-DAG: lfs f[[REG0:[0-9]+]], 0(r3) -; CHECK-LE-DAG: lfs f[[REG1:[0-9]+]], 0(r4) -; CHECK-LE-DAG: lfs f[[REG2:[0-9]+]], 0(r5) -; CHECK-LE-DAG: lfs f[[REG3:[0-9]+]], 0(r6) -; CHECK-LE-DAG: xxmrghd vs[[REG4:[0-9]+]], vs[[REG2]], vs[[REG0]] -; CHECK-LE-NEXT: xvcvdpsp v[[VREG2:[0-9]+]], vs[[REG4]] -; CHECK-LE-NEXT: xxmrghd vs[[REG5:[0-9]+]], vs[[REG3]], vs[[REG1]] -; CHECK-LE-NEXT: xvcvdpsp v[[VREG3:[0-9]+]], vs[[REG5]] -; CHECK-LE-NEXT: vmrgew v[[VREG:[0-9]+]], v[[VREG3]], v[[VREG2]] +; CHECK-LE-DAG: lfiwzx f[[REG0:[0-9]+]], 0, r6 +; CHECK-LE-DAG: lfiwzx f[[REG1:[0-9]+]], 0, r5 +; CHECK-LE-DAG: lfiwzx f[[REG2:[0-9]+]], 0, r4 +; CHECK-LE-DAG: lfiwzx f[[REG3:[0-9]+]], 0, r3 +; CHECK-LE-DAG: xxmrghw vs[[REG0]], vs[[REG0]], vs[[REG1]] +; CHECK-LE-DAG: xxmrghw vs[[REG4:[0-9]+]], vs[[REG2]], vs[[REG3]] +; CHECK-LE-NEXT: xxmrgld v[[REG:[0-9]+]], vs[[REG0]], vs[[REG4]] ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: vector_gatherf: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-DAG: lfs f[[REG0:[0-9]+]], 0(r3) -; CHECK-BE-DAG: lfs f[[REG1:[0-9]+]], 0(r4) -; CHECK-BE-DAG: lfs f[[REG2:[0-9]+]], 0(r5) -; CHECK-BE-DAG: lfs f[[REG3:[0-9]+]], 0(r6) -; CHECK-BE-DAG: xxmrghd vs[[REG4:[0-9]+]], vs[[REG0]], vs[[REG2]] -; CHECK-BE-DAG: xxmrghd vs[[REG5:[0-9]+]], vs[[REG1]], vs[[REG3]] -; CHECK-BE-NEXT: xvcvdpsp v[[VREG2:[0-9]+]], vs[[REG5]] -; CHECK-BE-NEXT: xvcvdpsp v[[VREG3:[0-9]+]], vs[[REG4]] -; CHECK-BE-NEXT: vmrgew v[[VREG:[0-9]+]], v[[VREG3]], v[[VREG2]] +; CHECK-BE-DAG: lfiwzx f[[REG0:[0-9]+]], 0, r3 +; CHECK-BE-DAG: lfiwzx f[[REG1:[0-9]+]], 0, r4 +; CHECK-BE-DAG: lfiwzx f[[REG2:[0-9]+]], 0, r5 +; CHECK-BE-DAG: lfiwzx f[[REG3:[0-9]+]], 0, r6 +; CHECK-BE-DAG: xxmrghw vs[[REG0]], vs[[REG0]], vs[[REG1]] +; CHECK-BE-DAG: xxmrghw vs[[REG4:[0-9]+]], vs[[REG2]], vs[[REG3]] +; CHECK-BE-NEXT: xxmrgld v[[REG:[0-9]+]], vs[[REG0]], vs[[REG4]] ; CHECK-BE-NEXT: blr entry: %0 = load float, float* %a, align 4 |
