diff options
Diffstat (limited to 'llvm/test/CodeGen/PowerPC/f128-vecExtractNconv.ll')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/f128-vecExtractNconv.ll | 863 |
1 files changed, 432 insertions, 431 deletions
diff --git a/llvm/test/CodeGen/PowerPC/f128-vecExtractNconv.ll b/llvm/test/CodeGen/PowerPC/f128-vecExtractNconv.ll index ff5be8c8ba2..3ab5ee94142 100644 --- a/llvm/test/CodeGen/PowerPC/f128-vecExtractNconv.ll +++ b/llvm/test/CodeGen/PowerPC/f128-vecExtractNconv.ll @@ -1,9 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \ -; RUN: -verify-machineinstrs -enable-ppc-quad-precision < %s | FileCheck %s -; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown \ -; RUN: -verify-machineinstrs -enable-ppc-quad-precision < %s | \ -; RUN: FileCheck %s -check-prefix=CHECK-BE +; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -ppc-vsr-nums-as-vr \ +; RUN: -ppc-asm-full-reg-names -verify-machineinstrs \ +; RUN: -enable-ppc-quad-precision < %s | FileCheck %s +; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown -ppc-vsr-nums-as-vr \ +; RUN: -ppc-asm-full-reg-names -verify-machineinstrs \ +; RUN: -enable-ppc-quad-precision < %s | FileCheck %s -check-prefix=CHECK-BE ; Vector extract DWord and convert to quad precision. @@ -14,14 +15,14 @@ define void @sdwVecConv2qp(fp128* nocapture %a, <2 x i64> %b) { ; CHECK-LABEL: sdwVecConv2qp: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xxspltd 34, 34, 1 -; CHECK-NEXT: xscvsdqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: xxspltd v2, v2, 1 +; CHECK-NEXT: xscvsdqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; CHECK-BE-LABEL: sdwVecConv2qp: -; CHECK-BE: xscvsdqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE: xscvsdqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <2 x i64> %b, i32 0 @@ -34,15 +35,15 @@ entry: define void @sdwVecConv2qp1(fp128* nocapture %a, <2 x i64> %b) { ; CHECK-LABEL: sdwVecConv2qp1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xscvsdqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: xscvsdqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; CHECK-BE-LABEL: sdwVecConv2qp1: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: xxspltd 34, 34, 1 -; CHECK-BE-NEXT: xscvsdqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: xxspltd v2, v2, 1 +; CHECK-BE-NEXT: xscvsdqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <2 x i64> %b, i32 1 @@ -55,11 +56,11 @@ entry: define void @sdwVecConv2qp_02(fp128* nocapture %a) { ; CHECK-LABEL: sdwVecConv2qp_02: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis 4, 2, .LC0@toc@ha -; CHECK-NEXT: ld 4, .LC0@toc@l(4) -; CHECK-NEXT: lxsd 2, 0(4) -; CHECK-NEXT: xscvsdqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: lxsd v2, 0(r4) +; CHECK-NEXT: xscvsdqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr entry: %0 = load <2 x i64>, <2 x i64>* @sdwVecMem, align 16 @@ -73,9 +74,9 @@ entry: define void @sdwVecConv2qp1_03(fp128* nocapture %a, <2 x i64>* nocapture readonly %b) { ; CHECK-LABEL: sdwVecConv2qp1_03: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: lxsd 2, 8(4) -; CHECK-NEXT: xscvsdqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: lxsd v2, 8(r4) +; CHECK-NEXT: xscvsdqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr entry: %0 = load <2 x i64>, <2 x i64>* %b, align 16 @@ -89,15 +90,15 @@ entry: define void @udwVecConv2qp(fp128* nocapture %a, <2 x i64> %b) { ; CHECK-LABEL: udwVecConv2qp: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xxspltd 34, 34, 1 -; CHECK-NEXT: xscvudqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: xxspltd v2, v2, 1 +; CHECK-NEXT: xscvudqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; CHECK-BE-LABEL: udwVecConv2qp: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: xscvudqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: xscvudqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <2 x i64> %b, i32 0 @@ -110,15 +111,15 @@ entry: define void @udwVecConv2qp1(fp128* nocapture %a, <2 x i64> %b) { ; CHECK-LABEL: udwVecConv2qp1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xscvudqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: xscvudqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; CHECK-BE-LABEL: udwVecConv2qp1: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: xxspltd 34, 34, 1 -; CHECK-BE-NEXT: xscvudqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: xxspltd v2, v2, 1 +; CHECK-BE-NEXT: xscvudqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <2 x i64> %b, i32 1 @@ -131,11 +132,11 @@ entry: define void @udwVecConv2qp1_02(fp128* nocapture %a) { ; CHECK-LABEL: udwVecConv2qp1_02: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis 4, 2, .LC1@toc@ha -; CHECK-NEXT: ld 4, .LC1@toc@l(4) -; CHECK-NEXT: lxsd 2, 8(4) -; CHECK-NEXT: xscvudqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: addis r4, r2, .LC1@toc@ha +; CHECK-NEXT: ld r4, .LC1@toc@l(r4) +; CHECK-NEXT: lxsd v2, 8(r4) +; CHECK-NEXT: xscvudqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr entry: %0 = load <2 x i64>, <2 x i64>* @udwVecMem, align 16 @@ -149,9 +150,9 @@ entry: define void @udwVecConv2qp_03(fp128* nocapture %a, <2 x i64>* nocapture readonly %b) { ; CHECK-LABEL: udwVecConv2qp_03: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: lxsd 2, 0(4) -; CHECK-NEXT: xscvudqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: lxsd v2, 0(r4) +; CHECK-NEXT: xscvudqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr entry: %0 = load <2 x i64>, <2 x i64>* %b, align 16 @@ -167,17 +168,17 @@ entry: define void @swVecConv2qp(fp128* nocapture %a, <4 x i32> %b) { ; CHECK-LABEL: swVecConv2qp: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vspltw 2, 2, 3 -; CHECK-NEXT: vextsw2d 2, 2 -; CHECK-NEXT: xscvsdqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vspltw v2, v2, 3 +; CHECK-NEXT: vextsw2d v2, v2 +; CHECK-NEXT: xscvsdqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; CHECK-BE-LABEL: swVecConv2qp: -; CHECK-BE: vspltw 2, 2, 0 -; CHECK-BE-NEXT: vextsw2d 2, 2 -; CHECK-BE-NEXT: xscvsdqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE: vspltw v2, v2, 0 +; CHECK-BE-NEXT: vextsw2d v2, v2 +; CHECK-BE-NEXT: xscvsdqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <4 x i32> %b, i32 0 @@ -190,16 +191,16 @@ entry: define void @swVecConv2qp1(fp128* nocapture %a, <4 x i32> %b) { ; CHECK-LABEL: swVecConv2qp1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vspltw 2, 2, 2 -; CHECK-NEXT: vextsw2d 2, 2 -; CHECK-NEXT: xscvsdqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vspltw v2, v2, 2 +; CHECK-NEXT: vextsw2d v2, v2 +; CHECK-NEXT: xscvsdqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; CHECK-BE-LABEL: swVecConv2qp1: -; CHECK-BE: vextsw2d 2, 2 -; CHECK-BE-NEXT: xscvsdqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE: vextsw2d v2, v2 +; CHECK-BE-NEXT: xscvsdqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <4 x i32> %b, i32 1 @@ -212,16 +213,16 @@ entry: define void @swVecConv2qp2(fp128* nocapture %a, <4 x i32> %b) { ; CHECK-LABEL: swVecConv2qp2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextsw2d 2, 2 -; CHECK-NEXT: xscvsdqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextsw2d v2, v2 +; CHECK-NEXT: xscvsdqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; CHECK-BE-LABEL: swVecConv2qp2: -; CHECK-BE: vspltw 2, 2, 2 -; CHECK-BE-NEXT: vextsw2d 2, 2 -; CHECK-BE-NEXT: xscvsdqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE: vspltw v2, v2, 2 +; CHECK-BE-NEXT: vextsw2d v2, v2 +; CHECK-BE-NEXT: xscvsdqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <4 x i32> %b, i32 2 @@ -234,17 +235,17 @@ entry: define void @swVecConv2qp3(fp128* nocapture %a, <4 x i32> %b) { ; CHECK-LABEL: swVecConv2qp3: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vspltw 2, 2, 0 -; CHECK-NEXT: vextsw2d 2, 2 -; CHECK-NEXT: xscvsdqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vspltw v2, v2, 0 +; CHECK-NEXT: vextsw2d v2, v2 +; CHECK-NEXT: xscvsdqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; CHECK-BE-LABEL: swVecConv2qp3: -; CHECK-BE: vspltw 2, 2, 3 -; CHECK-BE-NEXT: vextsw2d 2, 2 -; CHECK-BE-NEXT: xscvsdqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE: vspltw v2, v2, 3 +; CHECK-BE-NEXT: vextsw2d v2, v2 +; CHECK-BE-NEXT: xscvsdqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <4 x i32> %b, i32 3 @@ -257,15 +258,15 @@ entry: define void @uwVecConv2qp(fp128* nocapture %a, <4 x i32> %b) { ; CHECK-LABEL: uwVecConv2qp: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xxextractuw 34, 34, 12 -; CHECK-NEXT: xscvudqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: xxextractuw v2, v2, 12 +; CHECK-NEXT: xscvudqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; CHECK-BE-LABEL: uwVecConv2qp: -; CHECK-BE: xxextractuw 34, 34, 0 -; CHECK-BE-NEXT: xscvudqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE: xxextractuw v2, v2, 0 +; CHECK-BE-NEXT: xscvudqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <4 x i32> %b, i32 0 @@ -278,15 +279,15 @@ entry: define void @uwVecConv2qp1(fp128* nocapture %a, <4 x i32> %b) { ; CHECK-LABEL: uwVecConv2qp1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xxextractuw 34, 34, 8 -; CHECK-NEXT: xscvudqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: xxextractuw v2, v2, 8 +; CHECK-NEXT: xscvudqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; CHECK-BE-LABEL: uwVecConv2qp1: -; CHECK-BE: xxextractuw 34, 34, 4 -; CHECK-BE-NEXT: xscvudqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE: xxextractuw v2, v2, 4 +; CHECK-BE-NEXT: xscvudqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <4 x i32> %b, i32 1 @@ -299,15 +300,15 @@ entry: define void @uwVecConv2qp2(fp128* nocapture %a, <4 x i32> %b) { ; CHECK-LABEL: uwVecConv2qp2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xxextractuw 34, 34, 4 -; CHECK-NEXT: xscvudqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: xxextractuw v2, v2, 4 +; CHECK-NEXT: xscvudqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; CHECK-BE-LABEL: uwVecConv2qp2: -; CHECK-BE: xxextractuw 34, 34, 8 -; CHECK-BE-NEXT: xscvudqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE: xxextractuw v2, v2, 8 +; CHECK-BE-NEXT: xscvudqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <4 x i32> %b, i32 2 @@ -320,15 +321,15 @@ entry: define void @uwVecConv2qp3(fp128* nocapture %a, <4 x i32> %b) { ; CHECK-LABEL: uwVecConv2qp3: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xxextractuw 34, 34, 0 -; CHECK-NEXT: xscvudqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: xxextractuw v2, v2, 0 +; CHECK-NEXT: xscvudqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; CHECK-BE-LABEL: uwVecConv2qp3: -; CHECK-BE: xxextractuw 34, 34, 12 -; CHECK-BE-NEXT: xscvudqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE: xxextractuw v2, v2, 12 +; CHECK-BE-NEXT: xscvudqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <4 x i32> %b, i32 3 @@ -343,18 +344,18 @@ entry: define void @shwVecConv2qp(fp128* nocapture %a, <8 x i16> %b) { ; CHECK-LABEL: shwVecConv2qp: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractuh 2, 2, 14 -; CHECK-NEXT: vextsh2d 2, 2 -; CHECK-NEXT: xscvsdqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractuh v2, v2, 14 +; CHECK-NEXT: vextsh2d v2, v2 +; CHECK-NEXT: xscvsdqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: shwVecConv2qp: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractuh 2, 2, 0 -; CHECK-BE-NEXT: vextsh2d 2, 2 -; CHECK-BE-NEXT: xscvsdqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractuh v2, v2, 0 +; CHECK-BE-NEXT: vextsh2d v2, v2 +; CHECK-BE-NEXT: xscvsdqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <8 x i16> %b, i32 0 @@ -367,18 +368,18 @@ entry: define void @shwVecConv2qp1(fp128* nocapture %a, <8 x i16> %b) { ; CHECK-LABEL: shwVecConv2qp1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractuh 2, 2, 12 -; CHECK-NEXT: vextsh2d 2, 2 -; CHECK-NEXT: xscvsdqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractuh v2, v2, 12 +; CHECK-NEXT: vextsh2d v2, v2 +; CHECK-NEXT: xscvsdqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: shwVecConv2qp1: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractuh 2, 2, 2 -; CHECK-BE-NEXT: vextsh2d 2, 2 -; CHECK-BE-NEXT: xscvsdqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractuh v2, v2, 2 +; CHECK-BE-NEXT: vextsh2d v2, v2 +; CHECK-BE-NEXT: xscvsdqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <8 x i16> %b, i32 1 @@ -391,18 +392,18 @@ entry: define void @shwVecConv2qp2(fp128* nocapture %a, <8 x i16> %b) { ; CHECK-LABEL: shwVecConv2qp2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractuh 2, 2, 10 -; CHECK-NEXT: vextsh2d 2, 2 -; CHECK-NEXT: xscvsdqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractuh v2, v2, 10 +; CHECK-NEXT: vextsh2d v2, v2 +; CHECK-NEXT: xscvsdqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: shwVecConv2qp2: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractuh 2, 2, 4 -; CHECK-BE-NEXT: vextsh2d 2, 2 -; CHECK-BE-NEXT: xscvsdqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractuh v2, v2, 4 +; CHECK-BE-NEXT: vextsh2d v2, v2 +; CHECK-BE-NEXT: xscvsdqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <8 x i16> %b, i32 2 @@ -415,18 +416,18 @@ entry: define void @shwVecConv2qp3(fp128* nocapture %a, <8 x i16> %b) { ; CHECK-LABEL: shwVecConv2qp3: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractuh 2, 2, 8 -; CHECK-NEXT: vextsh2d 2, 2 -; CHECK-NEXT: xscvsdqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractuh v2, v2, 8 +; CHECK-NEXT: vextsh2d v2, v2 +; CHECK-NEXT: xscvsdqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: shwVecConv2qp3: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractuh 2, 2, 6 -; CHECK-BE-NEXT: vextsh2d 2, 2 -; CHECK-BE-NEXT: xscvsdqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractuh v2, v2, 6 +; CHECK-BE-NEXT: vextsh2d v2, v2 +; CHECK-BE-NEXT: xscvsdqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <8 x i16> %b, i32 3 @@ -439,18 +440,18 @@ entry: define void @shwVecConv2qp4(fp128* nocapture %a, <8 x i16> %b) { ; CHECK-LABEL: shwVecConv2qp4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractuh 2, 2, 6 -; CHECK-NEXT: vextsh2d 2, 2 -; CHECK-NEXT: xscvsdqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractuh v2, v2, 6 +; CHECK-NEXT: vextsh2d v2, v2 +; CHECK-NEXT: xscvsdqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: shwVecConv2qp4: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractuh 2, 2, 8 -; CHECK-BE-NEXT: vextsh2d 2, 2 -; CHECK-BE-NEXT: xscvsdqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractuh v2, v2, 8 +; CHECK-BE-NEXT: vextsh2d v2, v2 +; CHECK-BE-NEXT: xscvsdqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <8 x i16> %b, i32 4 @@ -463,18 +464,18 @@ entry: define void @shwVecConv2qp5(fp128* nocapture %a, <8 x i16> %b) { ; CHECK-LABEL: shwVecConv2qp5: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractuh 2, 2, 4 -; CHECK-NEXT: vextsh2d 2, 2 -; CHECK-NEXT: xscvsdqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractuh v2, v2, 4 +; CHECK-NEXT: vextsh2d v2, v2 +; CHECK-NEXT: xscvsdqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: shwVecConv2qp5: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractuh 2, 2, 10 -; CHECK-BE-NEXT: vextsh2d 2, 2 -; CHECK-BE-NEXT: xscvsdqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractuh v2, v2, 10 +; CHECK-BE-NEXT: vextsh2d v2, v2 +; CHECK-BE-NEXT: xscvsdqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <8 x i16> %b, i32 5 @@ -487,18 +488,18 @@ entry: define void @shwVecConv2qp6(fp128* nocapture %a, <8 x i16> %b) { ; CHECK-LABEL: shwVecConv2qp6: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractuh 2, 2, 2 -; CHECK-NEXT: vextsh2d 2, 2 -; CHECK-NEXT: xscvsdqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractuh v2, v2, 2 +; CHECK-NEXT: vextsh2d v2, v2 +; CHECK-NEXT: xscvsdqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: shwVecConv2qp6: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractuh 2, 2, 12 -; CHECK-BE-NEXT: vextsh2d 2, 2 -; CHECK-BE-NEXT: xscvsdqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractuh v2, v2, 12 +; CHECK-BE-NEXT: vextsh2d v2, v2 +; CHECK-BE-NEXT: xscvsdqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <8 x i16> %b, i32 6 @@ -511,18 +512,18 @@ entry: define void @shwVecConv2qp7(fp128* nocapture %a, <8 x i16> %b) { ; CHECK-LABEL: shwVecConv2qp7: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractuh 2, 2, 0 -; CHECK-NEXT: vextsh2d 2, 2 -; CHECK-NEXT: xscvsdqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractuh v2, v2, 0 +; CHECK-NEXT: vextsh2d v2, v2 +; CHECK-NEXT: xscvsdqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: shwVecConv2qp7: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractuh 2, 2, 14 -; CHECK-BE-NEXT: vextsh2d 2, 2 -; CHECK-BE-NEXT: xscvsdqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractuh v2, v2, 14 +; CHECK-BE-NEXT: vextsh2d v2, v2 +; CHECK-BE-NEXT: xscvsdqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <8 x i16> %b, i32 7 @@ -535,16 +536,16 @@ entry: define void @uhwVecConv2qp(fp128* nocapture %a, <8 x i16> %b) { ; CHECK-LABEL: uhwVecConv2qp: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractuh 2, 2, 14 -; CHECK-NEXT: xscvudqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractuh v2, v2, 14 +; CHECK-NEXT: xscvudqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: uhwVecConv2qp: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractuh 2, 2, 0 -; CHECK-BE-NEXT: xscvudqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractuh v2, v2, 0 +; CHECK-BE-NEXT: xscvudqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <8 x i16> %b, i32 0 @@ -557,16 +558,16 @@ entry: define void @uhwVecConv2qp1(fp128* nocapture %a, <8 x i16> %b) { ; CHECK-LABEL: uhwVecConv2qp1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractuh 2, 2, 12 -; CHECK-NEXT: xscvudqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractuh v2, v2, 12 +; CHECK-NEXT: xscvudqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: uhwVecConv2qp1: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractuh 2, 2, 2 -; CHECK-BE-NEXT: xscvudqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractuh v2, v2, 2 +; CHECK-BE-NEXT: xscvudqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <8 x i16> %b, i32 1 @@ -579,16 +580,16 @@ entry: define void @uhwVecConv2qp2(fp128* nocapture %a, <8 x i16> %b) { ; CHECK-LABEL: uhwVecConv2qp2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractuh 2, 2, 10 -; CHECK-NEXT: xscvudqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractuh v2, v2, 10 +; CHECK-NEXT: xscvudqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: uhwVecConv2qp2: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractuh 2, 2, 4 -; CHECK-BE-NEXT: xscvudqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractuh v2, v2, 4 +; CHECK-BE-NEXT: xscvudqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <8 x i16> %b, i32 2 @@ -601,16 +602,16 @@ entry: define void @uhwVecConv2qp3(fp128* nocapture %a, <8 x i16> %b) { ; CHECK-LABEL: uhwVecConv2qp3: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractuh 2, 2, 8 -; CHECK-NEXT: xscvudqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractuh v2, v2, 8 +; CHECK-NEXT: xscvudqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: uhwVecConv2qp3: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractuh 2, 2, 6 -; CHECK-BE-NEXT: xscvudqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractuh v2, v2, 6 +; CHECK-BE-NEXT: xscvudqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <8 x i16> %b, i32 3 @@ -623,16 +624,16 @@ entry: define void @uhwVecConv2qp4(fp128* nocapture %a, <8 x i16> %b) { ; CHECK-LABEL: uhwVecConv2qp4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractuh 2, 2, 6 -; CHECK-NEXT: xscvudqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractuh v2, v2, 6 +; CHECK-NEXT: xscvudqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: uhwVecConv2qp4: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractuh 2, 2, 8 -; CHECK-BE-NEXT: xscvudqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractuh v2, v2, 8 +; CHECK-BE-NEXT: xscvudqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <8 x i16> %b, i32 4 @@ -645,16 +646,16 @@ entry: define void @uhwVecConv2qp5(fp128* nocapture %a, <8 x i16> %b) { ; CHECK-LABEL: uhwVecConv2qp5: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractuh 2, 2, 4 -; CHECK-NEXT: xscvudqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractuh v2, v2, 4 +; CHECK-NEXT: xscvudqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: uhwVecConv2qp5: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractuh 2, 2, 10 -; CHECK-BE-NEXT: xscvudqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractuh v2, v2, 10 +; CHECK-BE-NEXT: xscvudqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <8 x i16> %b, i32 5 @@ -667,16 +668,16 @@ entry: define void @uhwVecConv2qp6(fp128* nocapture %a, <8 x i16> %b) { ; CHECK-LABEL: uhwVecConv2qp6: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractuh 2, 2, 2 -; CHECK-NEXT: xscvudqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractuh v2, v2, 2 +; CHECK-NEXT: xscvudqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: uhwVecConv2qp6: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractuh 2, 2, 12 -; CHECK-BE-NEXT: xscvudqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractuh v2, v2, 12 +; CHECK-BE-NEXT: xscvudqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <8 x i16> %b, i32 6 @@ -689,16 +690,16 @@ entry: define void @uhwVecConv2qp7(fp128* nocapture %a, <8 x i16> %b) { ; CHECK-LABEL: uhwVecConv2qp7: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractuh 2, 2, 0 -; CHECK-NEXT: xscvudqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractuh v2, v2, 0 +; CHECK-NEXT: xscvudqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: uhwVecConv2qp7: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractuh 2, 2, 14 -; CHECK-BE-NEXT: xscvudqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractuh v2, v2, 14 +; CHECK-BE-NEXT: xscvudqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <8 x i16> %b, i32 7 @@ -713,18 +714,18 @@ entry: define void @sbVecConv2qp(fp128* nocapture %a, <16 x i8> %b) { ; CHECK-LABEL: sbVecConv2qp: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractub 2, 2, 15 -; CHECK-NEXT: vextsb2d 2, 2 -; CHECK-NEXT: xscvsdqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractub v2, v2, 15 +; CHECK-NEXT: vextsb2d v2, v2 +; CHECK-NEXT: xscvsdqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: sbVecConv2qp: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractub 2, 2, 0 -; CHECK-BE-NEXT: vextsb2d 2, 2 -; CHECK-BE-NEXT: xscvsdqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractub v2, v2, 0 +; CHECK-BE-NEXT: vextsb2d v2, v2 +; CHECK-BE-NEXT: xscvsdqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <16 x i8> %b, i32 0 @@ -737,18 +738,18 @@ entry: define void @sbVecConv2qp1(fp128* nocapture %a, <16 x i8> %b) { ; CHECK-LABEL: sbVecConv2qp1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractub 2, 2, 14 -; CHECK-NEXT: vextsb2d 2, 2 -; CHECK-NEXT: xscvsdqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractub v2, v2, 14 +; CHECK-NEXT: vextsb2d v2, v2 +; CHECK-NEXT: xscvsdqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: sbVecConv2qp1: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractub 2, 2, 1 -; CHECK-BE-NEXT: vextsb2d 2, 2 -; CHECK-BE-NEXT: xscvsdqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractub v2, v2, 1 +; CHECK-BE-NEXT: vextsb2d v2, v2 +; CHECK-BE-NEXT: xscvsdqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <16 x i8> %b, i32 1 @@ -761,18 +762,18 @@ entry: define void @sbVecConv2qp2(fp128* nocapture %a, <16 x i8> %b) { ; CHECK-LABEL: sbVecConv2qp2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractub 2, 2, 13 -; CHECK-NEXT: vextsb2d 2, 2 -; CHECK-NEXT: xscvsdqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractub v2, v2, 13 +; CHECK-NEXT: vextsb2d v2, v2 +; CHECK-NEXT: xscvsdqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: sbVecConv2qp2: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractub 2, 2, 2 -; CHECK-BE-NEXT: vextsb2d 2, 2 -; CHECK-BE-NEXT: xscvsdqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractub v2, v2, 2 +; CHECK-BE-NEXT: vextsb2d v2, v2 +; CHECK-BE-NEXT: xscvsdqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <16 x i8> %b, i32 2 @@ -785,18 +786,18 @@ entry: define void @sbVecConv2qp3(fp128* nocapture %a, <16 x i8> %b) { ; CHECK-LABEL: sbVecConv2qp3: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractub 2, 2, 12 -; CHECK-NEXT: vextsb2d 2, 2 -; CHECK-NEXT: xscvsdqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractub v2, v2, 12 +; CHECK-NEXT: vextsb2d v2, v2 +; CHECK-NEXT: xscvsdqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: sbVecConv2qp3: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractub 2, 2, 3 -; CHECK-BE-NEXT: vextsb2d 2, 2 -; CHECK-BE-NEXT: xscvsdqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractub v2, v2, 3 +; CHECK-BE-NEXT: vextsb2d v2, v2 +; CHECK-BE-NEXT: xscvsdqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <16 x i8> %b, i32 3 @@ -809,18 +810,18 @@ entry: define void @sbVecConv2qp4(fp128* nocapture %a, <16 x i8> %b) { ; CHECK-LABEL: sbVecConv2qp4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractub 2, 2, 11 -; CHECK-NEXT: vextsb2d 2, 2 -; CHECK-NEXT: xscvsdqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractub v2, v2, 11 +; CHECK-NEXT: vextsb2d v2, v2 +; CHECK-NEXT: xscvsdqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: sbVecConv2qp4: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractub 2, 2, 4 -; CHECK-BE-NEXT: vextsb2d 2, 2 -; CHECK-BE-NEXT: xscvsdqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractub v2, v2, 4 +; CHECK-BE-NEXT: vextsb2d v2, v2 +; CHECK-BE-NEXT: xscvsdqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <16 x i8> %b, i32 4 @@ -833,18 +834,18 @@ entry: define void @sbVecConv2qp5(fp128* nocapture %a, <16 x i8> %b) { ; CHECK-LABEL: sbVecConv2qp5: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractub 2, 2, 10 -; CHECK-NEXT: vextsb2d 2, 2 -; CHECK-NEXT: xscvsdqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractub v2, v2, 10 +; CHECK-NEXT: vextsb2d v2, v2 +; CHECK-NEXT: xscvsdqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: sbVecConv2qp5: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractub 2, 2, 5 -; CHECK-BE-NEXT: vextsb2d 2, 2 -; CHECK-BE-NEXT: xscvsdqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractub v2, v2, 5 +; CHECK-BE-NEXT: vextsb2d v2, v2 +; CHECK-BE-NEXT: xscvsdqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <16 x i8> %b, i32 5 @@ -857,18 +858,18 @@ entry: define void @sbVecConv2qp6(fp128* nocapture %a, <16 x i8> %b) { ; CHECK-LABEL: sbVecConv2qp6: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractub 2, 2, 9 -; CHECK-NEXT: vextsb2d 2, 2 -; CHECK-NEXT: xscvsdqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractub v2, v2, 9 +; CHECK-NEXT: vextsb2d v2, v2 +; CHECK-NEXT: xscvsdqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: sbVecConv2qp6: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractub 2, 2, 6 -; CHECK-BE-NEXT: vextsb2d 2, 2 -; CHECK-BE-NEXT: xscvsdqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractub v2, v2, 6 +; CHECK-BE-NEXT: vextsb2d v2, v2 +; CHECK-BE-NEXT: xscvsdqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <16 x i8> %b, i32 6 @@ -881,18 +882,18 @@ entry: define void @sbVecConv2qp7(fp128* nocapture %a, <16 x i8> %b) { ; CHECK-LABEL: sbVecConv2qp7: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractub 2, 2, 8 -; CHECK-NEXT: vextsb2d 2, 2 -; CHECK-NEXT: xscvsdqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractub v2, v2, 8 +; CHECK-NEXT: vextsb2d v2, v2 +; CHECK-NEXT: xscvsdqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: sbVecConv2qp7: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractub 2, 2, 7 -; CHECK-BE-NEXT: vextsb2d 2, 2 -; CHECK-BE-NEXT: xscvsdqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractub v2, v2, 7 +; CHECK-BE-NEXT: vextsb2d v2, v2 +; CHECK-BE-NEXT: xscvsdqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <16 x i8> %b, i32 7 @@ -905,18 +906,18 @@ entry: define void @sbVecConv2qp8(fp128* nocapture %a, <16 x i8> %b) { ; CHECK-LABEL: sbVecConv2qp8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractub 2, 2, 7 -; CHECK-NEXT: vextsb2d 2, 2 -; CHECK-NEXT: xscvsdqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractub v2, v2, 7 +; CHECK-NEXT: vextsb2d v2, v2 +; CHECK-NEXT: xscvsdqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: sbVecConv2qp8: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractub 2, 2, 8 -; CHECK-BE-NEXT: vextsb2d 2, 2 -; CHECK-BE-NEXT: xscvsdqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractub v2, v2, 8 +; CHECK-BE-NEXT: vextsb2d v2, v2 +; CHECK-BE-NEXT: xscvsdqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <16 x i8> %b, i32 8 @@ -929,18 +930,18 @@ entry: define void @sbVecConv2qp9(fp128* nocapture %a, <16 x i8> %b) { ; CHECK-LABEL: sbVecConv2qp9: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractub 2, 2, 6 -; CHECK-NEXT: vextsb2d 2, 2 -; CHECK-NEXT: xscvsdqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractub v2, v2, 6 +; CHECK-NEXT: vextsb2d v2, v2 +; CHECK-NEXT: xscvsdqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: sbVecConv2qp9: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractub 2, 2, 9 -; CHECK-BE-NEXT: vextsb2d 2, 2 -; CHECK-BE-NEXT: xscvsdqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractub v2, v2, 9 +; CHECK-BE-NEXT: vextsb2d v2, v2 +; CHECK-BE-NEXT: xscvsdqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <16 x i8> %b, i32 9 @@ -953,18 +954,18 @@ entry: define void @sbVecConv2qp10(fp128* nocapture %a, <16 x i8> %b) { ; CHECK-LABEL: sbVecConv2qp10: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractub 2, 2, 5 -; CHECK-NEXT: vextsb2d 2, 2 -; CHECK-NEXT: xscvsdqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractub v2, v2, 5 +; CHECK-NEXT: vextsb2d v2, v2 +; CHECK-NEXT: xscvsdqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: sbVecConv2qp10: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractub 2, 2, 10 -; CHECK-BE-NEXT: vextsb2d 2, 2 -; CHECK-BE-NEXT: xscvsdqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractub v2, v2, 10 +; CHECK-BE-NEXT: vextsb2d v2, v2 +; CHECK-BE-NEXT: xscvsdqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <16 x i8> %b, i32 10 @@ -977,18 +978,18 @@ entry: define void @sbVecConv2qp11(fp128* nocapture %a, <16 x i8> %b) { ; CHECK-LABEL: sbVecConv2qp11: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractub 2, 2, 4 -; CHECK-NEXT: vextsb2d 2, 2 -; CHECK-NEXT: xscvsdqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractub v2, v2, 4 +; CHECK-NEXT: vextsb2d v2, v2 +; CHECK-NEXT: xscvsdqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: sbVecConv2qp11: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractub 2, 2, 11 -; CHECK-BE-NEXT: vextsb2d 2, 2 -; CHECK-BE-NEXT: xscvsdqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractub v2, v2, 11 +; CHECK-BE-NEXT: vextsb2d v2, v2 +; CHECK-BE-NEXT: xscvsdqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <16 x i8> %b, i32 11 @@ -1001,18 +1002,18 @@ entry: define void @sbVecConv2qp12(fp128* nocapture %a, <16 x i8> %b) { ; CHECK-LABEL: sbVecConv2qp12: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractub 2, 2, 3 -; CHECK-NEXT: vextsb2d 2, 2 -; CHECK-NEXT: xscvsdqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractub v2, v2, 3 +; CHECK-NEXT: vextsb2d v2, v2 +; CHECK-NEXT: xscvsdqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: sbVecConv2qp12: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractub 2, 2, 12 -; CHECK-BE-NEXT: vextsb2d 2, 2 -; CHECK-BE-NEXT: xscvsdqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractub v2, v2, 12 +; CHECK-BE-NEXT: vextsb2d v2, v2 +; CHECK-BE-NEXT: xscvsdqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <16 x i8> %b, i32 12 @@ -1025,18 +1026,18 @@ entry: define void @sbVecConv2qp13(fp128* nocapture %a, <16 x i8> %b) { ; CHECK-LABEL: sbVecConv2qp13: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractub 2, 2, 2 -; CHECK-NEXT: vextsb2d 2, 2 -; CHECK-NEXT: xscvsdqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractub v2, v2, 2 +; CHECK-NEXT: vextsb2d v2, v2 +; CHECK-NEXT: xscvsdqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: sbVecConv2qp13: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractub 2, 2, 13 -; CHECK-BE-NEXT: vextsb2d 2, 2 -; CHECK-BE-NEXT: xscvsdqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractub v2, v2, 13 +; CHECK-BE-NEXT: vextsb2d v2, v2 +; CHECK-BE-NEXT: xscvsdqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <16 x i8> %b, i32 13 @@ -1049,18 +1050,18 @@ entry: define void @sbVecConv2qp14(fp128* nocapture %a, <16 x i8> %b) { ; CHECK-LABEL: sbVecConv2qp14: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractub 2, 2, 1 -; CHECK-NEXT: vextsb2d 2, 2 -; CHECK-NEXT: xscvsdqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractub v2, v2, 1 +; CHECK-NEXT: vextsb2d v2, v2 +; CHECK-NEXT: xscvsdqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: sbVecConv2qp14: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractub 2, 2, 14 -; CHECK-BE-NEXT: vextsb2d 2, 2 -; CHECK-BE-NEXT: xscvsdqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractub v2, v2, 14 +; CHECK-BE-NEXT: vextsb2d v2, v2 +; CHECK-BE-NEXT: xscvsdqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <16 x i8> %b, i32 14 @@ -1073,18 +1074,18 @@ entry: define void @sbVecConv2qp15(fp128* nocapture %a, <16 x i8> %b) { ; CHECK-LABEL: sbVecConv2qp15: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractub 2, 2, 0 -; CHECK-NEXT: vextsb2d 2, 2 -; CHECK-NEXT: xscvsdqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractub v2, v2, 0 +; CHECK-NEXT: vextsb2d v2, v2 +; CHECK-NEXT: xscvsdqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: sbVecConv2qp15: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractub 2, 2, 15 -; CHECK-BE-NEXT: vextsb2d 2, 2 -; CHECK-BE-NEXT: xscvsdqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractub v2, v2, 15 +; CHECK-BE-NEXT: vextsb2d v2, v2 +; CHECK-BE-NEXT: xscvsdqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <16 x i8> %b, i32 15 @@ -1097,16 +1098,16 @@ entry: define void @ubVecConv2qp(fp128* nocapture %a, <16 x i8> %b) { ; CHECK-LABEL: ubVecConv2qp: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractub 2, 2, 15 -; CHECK-NEXT: xscvudqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractub v2, v2, 15 +; CHECK-NEXT: xscvudqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: ubVecConv2qp: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractub 2, 2, 0 -; CHECK-BE-NEXT: xscvudqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractub v2, v2, 0 +; CHECK-BE-NEXT: xscvudqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <16 x i8> %b, i32 0 @@ -1119,16 +1120,16 @@ entry: define void @ubVecConv2qp1(fp128* nocapture %a, <16 x i8> %b) { ; CHECK-LABEL: ubVecConv2qp1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractub 2, 2, 14 -; CHECK-NEXT: xscvudqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractub v2, v2, 14 +; CHECK-NEXT: xscvudqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: ubVecConv2qp1: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractub 2, 2, 1 -; CHECK-BE-NEXT: xscvudqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractub v2, v2, 1 +; CHECK-BE-NEXT: xscvudqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <16 x i8> %b, i32 1 @@ -1141,16 +1142,16 @@ entry: define void @ubVecConv2qp2(fp128* nocapture %a, <16 x i8> %b) { ; CHECK-LABEL: ubVecConv2qp2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractub 2, 2, 13 -; CHECK-NEXT: xscvudqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractub v2, v2, 13 +; CHECK-NEXT: xscvudqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: ubVecConv2qp2: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractub 2, 2, 2 -; CHECK-BE-NEXT: xscvudqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractub v2, v2, 2 +; CHECK-BE-NEXT: xscvudqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <16 x i8> %b, i32 2 @@ -1163,16 +1164,16 @@ entry: define void @ubVecConv2qp3(fp128* nocapture %a, <16 x i8> %b) { ; CHECK-LABEL: ubVecConv2qp3: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractub 2, 2, 12 -; CHECK-NEXT: xscvudqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractub v2, v2, 12 +; CHECK-NEXT: xscvudqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: ubVecConv2qp3: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractub 2, 2, 3 -; CHECK-BE-NEXT: xscvudqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractub v2, v2, 3 +; CHECK-BE-NEXT: xscvudqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <16 x i8> %b, i32 3 @@ -1185,16 +1186,16 @@ entry: define void @ubVecConv2qp4(fp128* nocapture %a, <16 x i8> %b) { ; CHECK-LABEL: ubVecConv2qp4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractub 2, 2, 11 -; CHECK-NEXT: xscvudqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractub v2, v2, 11 +; CHECK-NEXT: xscvudqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: ubVecConv2qp4: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractub 2, 2, 4 -; CHECK-BE-NEXT: xscvudqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractub v2, v2, 4 +; CHECK-BE-NEXT: xscvudqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <16 x i8> %b, i32 4 @@ -1207,16 +1208,16 @@ entry: define void @ubVecConv2qp5(fp128* nocapture %a, <16 x i8> %b) { ; CHECK-LABEL: ubVecConv2qp5: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractub 2, 2, 10 -; CHECK-NEXT: xscvudqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractub v2, v2, 10 +; CHECK-NEXT: xscvudqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: ubVecConv2qp5: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractub 2, 2, 5 -; CHECK-BE-NEXT: xscvudqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractub v2, v2, 5 +; CHECK-BE-NEXT: xscvudqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <16 x i8> %b, i32 5 @@ -1229,16 +1230,16 @@ entry: define void @ubVecConv2qp6(fp128* nocapture %a, <16 x i8> %b) { ; CHECK-LABEL: ubVecConv2qp6: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractub 2, 2, 9 -; CHECK-NEXT: xscvudqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractub v2, v2, 9 +; CHECK-NEXT: xscvudqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: ubVecConv2qp6: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractub 2, 2, 6 -; CHECK-BE-NEXT: xscvudqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractub v2, v2, 6 +; CHECK-BE-NEXT: xscvudqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <16 x i8> %b, i32 6 @@ -1251,16 +1252,16 @@ entry: define void @ubVecConv2qp7(fp128* nocapture %a, <16 x i8> %b) { ; CHECK-LABEL: ubVecConv2qp7: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractub 2, 2, 8 -; CHECK-NEXT: xscvudqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractub v2, v2, 8 +; CHECK-NEXT: xscvudqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: ubVecConv2qp7: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractub 2, 2, 7 -; CHECK-BE-NEXT: xscvudqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractub v2, v2, 7 +; CHECK-BE-NEXT: xscvudqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <16 x i8> %b, i32 7 @@ -1273,16 +1274,16 @@ entry: define void @ubVecConv2qp8(fp128* nocapture %a, <16 x i8> %b) { ; CHECK-LABEL: ubVecConv2qp8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractub 2, 2, 7 -; CHECK-NEXT: xscvudqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractub v2, v2, 7 +; CHECK-NEXT: xscvudqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: ubVecConv2qp8: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractub 2, 2, 8 -; CHECK-BE-NEXT: xscvudqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractub v2, v2, 8 +; CHECK-BE-NEXT: xscvudqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <16 x i8> %b, i32 8 @@ -1295,16 +1296,16 @@ entry: define void @ubVecConv2qp9(fp128* nocapture %a, <16 x i8> %b) { ; CHECK-LABEL: ubVecConv2qp9: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractub 2, 2, 6 -; CHECK-NEXT: xscvudqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractub v2, v2, 6 +; CHECK-NEXT: xscvudqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: ubVecConv2qp9: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractub 2, 2, 9 -; CHECK-BE-NEXT: xscvudqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractub v2, v2, 9 +; CHECK-BE-NEXT: xscvudqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <16 x i8> %b, i32 9 @@ -1317,16 +1318,16 @@ entry: define void @ubVecConv2qp10(fp128* nocapture %a, <16 x i8> %b) { ; CHECK-LABEL: ubVecConv2qp10: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractub 2, 2, 5 -; CHECK-NEXT: xscvudqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractub v2, v2, 5 +; CHECK-NEXT: xscvudqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: ubVecConv2qp10: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractub 2, 2, 10 -; CHECK-BE-NEXT: xscvudqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractub v2, v2, 10 +; CHECK-BE-NEXT: xscvudqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <16 x i8> %b, i32 10 @@ -1339,16 +1340,16 @@ entry: define void @ubVecConv2qp11(fp128* nocapture %a, <16 x i8> %b) { ; CHECK-LABEL: ubVecConv2qp11: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractub 2, 2, 4 -; CHECK-NEXT: xscvudqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractub v2, v2, 4 +; CHECK-NEXT: xscvudqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: ubVecConv2qp11: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractub 2, 2, 11 -; CHECK-BE-NEXT: xscvudqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractub v2, v2, 11 +; CHECK-BE-NEXT: xscvudqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <16 x i8> %b, i32 11 @@ -1361,16 +1362,16 @@ entry: define void @ubVecConv2qp12(fp128* nocapture %a, <16 x i8> %b) { ; CHECK-LABEL: ubVecConv2qp12: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractub 2, 2, 3 -; CHECK-NEXT: xscvudqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractub v2, v2, 3 +; CHECK-NEXT: xscvudqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: ubVecConv2qp12: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractub 2, 2, 12 -; CHECK-BE-NEXT: xscvudqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractub v2, v2, 12 +; CHECK-BE-NEXT: xscvudqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <16 x i8> %b, i32 12 @@ -1383,16 +1384,16 @@ entry: define void @ubVecConv2qp13(fp128* nocapture %a, <16 x i8> %b) { ; CHECK-LABEL: ubVecConv2qp13: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractub 2, 2, 2 -; CHECK-NEXT: xscvudqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractub v2, v2, 2 +; CHECK-NEXT: xscvudqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: ubVecConv2qp13: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractub 2, 2, 13 -; CHECK-BE-NEXT: xscvudqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractub v2, v2, 13 +; CHECK-BE-NEXT: xscvudqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <16 x i8> %b, i32 13 @@ -1405,16 +1406,16 @@ entry: define void @ubVecConv2qp14(fp128* nocapture %a, <16 x i8> %b) { ; CHECK-LABEL: ubVecConv2qp14: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractub 2, 2, 1 -; CHECK-NEXT: xscvudqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractub v2, v2, 1 +; CHECK-NEXT: xscvudqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: ubVecConv2qp14: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractub 2, 2, 14 -; CHECK-BE-NEXT: xscvudqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractub v2, v2, 14 +; CHECK-BE-NEXT: xscvudqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <16 x i8> %b, i32 14 @@ -1427,16 +1428,16 @@ entry: define void @ubVecConv2qp15(fp128* nocapture %a, <16 x i8> %b) { ; CHECK-LABEL: ubVecConv2qp15: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextractub 2, 2, 0 -; CHECK-NEXT: xscvudqp 2, 2 -; CHECK-NEXT: stxv 34, 0(3) +; CHECK-NEXT: vextractub v2, v2, 0 +; CHECK-NEXT: xscvudqp v2, v2 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: ubVecConv2qp15: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextractub 2, 2, 15 -; CHECK-BE-NEXT: xscvudqp 2, 2 -; CHECK-BE-NEXT: stxv 34, 0(3) +; CHECK-BE-NEXT: vextractub v2, v2, 15 +; CHECK-BE-NEXT: xscvudqp v2, v2 +; CHECK-BE-NEXT: stxv v2, 0(r3) ; CHECK-BE-NEXT: blr entry: %vecext = extractelement <16 x i8> %b, i32 15 |
