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-rw-r--r--llvm/test/CodeGen/PowerPC/f128-rounding.ll15
1 files changed, 8 insertions, 7 deletions
diff --git a/llvm/test/CodeGen/PowerPC/f128-rounding.ll b/llvm/test/CodeGen/PowerPC/f128-rounding.ll
index ac0b3be9cd0..063eb1456fd 100644
--- a/llvm/test/CodeGen/PowerPC/f128-rounding.ll
+++ b/llvm/test/CodeGen/PowerPC/f128-rounding.ll
@@ -1,5 +1,6 @@
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
-; RUN: -enable-ppc-quad-precision -verify-machineinstrs < %s | FileCheck %s
+; RUN: -enable-ppc-quad-precision -verify-machineinstrs \
+; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
define void @qp_trunc(fp128* nocapture readonly %a, fp128* nocapture %res) {
@@ -9,7 +10,7 @@ entry:
store fp128 %1, fp128* %res, align 16
ret void
; CHECK-LABEL: qp_trunc
-; CHECK: xsrqpi 1, {{[0-9]+}}, {{[0-9]+}}, 1
+; CHECK: xsrqpi 1, v{{[0-9]+}}, v{{[0-9]+}}, 1
; CHECK: blr
}
declare fp128 @llvm.trunc.f128(fp128 %Val)
@@ -21,7 +22,7 @@ entry:
store fp128 %1, fp128* %res, align 16
ret void
; CHECK-LABEL: qp_rint
-; CHECK: xsrqpix 0, {{[0-9]+}}, {{[0-9]+}}, 3
+; CHECK: xsrqpix 0, v{{[0-9]+}}, v{{[0-9]+}}, 3
; CHECK: blr
}
declare fp128 @llvm.rint.f128(fp128 %Val)
@@ -33,7 +34,7 @@ entry:
store fp128 %1, fp128* %res, align 16
ret void
; CHECK-LABEL: qp_nearbyint
-; CHECK: xsrqpi 0, {{[0-9]+}}, {{[0-9]+}}, 3
+; CHECK: xsrqpi 0, v{{[0-9]+}}, v{{[0-9]+}}, 3
; CHECK: blr
}
declare fp128 @llvm.nearbyint.f128(fp128 %Val)
@@ -45,7 +46,7 @@ entry:
store fp128 %1, fp128* %res, align 16
ret void
; CHECK-LABEL: qp_round
-; CHECK: xsrqpi 0, {{[0-9]+}}, {{[0-9]+}}, 0
+; CHECK: xsrqpi 0, v{{[0-9]+}}, v{{[0-9]+}}, 0
; CHECK: blr
}
declare fp128 @llvm.round.f128(fp128 %Val)
@@ -57,7 +58,7 @@ entry:
store fp128 %1, fp128* %res, align 16
ret void
; CHECK-LABEL: qp_floor
-; CHECK: xsrqpi 1, {{[0-9]+}}, {{[0-9]+}}, 3
+; CHECK: xsrqpi 1, v{{[0-9]+}}, v{{[0-9]+}}, 3
; CHECK: blr
}
declare fp128 @llvm.floor.f128(fp128 %Val)
@@ -69,7 +70,7 @@ entry:
store fp128 %1, fp128* %res, align 16
ret void
; CHECK-LABEL: qp_ceil
-; CHECK: xsrqpi 1, {{[0-9]+}}, {{[0-9]+}}, 2
+; CHECK: xsrqpi 1, v{{[0-9]+}}, v{{[0-9]+}}, 2
; CHECK: blr
}
declare fp128 @llvm.ceil.f128(fp128 %Val)
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