summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen/PowerPC/f128-conv.ll
diff options
context:
space:
mode:
Diffstat (limited to 'llvm/test/CodeGen/PowerPC/f128-conv.ll')
-rw-r--r--llvm/test/CodeGen/PowerPC/f128-conv.ll402
1 files changed, 201 insertions, 201 deletions
diff --git a/llvm/test/CodeGen/PowerPC/f128-conv.ll b/llvm/test/CodeGen/PowerPC/f128-conv.ll
index 42949685e3c..4ac0a009974 100644
--- a/llvm/test/CodeGen/PowerPC/f128-conv.ll
+++ b/llvm/test/CodeGen/PowerPC/f128-conv.ll
@@ -1,6 +1,6 @@
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
; RUN: -enable-ppc-quad-precision -ppc-vsr-nums-as-vr \
-; RUN: -verify-machineinstrs < %s | FileCheck %s
+; RUN: -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s
@mem = global [5 x i64] [i64 56, i64 63, i64 3, i64 5, i64 6], align 8
@umem = global [5 x i64] [i64 560, i64 100, i64 34, i64 2, i64 5], align 8
@@ -17,9 +17,9 @@ entry:
ret void
; CHECK-LABEL: sdwConv2qp
-; CHECK: mtvsrd [[REG:[0-9]+]], 4
-; CHECK-NEXT: xscvsdqp [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: mtvsrd v[[REG:[0-9]+]], r4
+; CHECK-NEXT: xscvsdqp v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -33,11 +33,11 @@ entry:
ret void
; CHECK-LABEL: sdwConv2qp_02
-; CHECK: addis [[REG:[0-9]+]], 2, .LC0@toc@ha
-; CHECK: ld [[REG]], .LC0@toc@l([[REG]])
-; CHECK: lxsd [[REG0:[0-9]+]], 16([[REG]])
-; CHECK-NEXT: xscvsdqp [[CONV:[0-9]+]], [[REG0]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: addis r[[REG:[0-9]+]], r2, .LC0@toc@ha
+; CHECK: ld r[[REG]], .LC0@toc@l(r[[REG]])
+; CHECK: lxsd v[[REG0:[0-9]+]], 16(r[[REG]])
+; CHECK-NEXT: xscvsdqp v[[CONV:[0-9]+]], v[[REG0]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -51,9 +51,9 @@ entry:
; CHECK-LABEL: sdwConv2qp_03
; CHECK-NOT: ld
-; CHECK: lxsd [[REG0:[0-9]+]], 0(4)
-; CHECK-NEXT: xscvsdqp [[CONV:[0-9]+]], [[REG0]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: lxsd v[[REG0:[0-9]+]], 0(r4)
+; CHECK-NEXT: xscvsdqp v[[CONV:[0-9]+]], v[[REG0]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -65,9 +65,9 @@ entry:
ret void
; CHECK-LABEL: udwConv2qp
-; CHECK: mtvsrd [[REG:[0-9]+]], 4
-; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: mtvsrd v[[REG:[0-9]+]], r4
+; CHECK-NEXT: xscvudqp v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -81,11 +81,11 @@ entry:
ret void
; CHECK-LABEL: udwConv2qp_02
-; CHECK: addis [[REG:[0-9]+]], 2, .LC1@toc@ha
-; CHECK: ld [[REG]], .LC1@toc@l([[REG]])
-; CHECK: lxsd [[REG0:[0-9]+]], 32([[REG]])
-; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG0]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: addis r[[REG:[0-9]+]], r2, .LC1@toc@ha
+; CHECK: ld r[[REG]], .LC1@toc@l(r[[REG]])
+; CHECK: lxsd v[[REG0:[0-9]+]], 32(r[[REG]])
+; CHECK-NEXT: xscvudqp v[[CONV:[0-9]+]], v[[REG0]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -99,9 +99,9 @@ entry:
; CHECK-LABEL: udwConv2qp_03
; CHECK-NOT: ld
-; CHECK: lxsd [[REG:[0-9]+]], 0(4)
-; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: lxsd v[[REG:[0-9]+]], 0(r4)
+; CHECK-NEXT: xscvudqp v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -117,9 +117,9 @@ entry:
ret fp128* %sink
; CHECK-LABEL: sdwConv2qp_testXForm
-; CHECK: lxsdx [[REG:[0-9]+]],
-; CHECK-NEXT: xscvsdqp [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: lxsdx v[[REG:[0-9]+]],
+; CHECK-NEXT: xscvsdqp v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -135,9 +135,9 @@ entry:
ret fp128* %sink
; CHECK-LABEL: udwConv2qp_testXForm
-; CHECK: lxsdx [[REG:[0-9]+]],
-; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: lxsdx v[[REG:[0-9]+]],
+; CHECK-NEXT: xscvudqp v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -150,9 +150,9 @@ entry:
; CHECK-LABEL: swConv2qp
; CHECK-NOT: lwz
-; CHECK: mtvsrwa [[REG:[0-9]+]], 4
-; CHECK-NEXT: xscvsdqp [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: mtvsrwa v[[REG:[0-9]+]], r4
+; CHECK-NEXT: xscvsdqp v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -166,9 +166,9 @@ entry:
; CHECK-LABEL: swConv2qp_02
; CHECK-NOT: lwz
-; CHECK: lxsiwax [[REG:[0-9]+]], 0, 4
-; CHECK-NEXT: xscvsdqp [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: lxsiwax v[[REG:[0-9]+]], 0, r4
+; CHECK-NEXT: xscvsdqp v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -182,12 +182,12 @@ entry:
ret void
; CHECK-LABEL: swConv2qp_03
-; CHECK: addis [[REG:[0-9]+]], 2, .LC2@toc@ha
-; CHECK: ld [[REG]], .LC2@toc@l([[REG]])
-; CHECK: addi [[REG2:[0-9]+]], [[REG]], 12
-; CHECK: lxsiwax [[REG0:[0-9]+]], 0, [[REG2]]
-; CHECK-NEXT: xscvsdqp [[CONV:[0-9]+]], [[REG0]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: addis r[[REG:[0-9]+]], r2, .LC2@toc@ha
+; CHECK: ld r[[REG]], .LC2@toc@l(r[[REG]])
+; CHECK: addi r[[REG2:[0-9]+]], r[[REG]], 12
+; CHECK: lxsiwax v[[REG0:[0-9]+]], 0, r[[REG2]]
+; CHECK-NEXT: xscvsdqp v[[CONV:[0-9]+]], v[[REG0]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -200,9 +200,9 @@ entry:
; CHECK-LABEL: uwConv2qp
; CHECK-NOT: lwz
-; CHECK: mtvsrwz [[REG:[0-9]+]], 4
-; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: mtvsrwz v[[REG:[0-9]+]], r4
+; CHECK-NEXT: xscvudqp v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -216,9 +216,9 @@ entry:
; CHECK-LABEL: uwConv2qp_02
; CHECK-NOT: lwz
-; CHECK: lxsiwzx [[REG:[0-9]+]], 0, 4
-; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: lxsiwzx v[[REG:[0-9]+]], 0, r4
+; CHECK-NEXT: xscvudqp v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -232,12 +232,12 @@ entry:
ret void
; CHECK-LABEL: uwConv2qp_03
-; CHECK: addis [[REG:[0-9]+]], 2, .LC3@toc@ha
-; CHECK-NEXT: ld [[REG]], .LC3@toc@l([[REG]])
-; CHECK-NEXT: addi [[REG2:[0-9]+]], [[REG]], 12
-; CHECK-NEXT: lxsiwzx [[REG1:[0-9]+]], 0, [[REG2]]
-; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG1]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: addis r[[REG:[0-9]+]], r2, .LC3@toc@ha
+; CHECK-NEXT: ld r[[REG]], .LC3@toc@l(r[[REG]])
+; CHECK-NEXT: addi r[[REG2:[0-9]+]], r[[REG]], 12
+; CHECK-NEXT: lxsiwzx v[[REG1:[0-9]+]], 0, r[[REG2]]
+; CHECK-NEXT: xscvudqp v[[CONV:[0-9]+]], v[[REG1]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -252,11 +252,11 @@ entry:
ret void
; CHECK-LABEL: uwConv2qp_04
-; CHECK: lwz [[REG:[0-9]+]], 0(5)
-; CHECK-NEXT: add [[REG1:[0-9]+]], [[REG]], [[REG1]]
-; CHECK-NEXT: mtvsrwz [[REG0:[0-9]+]], [[REG1]]
-; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG0]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: lwz r[[REG:[0-9]+]], 0(r5)
+; CHECK-NEXT: add r[[REG1:[0-9]+]], r[[REG]], r[[REG1]]
+; CHECK-NEXT: mtvsrwz v[[REG0:[0-9]+]], r[[REG1]]
+; CHECK-NEXT: xscvudqp v[[CONV:[0-9]+]], v[[REG0]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -269,9 +269,9 @@ entry:
; CHECK-LABEL: uhwConv2qp
-; CHECK: mtvsrwz [[REG:[0-9]+]], 4
-; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: mtvsrwz v[[REG:[0-9]+]], r4
+; CHECK-NEXT: xscvudqp v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -284,9 +284,9 @@ entry:
ret void
; CHECK-LABEL: uhwConv2qp_02
-; CHECK: lxsihzx [[REG:[0-9]+]], 0, 4
-; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: lxsihzx v[[REG:[0-9]+]], 0, r4
+; CHECK-NEXT: xscvudqp v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -300,12 +300,12 @@ entry:
ret void
; CHECK-LABEL: uhwConv2qp_03
-; CHECK: addis [[REG0:[0-9]+]], 2, .LC4@toc@ha
-; CHECK: ld [[REG0]], .LC4@toc@l([[REG0]])
-; CHECK: addi [[REG0]], [[REG0]], 6
-; CHECK: lxsihzx [[REG:[0-9]+]], 0, [[REG0]]
-; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: addis r[[REG0:[0-9]+]], r2, .LC4@toc@ha
+; CHECK: ld r[[REG0]], .LC4@toc@l(r[[REG0]])
+; CHECK: addi r[[REG0]], r[[REG0]], 6
+; CHECK: lxsihzx v[[REG:[0-9]+]], 0, r[[REG0]]
+; CHECK-NEXT: xscvudqp v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -322,11 +322,11 @@ entry:
ret void
; CHECK-LABEL: uhwConv2qp_04
-; CHECK: lhz [[REG0:[0-9]+]], 0(5)
-; CHECK: add 4, [[REG0]], 4
-; CHECK: mtvsrwa [[REG:[0-9]+]], 4
-; CHECK-NEXT: xscvsdqp [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: lhz r[[REG0:[0-9]+]], 0(r5)
+; CHECK: add r4, r[[REG0]], r4
+; CHECK: mtvsrwa v[[REG:[0-9]+]], r4
+; CHECK-NEXT: xscvsdqp v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -338,9 +338,9 @@ entry:
ret void
; CHECK-LABEL: ubConv2qp
-; CHECK: mtvsrwz [[REG:[0-9]+]], 4
-; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: mtvsrwz v[[REG:[0-9]+]], r4
+; CHECK-NEXT: xscvudqp v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -353,9 +353,9 @@ entry:
ret void
; CHECK-LABEL: ubConv2qp_02
-; CHECK: lxsibzx [[REG:[0-9]+]], 0, 4
-; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: lxsibzx v[[REG:[0-9]+]], 0, r4
+; CHECK-NEXT: xscvudqp v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -369,12 +369,12 @@ entry:
ret void
; CHECK-LABEL: ubConv2qp_03
-; CHECK: addis [[REG0:[0-9]+]], 2, .LC5@toc@ha
-; CHECK: ld [[REG0]], .LC5@toc@l([[REG0]])
-; CHECK: addi [[REG0]], [[REG0]], 2
-; CHECK: lxsibzx [[REG:[0-9]+]], 0, [[REG0]]
-; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: addis r[[REG0:[0-9]+]], r2, .LC5@toc@ha
+; CHECK: ld r[[REG0]], .LC5@toc@l(r[[REG0]])
+; CHECK: addi r[[REG0]], r[[REG0]], 2
+; CHECK: lxsibzx v[[REG:[0-9]+]], 0, r[[REG0]]
+; CHECK-NEXT: xscvudqp v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -391,11 +391,11 @@ entry:
ret void
; CHECK-LABEL: ubConv2qp_04
-; CHECK: lbz [[REG0:[0-9]+]], 0(5)
-; CHECK: add 4, [[REG0]], 4
-; CHECK: mtvsrwa [[REG:[0-9]+]], 4
-; CHECK-NEXT: xscvsdqp [[CONV:[0-9]+]], [[REG]]
-; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK: lbz r[[REG0:[0-9]+]], 0(r5)
+; CHECK: add r4, r[[REG0]], r4
+; CHECK: mtvsrwa v[[REG:[0-9]+]], r4
+; CHECK-NEXT: xscvsdqp v[[CONV:[0-9]+]], v[[REG]]
+; CHECK-NEXT: stxv v[[CONV]], 0(r3)
; CHECK-NEXT: blr
}
@@ -412,9 +412,9 @@ entry:
define double @qpConv2dp(fp128* nocapture readonly %a) {
; CHECK-LABEL: qpConv2dp:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lxv 2, 0(3)
-; CHECK-NEXT: xscvqpdp 2, 2
-; CHECK-NEXT: xxlor 1, 2, 2
+; CHECK-NEXT: lxv v2, 0(r3)
+; CHECK-NEXT: xscvqpdp v2, v2
+; CHECK-NEXT: xxlor f1, v2, v2
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* %a, align 16
@@ -426,11 +426,11 @@ entry:
define void @qpConv2dp_02(double* nocapture %res) {
; CHECK-LABEL: qpConv2dp_02:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis 4, 2, .LC6@toc@ha
-; CHECK-NEXT: ld 4, .LC6@toc@l(4)
-; CHECK-NEXT: lxvx 2, 0, 4
-; CHECK-NEXT: xscvqpdp 2, 2
-; CHECK-NEXT: stxsd 2, 0(3)
+; CHECK-NEXT: addis r4, r2, .LC6@toc@ha
+; CHECK-NEXT: ld r4, .LC6@toc@l(r4)
+; CHECK-NEXT: lxvx v2, 0, r4
+; CHECK-NEXT: xscvqpdp v2, v2
+; CHECK-NEXT: stxsd v2, 0(r3)
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* @f128global, align 16
@@ -443,12 +443,12 @@ entry:
define void @qpConv2dp_03(double* nocapture %res, i32 signext %idx) {
; CHECK-LABEL: qpConv2dp_03:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis 5, 2, .LC7@toc@ha
-; CHECK-NEXT: sldi 4, 4, 3
-; CHECK-NEXT: ld 5, .LC7@toc@l(5)
-; CHECK-NEXT: lxvx 2, 0, 5
-; CHECK-NEXT: xscvqpdp 2, 2
-; CHECK-NEXT: stxsdx 2, 3, 4
+; CHECK-NEXT: addis r5, r2, .LC7@toc@ha
+; CHECK-NEXT: sldi r4, r4, 3
+; CHECK-NEXT: ld r5, .LC7@toc@l(r5)
+; CHECK-NEXT: lxvx v2, 0, r5
+; CHECK-NEXT: xscvqpdp v2, v2
+; CHECK-NEXT: stxsdx v2, r3, r4
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* getelementptr inbounds ([4 x fp128], [4 x fp128]* @f128Array, i64 0, i64 0), align 16
@@ -463,11 +463,11 @@ entry:
define void @qpConv2dp_04(fp128* nocapture readonly %a, fp128* nocapture readonly %b, double* nocapture %res) {
; CHECK-LABEL: qpConv2dp_04:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lxv 2, 0(3)
-; CHECK-NEXT: lxv 3, 0(4)
-; CHECK-NEXT: xsaddqp 2, 2, 3
-; CHECK-NEXT: xscvqpdp 2, 2
-; CHECK-NEXT: stxsd 2, 0(5)
+; CHECK-NEXT: lxv v2, 0(r3)
+; CHECK-NEXT: lxv v3, 0(r4)
+; CHECK-NEXT: xsaddqp v2, v2, v3
+; CHECK-NEXT: xscvqpdp v2, v2
+; CHECK-NEXT: stxsd v2, 0(r5)
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* %a, align 16
@@ -484,9 +484,9 @@ entry:
define float @qpConv2sp(fp128* nocapture readonly %a) {
; CHECK-LABEL: qpConv2sp:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lxv 2, 0(3)
-; CHECK-NEXT: xscvqpdpo 2, 2
-; CHECK-NEXT: xsrsp 1, 2
+; CHECK-NEXT: lxv v2, 0(r3)
+; CHECK-NEXT: xscvqpdpo v2, v2
+; CHECK-NEXT: xsrsp f1, v2
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* %a, align 16
@@ -498,12 +498,12 @@ entry:
define void @qpConv2sp_02(float* nocapture %res) {
; CHECK-LABEL: qpConv2sp_02:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis 4, 2, .LC6@toc@ha
-; CHECK-NEXT: ld 4, .LC6@toc@l(4)
-; CHECK-NEXT: lxvx 2, 0, 4
-; CHECK-NEXT: xscvqpdpo 2, 2
-; CHECK-NEXT: xsrsp 0, 2
-; CHECK-NEXT: stfs 0, 0(3)
+; CHECK-NEXT: addis r4, r2, .LC6@toc@ha
+; CHECK-NEXT: ld r4, .LC6@toc@l(r4)
+; CHECK-NEXT: lxvx v2, 0, r4
+; CHECK-NEXT: xscvqpdpo v2, v2
+; CHECK-NEXT: xsrsp f0, v2
+; CHECK-NEXT: stfs f0, 0(r3)
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* @f128global, align 16
@@ -516,13 +516,13 @@ entry:
define void @qpConv2sp_03(float* nocapture %res, i32 signext %idx) {
; CHECK-LABEL: qpConv2sp_03:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis 5, 2, .LC7@toc@ha
-; CHECK-NEXT: sldi 4, 4, 2
-; CHECK-NEXT: ld 5, .LC7@toc@l(5)
-; CHECK-NEXT: lxv 2, 48(5)
-; CHECK-NEXT: xscvqpdpo 2, 2
-; CHECK-NEXT: xsrsp 0, 2
-; CHECK-NEXT: stfsx 0, 3, 4
+; CHECK-NEXT: addis r5, r2, .LC7@toc@ha
+; CHECK-NEXT: sldi r4, r4, 2
+; CHECK-NEXT: ld r5, .LC7@toc@l(r5)
+; CHECK-NEXT: lxv v2, 48(r5)
+; CHECK-NEXT: xscvqpdpo v2, v2
+; CHECK-NEXT: xsrsp f0, v2
+; CHECK-NEXT: stfsx f0, r3, r4
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* getelementptr inbounds ([4 x fp128], [4 x fp128]* @f128Array, i64 0, i64 3), align 16
@@ -537,12 +537,12 @@ entry:
define void @qpConv2sp_04(fp128* nocapture readonly %a, fp128* nocapture readonly %b, float* nocapture %res) {
; CHECK-LABEL: qpConv2sp_04:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lxv 2, 0(3)
-; CHECK-NEXT: lxv 3, 0(4)
-; CHECK-NEXT: xsaddqp 2, 2, 3
-; CHECK-NEXT: xscvqpdpo 2, 2
-; CHECK-NEXT: xsrsp 0, 2
-; CHECK-NEXT: stfs 0, 0(5)
+; CHECK-NEXT: lxv v2, 0(r3)
+; CHECK-NEXT: lxv v3, 0(r4)
+; CHECK-NEXT: xsaddqp v2, v2, v3
+; CHECK-NEXT: xscvqpdpo v2, v2
+; CHECK-NEXT: xsrsp f0, v2
+; CHECK-NEXT: stfs f0, 0(r5)
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* %a, align 16
@@ -559,8 +559,8 @@ entry:
define fp128 @dpConv2qp(double %a) {
; CHECK-LABEL: dpConv2qp:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxlor 2, 1, 1
-; CHECK-NEXT: xscvdpqp 2, 2
+; CHECK-NEXT: xxlor v2, f1, f1
+; CHECK-NEXT: xscvdpqp v2, v2
; CHECK-NEXT: blr
entry:
%conv = fpext double %a to fp128
@@ -571,11 +571,11 @@ entry:
define void @dpConv2qp_02(double* nocapture readonly %a) {
; CHECK-LABEL: dpConv2qp_02:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lxsd 2, 0(3)
-; CHECK-NEXT: addis 3, 2, .LC8@toc@ha
-; CHECK-NEXT: ld 3, .LC8@toc@l(3)
-; CHECK-NEXT: xscvdpqp 2, 2
-; CHECK-NEXT: stxvx 2, 0, 3
+; CHECK-NEXT: lxsd v2, 0(r3)
+; CHECK-NEXT: addis r3, r2, .LC8@toc@ha
+; CHECK-NEXT: ld r3, .LC8@toc@l(r3)
+; CHECK-NEXT: xscvdpqp v2, v2
+; CHECK-NEXT: stxvx v2, 0, r3
; CHECK-NEXT: blr
entry:
%0 = load double, double* %a, align 8
@@ -588,12 +588,12 @@ entry:
define void @dpConv2qp_02b(double* nocapture readonly %a, i32 signext %idx) {
; CHECK-LABEL: dpConv2qp_02b:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sldi 4, 4, 3
-; CHECK-NEXT: lxsdx 2, 3, 4
-; CHECK-NEXT: addis 3, 2, .LC8@toc@ha
-; CHECK-NEXT: ld 3, .LC8@toc@l(3)
-; CHECK-NEXT: xscvdpqp 2, 2
-; CHECK-NEXT: stxvx 2, 0, 3
+; CHECK-NEXT: sldi r4, r4, 3
+; CHECK-NEXT: lxsdx v2, r3, r4
+; CHECK-NEXT: addis r3, r2, .LC8@toc@ha
+; CHECK-NEXT: ld r3, .LC8@toc@l(r3)
+; CHECK-NEXT: xscvdpqp v2, v2
+; CHECK-NEXT: stxvx v2, 0, r3
; CHECK-NEXT: blr
entry:
%idxprom = sext i32 %idx to i64
@@ -608,10 +608,10 @@ entry:
define void @dpConv2qp_03(fp128* nocapture %res, i32 signext %idx, double %a) {
; CHECK-LABEL: dpConv2qp_03:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxlor 2, 1, 1
-; CHECK-NEXT: sldi 4, 4, 4
-; CHECK-NEXT: xscvdpqp 2, 2
-; CHECK-NEXT: stxvx 2, 3, 4
+; CHECK-NEXT: xxlor v2, f1, f1
+; CHECK-NEXT: sldi r4, r4, 4
+; CHECK-NEXT: xscvdpqp v2, v2
+; CHECK-NEXT: stxvx v2, r3, r4
; CHECK-NEXT: blr
entry:
%conv = fpext double %a to fp128
@@ -625,9 +625,9 @@ entry:
define void @dpConv2qp_04(double %a, fp128* nocapture %res) {
; CHECK-LABEL: dpConv2qp_04:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxlor 2, 1, 1
-; CHECK-NEXT: xscvdpqp 2, 2
-; CHECK-NEXT: stxv 2, 0(4)
+; CHECK-NEXT: xxlor v2, f1, f1
+; CHECK-NEXT: xscvdpqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r4)
; CHECK-NEXT: blr
entry:
%conv = fpext double %a to fp128
@@ -639,8 +639,8 @@ entry:
define fp128 @spConv2qp(float %a) {
; CHECK-LABEL: spConv2qp:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxlor 2, 1, 1
-; CHECK-NEXT: xscvdpqp 2, 2
+; CHECK-NEXT: xxlor v2, f1, f1
+; CHECK-NEXT: xscvdpqp v2, v2
; CHECK-NEXT: blr
entry:
%conv = fpext float %a to fp128
@@ -651,11 +651,11 @@ entry:
define void @spConv2qp_02(float* nocapture readonly %a) {
; CHECK-LABEL: spConv2qp_02:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lxssp 2, 0(3)
-; CHECK-NEXT: addis 3, 2, .LC8@toc@ha
-; CHECK-NEXT: ld 3, .LC8@toc@l(3)
-; CHECK-NEXT: xscvdpqp 2, 2
-; CHECK-NEXT: stxvx 2, 0, 3
+; CHECK-NEXT: lxssp v2, 0(r3)
+; CHECK-NEXT: addis r3, r2, .LC8@toc@ha
+; CHECK-NEXT: ld r3, .LC8@toc@l(r3)
+; CHECK-NEXT: xscvdpqp v2, v2
+; CHECK-NEXT: stxvx v2, 0, r3
; CHECK-NEXT: blr
entry:
%0 = load float, float* %a, align 4
@@ -668,12 +668,12 @@ entry:
define void @spConv2qp_02b(float* nocapture readonly %a, i32 signext %idx) {
; CHECK-LABEL: spConv2qp_02b:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sldi 4, 4, 2
-; CHECK-NEXT: lxsspx 2, 3, 4
-; CHECK-NEXT: addis 3, 2, .LC8@toc@ha
-; CHECK-NEXT: ld 3, .LC8@toc@l(3)
-; CHECK-NEXT: xscvdpqp 2, 2
-; CHECK-NEXT: stxvx 2, 0, 3
+; CHECK-NEXT: sldi r4, r4, 2
+; CHECK-NEXT: lxsspx v2, r3, r4
+; CHECK-NEXT: addis r3, r2, .LC8@toc@ha
+; CHECK-NEXT: ld r3, .LC8@toc@l(r3)
+; CHECK-NEXT: xscvdpqp v2, v2
+; CHECK-NEXT: stxvx v2, 0, r3
; CHECK-NEXT: blr
entry:
%idxprom = sext i32 %idx to i64
@@ -688,10 +688,10 @@ entry:
define void @spConv2qp_03(fp128* nocapture %res, i32 signext %idx, float %a) {
; CHECK-LABEL: spConv2qp_03:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxlor 2, 1, 1
-; CHECK-NEXT: sldi 4, 4, 4
-; CHECK-NEXT: xscvdpqp 2, 2
-; CHECK-NEXT: stxvx 2, 3, 4
+; CHECK-NEXT: xxlor v2, f1, f1
+; CHECK-NEXT: sldi r4, r4, 4
+; CHECK-NEXT: xscvdpqp v2, v2
+; CHECK-NEXT: stxvx v2, r3, r4
; CHECK-NEXT: blr
entry:
%conv = fpext float %a to fp128
@@ -705,9 +705,9 @@ entry:
define void @spConv2qp_04(float %a, fp128* nocapture %res) {
; CHECK-LABEL: spConv2qp_04:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxlor 2, 1, 1
-; CHECK-NEXT: xscvdpqp 2, 2
-; CHECK-NEXT: stxv 2, 0(4)
+; CHECK-NEXT: xxlor v2, f1, f1
+; CHECK-NEXT: xscvdpqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r4)
; CHECK-NEXT: blr
entry:
%conv = fpext float %a to fp128
@@ -721,10 +721,10 @@ entry:
define void @cvdp2sw2qp(double %val, fp128* nocapture %res) {
; CHECK-LABEL: cvdp2sw2qp:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xscvdpsxws 2, 1
-; CHECK-NEXT: vextsw2d 2, 2
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 2, 0(4)
+; CHECK-NEXT: xscvdpsxws v2, f1
+; CHECK-NEXT: vextsw2d v2, v2
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r4)
; CHECK-NEXT: blr
entry:
%conv = fptosi double %val to i32
@@ -737,9 +737,9 @@ entry:
define void @cvdp2sdw2qp(double %val, fp128* nocapture %res) {
; CHECK-LABEL: cvdp2sdw2qp:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xscvdpsxds 2, 1
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 2, 0(4)
+; CHECK-NEXT: xscvdpsxds v2, f1
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r4)
; CHECK-NEXT: blr
entry:
%conv = fptosi double %val to i64
@@ -752,10 +752,10 @@ entry:
define void @cvsp2sw2qp(float %val, fp128* nocapture %res) {
; CHECK-LABEL: cvsp2sw2qp:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xscvdpsxws 2, 1
-; CHECK-NEXT: vextsw2d 2, 2
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 2, 0(4)
+; CHECK-NEXT: xscvdpsxws v2, f1
+; CHECK-NEXT: vextsw2d v2, v2
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r4)
; CHECK-NEXT: blr
entry:
%conv = fptosi float %val to i32
@@ -768,9 +768,9 @@ entry:
define void @cvsp2sdw2qp(float %val, fp128* nocapture %res) {
; CHECK-LABEL: cvsp2sdw2qp:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xscvdpsxds 2, 1
-; CHECK-NEXT: xscvsdqp 2, 2
-; CHECK-NEXT: stxv 2, 0(4)
+; CHECK-NEXT: xscvdpsxds v2, f1
+; CHECK-NEXT: xscvsdqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r4)
; CHECK-NEXT: blr
entry:
%conv = fptosi float %val to i64
@@ -783,10 +783,10 @@ entry:
define void @cvdp2uw2qp(double %val, fp128* nocapture %res) {
; CHECK-LABEL: cvdp2uw2qp:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xscvdpuxws 0, 1
-; CHECK-NEXT: xxextractuw 2, 0, 8
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 2, 0(4)
+; CHECK-NEXT: xscvdpuxws f0, f1
+; CHECK-NEXT: xxextractuw v2, vs0, 8
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r4)
; CHECK-NEXT: blr
entry:
%conv = fptoui double %val to i32
@@ -799,9 +799,9 @@ entry:
define void @cvdp2udw2qp(double %val, fp128* nocapture %res) {
; CHECK-LABEL: cvdp2udw2qp:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xscvdpuxds 2, 1
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 2, 0(4)
+; CHECK-NEXT: xscvdpuxds v2, f1
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r4)
; CHECK-NEXT: blr
entry:
%conv = fptoui double %val to i64
@@ -814,10 +814,10 @@ entry:
define void @cvsp2uw2qp(float %val, fp128* nocapture %res) {
; CHECK-LABEL: cvsp2uw2qp:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xscvdpuxws 0, 1
-; CHECK-NEXT: xxextractuw 2, 0, 8
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 2, 0(4)
+; CHECK-NEXT: xscvdpuxws f0, f1
+; CHECK-NEXT: xxextractuw v2, vs0, 8
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r4)
; CHECK-NEXT: blr
entry:
%conv = fptoui float %val to i32
@@ -830,9 +830,9 @@ entry:
define void @cvsp2udw2qp(float %val, fp128* nocapture %res) {
; CHECK-LABEL: cvsp2udw2qp:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xscvdpuxds 2, 1
-; CHECK-NEXT: xscvudqp 2, 2
-; CHECK-NEXT: stxv 2, 0(4)
+; CHECK-NEXT: xscvdpuxds v2, f1
+; CHECK-NEXT: xscvudqp v2, v2
+; CHECK-NEXT: stxv v2, 0(r4)
; CHECK-NEXT: blr
entry:
%conv = fptoui float %val to i64
OpenPOWER on IntegriCloud