diff options
Diffstat (limited to 'llvm/test/CodeGen/PowerPC/f128-aggregates.ll')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/f128-aggregates.ll | 178 |
1 files changed, 90 insertions, 88 deletions
diff --git a/llvm/test/CodeGen/PowerPC/f128-aggregates.ll b/llvm/test/CodeGen/PowerPC/f128-aggregates.ll index fb2700e1c61..8c934ba6586 100644 --- a/llvm/test/CodeGen/PowerPC/f128-aggregates.ll +++ b/llvm/test/CodeGen/PowerPC/f128-aggregates.ll @@ -1,7 +1,9 @@ ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \ -; RUN: -enable-ppc-quad-precision -verify-machineinstrs < %s | FileCheck %s +; RUN: -enable-ppc-quad-precision -verify-machineinstrs \ +; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown \ -; RUN: -enable-ppc-quad-precision -verify-machineinstrs < %s \ +; RUN: -enable-ppc-quad-precision -verify-machineinstrs \ +; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \ ; RUN: | FileCheck -check-prefix=CHECK-BE %s ; Testing homogeneous aggregates. @@ -15,11 +17,11 @@ define fp128 @testArray_01(fp128* nocapture readonly %sa) { ; CHECK-LABEL: testArray_01: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: lxv 34, 32(3) +; CHECK-NEXT: lxv v2, 32(r3) ; CHECK-NEXT: blr ; CHECK-BE-LABEL: testArray_01: -; CHECK-BE: lxv 34, 32(3) +; CHECK-BE: lxv v2, 32(r3) ; CHECK-BE-NEXT: blr entry: %arrayidx = getelementptr inbounds fp128, fp128* %sa, i64 2 @@ -31,13 +33,13 @@ entry: define fp128 @testArray_02() { ; CHECK-LABEL: testArray_02: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis 3, 2, .LC0@toc@ha -; CHECK-NEXT: ld 3, .LC0@toc@l(3) -; CHECK-NEXT: lxv 34, 32(3) +; CHECK-NEXT: addis r3, r2, .LC0@toc@ha +; CHECK-NEXT: ld r3, .LC0@toc@l(r3) +; CHECK-NEXT: lxv v2, 32(r3) ; CHECK-NEXT: blr ; CHECK-BE-LABEL: testArray_02: -; CHECK-BE: lxv 34, 32(3) +; CHECK-BE: lxv v2, 32(r3) ; CHECK-BE-NEXT: blr entry: %0 = load fp128, fp128* getelementptr inbounds ([3 x fp128], [3 x fp128]* @a1, @@ -62,11 +64,11 @@ entry: define fp128 @testStruct_02([8 x fp128] %a.coerce) { ; CHECK-LABEL: testStruct_02: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmr 2, 9 +; CHECK-NEXT: vmr v2, v9 ; CHECK-NEXT: blr ; CHECK-BE-LABEL: testStruct_02: -; CHECK-BE: vmr 2, 9 +; CHECK-BE: vmr v2, v9 ; CHECK-BE-NEXT: blr entry: %a.coerce.fca.7.extract = extractvalue [8 x fp128] %a.coerce, 7 @@ -80,28 +82,28 @@ define fp128 @testStruct_03(%struct.With9fp128params* byval nocapture readonly align 16 %a) { ; CHECK-LABEL: testStruct_03: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: lxv 34, 128(1) -; CHECK-NEXT: std 10, 88(1) -; CHECK-NEXT: std 9, 80(1) -; CHECK-NEXT: std 8, 72(1) -; CHECK-NEXT: std 7, 64(1) -; CHECK-NEXT: std 6, 56(1) -; CHECK-NEXT: std 5, 48(1) -; CHECK-NEXT: std 4, 40(1) -; CHECK-NEXT: std 3, 32(1) +; CHECK-NEXT: lxv v2, 128(r1) +; CHECK-NEXT: std r10, 88(r1) +; CHECK-NEXT: std r9, 80(r1) +; CHECK-NEXT: std r8, 72(r1) +; CHECK-NEXT: std r7, 64(r1) +; CHECK-NEXT: std r6, 56(r1) +; CHECK-NEXT: std r5, 48(r1) +; CHECK-NEXT: std r4, 40(r1) +; CHECK-NEXT: std r3, 32(r1) ; CHECK-NEXT: blr ; CHECK-BE-LABEL: testStruct_03: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: lxv 34, 144(1) -; CHECK-BE-NEXT: std 10, 104(1) -; CHECK-BE-NEXT: std 9, 96(1) -; CHECK-BE-NEXT: std 8, 88(1) -; CHECK-BE-NEXT: std 7, 80(1) -; CHECK-BE-NEXT: std 6, 72(1) -; CHECK-BE-NEXT: std 5, 64(1) -; CHECK-BE-NEXT: std 4, 56(1) -; CHECK-BE-NEXT: std 3, 48(1) +; CHECK-BE-NEXT: lxv v2, 144(r1) +; CHECK-BE-NEXT: std r10, 104(r1) +; CHECK-BE-NEXT: std r9, 96(r1) +; CHECK-BE-NEXT: std r8, 88(r1) +; CHECK-BE-NEXT: std r7, 80(r1) +; CHECK-BE-NEXT: std r6, 72(r1) +; CHECK-BE-NEXT: std r5, 64(r1) +; CHECK-BE-NEXT: std r4, 56(r1) +; CHECK-BE-NEXT: std r3, 48(r1) ; CHECK-BE-NEXT: blr entry: %a7 = getelementptr inbounds %struct.With9fp128params, @@ -114,11 +116,11 @@ entry: define fp128 @testStruct_04([8 x fp128] %a.coerce) { ; CHECK-LABEL: testStruct_04: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmr 2, 5 +; CHECK-NEXT: vmr v2, v5 ; CHECK-NEXT: blr ; CHECK-BE-LABEL: testStruct_04: -; CHECK-BE: vmr 2, 5 +; CHECK-BE: vmr v2, v5 ; CHECK-BE-NEXT: blr entry: %a.coerce.fca.3.extract = extractvalue [8 x fp128] %a.coerce, 3 @@ -157,12 +159,12 @@ entry: define fp128 @testHUnion_03([3 x fp128] %a.coerce) { ; CHECK-LABEL: testHUnion_03: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmr 2, 3 +; CHECK-NEXT: vmr v2, v3 ; CHECK-NEXT: blr ; CHECK-BE-LABEL: testHUnion_03: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vmr 2, 3 +; CHECK-BE-NEXT: vmr v2, v3 ; CHECK-BE-NEXT: blr entry: %a.coerce.fca.1.extract = extractvalue [3 x fp128] %a.coerce, 1 @@ -173,12 +175,12 @@ entry: define fp128 @testHUnion_04([3 x fp128] %a.coerce) { ; CHECK-LABEL: testHUnion_04: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vmr 2, 4 +; CHECK-NEXT: vmr v2, v4 ; CHECK-NEXT: blr ; CHECK-BE-LABEL: testHUnion_04: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vmr 2, 4 +; CHECK-BE-NEXT: vmr v2, v4 ; CHECK-BE-NEXT: blr entry: %a.coerce.fca.2.extract = extractvalue [3 x fp128] %a.coerce, 2 @@ -194,11 +196,11 @@ entry: define fp128 @testMixedAggregate([3 x i128] %a.coerce) { ; CHECK-LABEL: testMixedAggregate: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: mtvsrdd 34, 8, 7 +; CHECK-NEXT: mtvsrdd v2, r8, r7 ; CHECK-NEXT: blr ; CHECK-BE-LABEL: testMixedAggregate: -; CHECK-BE: mtvsrdd 34, 8, 7 +; CHECK-BE: mtvsrdd v2, r8, r7 ; CHECK-BE-NEXT: blr entry: %a.coerce.fca.2.extract = extractvalue [3 x i128] %a.coerce, 2 @@ -210,11 +212,11 @@ entry: define fp128 @testMixedAggregate_02([4 x i128] %a.coerce) { ; CHECK-LABEL: testMixedAggregate_02: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: mtvsrdd 34, 6, 5 +; CHECK-NEXT: mtvsrdd v2, r6, r5 ; CHECK-NEXT: blr ; CHECK-BE-LABEL: testMixedAggregate_02: -; CHECK-BE: mtvsrdd 34, 6, 5 +; CHECK-BE: mtvsrdd v2, r6, r5 ; CHECK-BE-NEXT: blr entry: %a.coerce.fca.1.extract = extractvalue [4 x i128] %a.coerce, 1 @@ -226,13 +228,13 @@ entry: define fp128 @testMixedAggregate_03([4 x i128] %sa.coerce) { ; CHECK-LABEL: testMixedAggregate_03: ; CHECK: # %bb.0: # %entry -; CHECK-DAG: mtvsrwa 34, 3 -; CHECK-DAG: mtvsrdd 35, 6, 5 -; CHECK: mtvsrd 36, 10 -; CHECK: xscvsdqp 2, 2 -; CHECK-DAG: xscvsdqp [[REG:[0-9]+]], 4 -; CHECK-DAG: xsaddqp 2, 3, 2 -; CHECK: xsaddqp 2, 2, [[REG]] +; CHECK-DAG: mtvsrwa v2, r3 +; CHECK-DAG: mtvsrdd v3, r6, r5 +; CHECK: mtvsrd v4, r10 +; CHECK: xscvsdqp v2, v2 +; CHECK-DAG: xscvsdqp v[[REG:[0-9]+]], v4 +; CHECK-DAG: xsaddqp v2, v3, v2 +; CHECK: xsaddqp v2, v2, v[[REG]] ; CHECK-NEXT: blr entry: %sa.coerce.fca.0.extract = extractvalue [4 x i128] %sa.coerce, 0 @@ -254,28 +256,28 @@ entry: define fp128 @testNestedAggregate(%struct.MixedC* byval nocapture readonly align 16 %a) { ; CHECK-LABEL: testNestedAggregate: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: std 8, 72(1) -; CHECK-NEXT: std 7, 64(1) -; CHECK-NEXT: std 10, 88(1) -; CHECK-NEXT: std 9, 80(1) -; CHECK-NEXT: lxv 34, 64(1) -; CHECK-NEXT: std 6, 56(1) -; CHECK-NEXT: std 5, 48(1) -; CHECK-NEXT: std 4, 40(1) -; CHECK-NEXT: std 3, 32(1) +; CHECK-NEXT: std r8, 72(r1) +; CHECK-NEXT: std r7, 64(r1) +; CHECK-NEXT: std r10, 88(r1) +; CHECK-NEXT: std r9, 80(r1) +; CHECK-NEXT: lxv v2, 64(r1) +; CHECK-NEXT: std r6, 56(r1) +; CHECK-NEXT: std r5, 48(r1) +; CHECK-NEXT: std r4, 40(r1) +; CHECK-NEXT: std r3, 32(r1) ; CHECK-NEXT: blr ; CHECK-BE-LABEL: testNestedAggregate: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: std 8, 88(1) -; CHECK-BE-NEXT: std 7, 80(1) -; CHECK-BE-NEXT: std 10, 104(1) -; CHECK-BE-NEXT: std 9, 96(1) -; CHECK-BE-NEXT: lxv 34, 80(1) -; CHECK-BE-NEXT: std 6, 72(1) -; CHECK-BE-NEXT: std 5, 64(1) -; CHECK-BE-NEXT: std 4, 56(1) -; CHECK-BE-NEXT: std 3, 48(1) +; CHECK-BE-NEXT: std r8, 88(r1) +; CHECK-BE-NEXT: std r7, 80(r1) +; CHECK-BE-NEXT: std r10, 104(r1) +; CHECK-BE-NEXT: std r9, 96(r1) +; CHECK-BE-NEXT: lxv v2, 80(r1) +; CHECK-BE-NEXT: std r6, 72(r1) +; CHECK-BE-NEXT: std r5, 64(r1) +; CHECK-BE-NEXT: std r4, 56(r1) +; CHECK-BE-NEXT: std r3, 48(r1) ; CHECK-BE-NEXT: blr entry: %c = getelementptr inbounds %struct.MixedC, %struct.MixedC* %a, i64 0, i32 1, i32 1 @@ -287,11 +289,11 @@ entry: define fp128 @testUnion_01([1 x i128] %a.coerce) { ; CHECK-LABEL: testUnion_01: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: mtvsrdd 34, 4, 3 +; CHECK-NEXT: mtvsrdd v2, r4, r3 ; CHECK-NEXT: blr ; CHECK-BE-LABEL: testUnion_01: -; CHECK-BE: mtvsrdd 34, 4, 3 +; CHECK-BE: mtvsrdd v2, r4, r3 ; CHECK-BE-NEXT: blr entry: %a.coerce.fca.0.extract = extractvalue [1 x i128] %a.coerce, 0 @@ -303,11 +305,11 @@ entry: define fp128 @testUnion_02([1 x i128] %a.coerce) { ; CHECK-LABEL: testUnion_02: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: mtvsrdd 34, 4, 3 +; CHECK-NEXT: mtvsrdd v2, r4, r3 ; CHECK-NEXT: blr ; CHECK-BE-LABEL: testUnion_02: -; CHECK-BE: mtvsrdd 34, 4, 3 +; CHECK-BE: mtvsrdd v2, r4, r3 ; CHECK-BE-NEXT: blr entry: %a.coerce.fca.0.extract = extractvalue [1 x i128] %a.coerce, 0 @@ -319,11 +321,11 @@ entry: define fp128 @testUnion_03([4 x i128] %a.coerce) { ; CHECK-LABEL: testUnion_03: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: mtvsrdd 34, 8, 7 +; CHECK-NEXT: mtvsrdd v2, r8, r7 ; CHECK-NEXT: blr ; CHECK-BE-LABEL: testUnion_03: -; CHECK-BE: mtvsrdd 34, 8, 7 +; CHECK-BE: mtvsrdd v2, r8, r7 ; CHECK-BE-NEXT: blr entry: %a.coerce.fca.2.extract = extractvalue [4 x i128] %a.coerce, 2 @@ -335,26 +337,26 @@ entry: define fp128 @sum_float128(i32 signext %count, ...) { ; CHECK-LABEL: sum_float128: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis 11, 2, .LCPI17_0@toc@ha -; CHECK-NEXT: cmpwi 0, 3, 1 -; CHECK-NEXT: std 10, 88(1) -; CHECK-NEXT: std 9, 80(1) -; CHECK-NEXT: std 8, 72(1) -; CHECK-NEXT: std 7, 64(1) -; CHECK-NEXT: std 6, 56(1) -; CHECK-NEXT: std 5, 48(1) -; CHECK-NEXT: std 4, 40(1) -; CHECK-NEXT: addi 11, 11, .LCPI17_0@toc@l -; CHECK-NEXT: lxvx 34, 0, 11 -; CHECK-NEXT: bltlr 0 +; CHECK-NEXT: addis r11, r2, .LCPI17_0@toc@ha +; CHECK-NEXT: cmpwi cr0, r3, 1 +; CHECK-NEXT: std r10, 88(r1) +; CHECK-NEXT: std r9, 80(r1) +; CHECK-NEXT: std r8, 72(r1) +; CHECK-NEXT: std r7, 64(r1) +; CHECK-NEXT: std r6, 56(r1) +; CHECK-NEXT: std r5, 48(r1) +; CHECK-NEXT: std r4, 40(r1) +; CHECK-NEXT: addi r11, r11, .LCPI17_0@toc@l +; CHECK-NEXT: lxvx v2, 0, r11 +; CHECK-NEXT: bltlr cr0 ; CHECK-NEXT: # %bb.1: # %if.end -; CHECK-NEXT: addi 3, 1, 40 -; CHECK-NEXT: lxvx 35, 0, 3 -; CHECK-NEXT: xsaddqp 2, 3, 2 -; CHECK-NEXT: lxv 35, 16(3) -; CHECK-NEXT: addi 3, 1, 72 -; CHECK-NEXT: std 3, -8(1) -; CHECK-NEXT: xsaddqp 2, 2, 3 +; CHECK-NEXT: addi r3, r1, 40 +; CHECK-NEXT: lxvx v3, 0, r3 +; CHECK-NEXT: xsaddqp v2, v3, v2 +; CHECK-NEXT: lxv v3, 16(r3) +; CHECK-NEXT: addi r3, r1, 72 +; CHECK-NEXT: std r3, -8(r1) +; CHECK-NEXT: xsaddqp v2, v2, v3 ; CHECK-NEXT: blr entry: %ap = alloca i8*, align 8 |
