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-rw-r--r--llvm/test/CodeGen/Mips/llvm-ir/add.ll35
-rw-r--r--llvm/test/CodeGen/Mips/llvm-ir/and.ll46
-rw-r--r--llvm/test/CodeGen/Mips/llvm-ir/lh_lhu.ll1
-rw-r--r--llvm/test/CodeGen/Mips/llvm-ir/mul.ll22
-rw-r--r--llvm/test/CodeGen/Mips/llvm-ir/not.ll21
-rw-r--r--llvm/test/CodeGen/Mips/llvm-ir/or.ll46
-rw-r--r--llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll7
-rw-r--r--llvm/test/CodeGen/Mips/llvm-ir/srem.ll7
-rw-r--r--llvm/test/CodeGen/Mips/llvm-ir/sub.ll12
-rw-r--r--llvm/test/CodeGen/Mips/llvm-ir/udiv.ll7
-rw-r--r--llvm/test/CodeGen/Mips/llvm-ir/urem.ll7
-rw-r--r--llvm/test/CodeGen/Mips/llvm-ir/xor.ll21
12 files changed, 0 insertions, 232 deletions
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/add.ll b/llvm/test/CodeGen/Mips/llvm-ir/add.ll
index 63884eb03b8..2a7ae5a7153 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/add.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/add.ll
@@ -28,8 +28,6 @@
; RUN: -check-prefixes=ALL,MMR3,MM32
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -O2 | FileCheck %s \
; RUN: -check-prefixes=ALL,MMR6,MM32
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -O2 | FileCheck %s \
-; RUN: -check-prefixes=ALL,MM64
; FIXME: This code sequence is inefficient as it should be 'subu $[[T0]], $zero, $[[T0]'.
@@ -122,8 +120,6 @@ entry:
; MM32: sltu $[[T1:[0-9]+]], $3, $5
; MM32: addu16 $2, $[[T0]], $[[T1]]
- ; MM64: daddu $2, $4, $5
-
%r = add i64 %a, %b
ret i64 %r
}
@@ -228,13 +224,6 @@ entry:
; MMR6: addu16 $2, $[[T16]], $[[T20]]
; MMR6: addu16 $2, $[[T20]], $[[T21]]
- ; MM64: daddu $[[T0:[0-9]+]], $4, $6
- ; MM64: daddu $3, $5, $7
- ; MM64: sltu $[[T1:[0-9]+]], $3, $5
- ; MM64: dsll $[[T2:[0-9]+]], $[[T1]], 32
- ; MM64: dsrl $[[T3:[0-9]+]], $[[T2]], 32
- ; MM64: daddu $2, $[[T0]], $[[T3]]
-
%r = add i128 %a, %b
ret i128 %r
}
@@ -262,9 +251,6 @@ define signext i8 @add_i8_4(i8 signext %a) {
; MM32: addiur2 $[[T0:[0-9]+]], $4, 4
; MM32: seb $2, $[[T0]]
- ; MM64: addiur2 $[[T0:[0-9]+]], $4, 4
- ; MM64: seb $2, $[[T0]]
-
%r = add i8 4, %a
ret i8 %r
}
@@ -283,9 +269,6 @@ define signext i16 @add_i16_4(i16 signext %a) {
; MM32: addiur2 $[[T0:[0-9]+]], $4, 4
; MM32: seh $2, $[[T0]]
- ; MM64: addiur2 $[[T0:[0-9]+]], $4, 4
- ; MM64: seh $2, $[[T0]]
-
%r = add i16 4, %a
ret i16 %r
}
@@ -299,8 +282,6 @@ define signext i32 @add_i32_4(i32 signext %a) {
; MM32: addiur2 $2, $4, 4
- ; MM64: addiur2 $2, $4, 4
-
%r = add i32 4, %a
ret i32 %r
}
@@ -319,8 +300,6 @@ define signext i64 @add_i64_4(i64 signext %a) {
; GP64: daddiu $2, $4, 4
- ; MM64: daddiu $2, $4, 4
-
%r = add i64 4, %a
ret i64 %r
}
@@ -384,12 +363,6 @@ define signext i128 @add_i128_4(i128 signext %a) {
; MMR6: move $4, $7
; MMR6: move $5, $[[T1]]
- ; MM64: daddiu $[[T0:[0-9]+]], $5, 4
- ; MM64: sltu $[[T1:[0-9]+]], $[[T0]], $5
- ; MM64: dsll $[[T2:[0-9]+]], $[[T1]], 32
- ; MM64: dsrl $[[T3:[0-9]+]], $[[T2]], 32
- ; MM64: daddu $2, $4, $[[T3]]
-
%r = add i128 4, %a
ret i128 %r
}
@@ -477,8 +450,6 @@ define signext i64 @add_i64_3(i64 signext %a) {
; MM32: sltu $[[T2:[0-9]+]], $[[T1]], $5
; MM32: addu16 $2, $4, $[[T2]]
- ; MM64: daddiu $2, $4, 3
-
%r = add i64 3, %a
ret i64 %r
}
@@ -545,12 +516,6 @@ define signext i128 @add_i128_3(i128 signext %a) {
; MMR6: move $4, $[[T5]]
; MMR6: move $5, $[[T1]]
- ; MM64: daddiu $[[T0:[0-9]+]], $5, 3
- ; MM64: sltu $[[T1:[0-9]+]], $[[T0]], $5
- ; MM64: dsll $[[T2:[0-9]+]], $[[T1]], 32
- ; MM64: dsrl $[[T3:[0-9]+]], $[[T2]], 32
- ; MM64: daddu $2, $4, $[[T3]]
-
%r = add i128 3, %a
ret i128 %r
}
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/and.ll b/llvm/test/CodeGen/Mips/llvm-ir/and.ll
index 18d7a439f62..9ea810dfcbf 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/and.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/and.ll
@@ -28,8 +28,6 @@
; RUN: -check-prefixes=ALL,MM,MM32
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
; RUN: -check-prefixes=ALL,MM,MM32
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \
-; RUN: -check-prefixes=ALL,MM,MM64
define signext i1 @and_i1(i1 signext %a, i1 signext %b) {
entry:
@@ -42,8 +40,6 @@ entry:
; MM32: and16 $[[T0:[0-9]+]], $5
; MM32: move $2, $[[T0]]
- ; MM64: and $1, $4, $5
-
%r = and i1 %a, %b
ret i1 %r
}
@@ -59,8 +55,6 @@ entry:
; MM32: and16 $[[T0:[0-9]+]], $5
; MM32: move $2, $[[T0]]
- ; MM64: and $1, $4, $5
-
%r = and i8 %a, %b
ret i8 %r
}
@@ -76,8 +70,6 @@ entry:
; MM32: and16 $[[T0:[0-9]+]], $5
; MM32 move $2, $[[T0]]
- ; MM64: and $1, $4, $5
-
%r = and i16 %a, %b
ret i16 %r
}
@@ -94,9 +86,6 @@ entry:
; MM32: and16 $[[T0:[0-9]+]], $5
; MM32: move $2, $[[T0]]
- ; MM64: and $[[T0:[0-9]+]], $4, $5
- ; MM64: sll $2, $[[T0]], 0
-
%r = and i32 %a, %b
ret i32 %r
}
@@ -115,8 +104,6 @@ entry:
; MM32: move $2, $[[T0]]
; MM32: move $3, $[[T1]]
- ; MM64: and $2, $4, $5
-
%r = and i64 %a, %b
ret i64 %r
}
@@ -146,9 +133,6 @@ entry:
; MM32: lw $[[T3:[0-9]+]], 28($sp)
; MM32: and16 $[[T3]], $7
- ; MM64: and $2, $4, $6
- ; MM64: and $3, $5, $7
-
%r = and i128 %a, %b
ret i128 %r
}
@@ -221,8 +205,6 @@ entry:
; MM32: andi16 $3, $5, 4
; MM32: li16 $2, 0
- ; MM64: andi $2, $4, 4
-
%r = and i64 4, %b
ret i64 %r
}
@@ -244,9 +226,6 @@ entry:
; MM32: li16 $3, 0
; MM32: li16 $4, 0
- ; MM64: andi $3, $5, 4
- ; MM64: daddiu $2, $zero, 0
-
%r = and i128 4, %b
ret i128 %r
}
@@ -315,8 +294,6 @@ entry:
; MM32: andi16 $3, $5, 31
; MM32: li16 $2, 0
- ; MM64: andi $2, $4, 31
-
%r = and i64 31, %b
ret i64 %r
}
@@ -338,9 +315,6 @@ entry:
; MM32: li16 $3, 0
; MM32: li16 $4, 0
- ; MM64: andi $3, $5, 31
- ; MM64: daddiu $2, $zero, 0
-
%r = and i128 31, %b
ret i128 %r
}
@@ -405,8 +379,6 @@ entry:
; MM32: andi16 $3, $5, 255
; MM32: li16 $2, 0
- ; MM64: andi $2, $4, 255
-
%r = and i64 255, %b
ret i64 %r
}
@@ -428,9 +400,6 @@ entry:
; MM32: li16 $3, 0
; MM32: li16 $4, 0
- ; MM64: andi $3, $5, 255
- ; MM64: daddiu $2, $zero, 0
-
%r = and i128 255, %b
ret i128 %r
}
@@ -506,8 +475,6 @@ entry:
; MM32: andi16 $3, $5, 32768
; MM32: li16 $2, 0
- ; MM64: andi $2, $4, 32768
-
%r = and i64 32768, %b
ret i64 %r
}
@@ -529,9 +496,6 @@ entry:
; MM32: li16 $3, 0
; MM32: li16 $4, 0
- ; MM64: andi $3, $5, 32768
- ; MM64: daddiu $2, $zero, 0
-
%r = and i128 32768, %b
ret i128 %r
}
@@ -588,8 +552,6 @@ entry:
; MM32-DAG: andi $3, $5, 65
; MM32-DAG: li16 $2, 0
- ; MM64: andi $2, $4, 65
-
%r = and i64 65, %b
ret i64 %r
}
@@ -611,9 +573,6 @@ entry:
; MM32-DAG: li16 $3, 0
; MM32-DAG: li16 $4, 0
- ; MM64: andi $3, $5, 65
- ; MM64: daddiu $2, $zero, 0
-
%r = and i128 65, %b
ret i128 %r
}
@@ -678,8 +637,6 @@ entry:
; MM32-DAG: andi $3, $5, 256
; MM32-DAG: li16 $2, 0
- ; MM64: andi $2, $4, 256
-
%r = and i64 256, %b
ret i64 %r
}
@@ -701,9 +658,6 @@ entry:
; MM32-DAG: li16 $3, 0
; MM32-DAG: li16 $4, 0
- ; MM64: andi $3, $5, 256
- ; MM64: daddiu $2, $zero, 0
-
%r = and i128 256, %b
ret i128 %r
}
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/lh_lhu.ll b/llvm/test/CodeGen/Mips/llvm-ir/lh_lhu.ll
index fadcfdb0fb4..192e10ae8fc 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/lh_lhu.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/lh_lhu.ll
@@ -1,7 +1,6 @@
; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+micromips -relocation-model=pic | FileCheck %s
; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -relocation-model=pic | FileCheck %s
@us = global i16 0, align 2
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/mul.ll b/llvm/test/CodeGen/Mips/llvm-ir/mul.ll
index 1562372ce9a..5e85ecf2a93 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/mul.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/mul.ll
@@ -26,8 +26,6 @@
; RUN: FileCheck %s -check-prefixes=MM32,MM32R3
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | \
; RUN: FileCheck %s -check-prefixes=MM32,MM32R6
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic | \
-; RUN: FileCheck %s -check-prefix=MM64R6
define signext i1 @mul_i1(i1 signext %a, i1 signext %b) {
entry:
@@ -59,11 +57,6 @@ entry:
; 64R6: andi $[[T0]], $[[T0]], 1
; 64R6: negu $2, $[[T0]]
- ; MM64R6: mul $[[T0:[0-9]+]], $4, $5
- ; MM64R6: andi16 $[[T0]], $[[T0]], 1
- ; MM64R6: li16 $[[T1:[0-9]+]], 0
- ; MM64R6: subu16 $2, $[[T1]], $[[T0]]
-
; MM32: mul $[[T0:[0-9]+]], $4, $5
; MM32: andi16 $[[T0]], $[[T0]], 1
; MM32: li16 $[[T1:[0-9]+]], 0
@@ -107,9 +100,6 @@ entry:
; 64R6: mul $[[T0:[0-9]+]], $4, $5
; 64R6: seb $2, $[[T0]]
- ; MM64R6: mul $[[T0:[0-9]+]], $4, $5
- ; MM64R6: seb $2, $[[T0]]
-
; MM32: mul $[[T0:[0-9]+]], $4, $5
; MM32: seb $2, $[[T0]]
@@ -151,9 +141,6 @@ entry:
; 64R6: mul $[[T0:[0-9]+]], $4, $5
; 64R6: seh $2, $[[T0]]
- ; MM64R6: mul $[[T0:[0-9]+]], $4, $5
- ; MM64R6: seh $2, $[[T0]]
-
; MM32: mul $[[T0:[0-9]+]], $4, $5
; MM32: seh $2, $[[T0]]
@@ -173,7 +160,6 @@ entry:
; 64R1-R5: mul $2, $4, $5
; 64R6: mul $2, $4, $5
- ; MM64R6: mul $2, $4, $5
; MM32: mul $2, $4, $5
@@ -217,7 +203,6 @@ entry:
; 64R1-R5: mflo $2
; 64R6: dmul $2, $4, $5
- ; MM64R6: dmul $2, $4, $5
; MM32R3: multu $[[T0:[0-9]+]], $7
; MM32R3: mflo $[[T1:[0-9]+]]
@@ -261,13 +246,6 @@ entry:
; 64R6: daddu $2, $[[T1]], $[[T0]]
; 64R6-DAG: dmul $3, $5, $7
- ; MM64R6-DAG: dmul $[[T1:[0-9]+]], $5, $6
- ; MM64R6: dmuhu $[[T2:[0-9]+]], $5, $7
- ; MM64R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]]
- ; MM64R6-DAG: dmul $[[T0:[0-9]+]], $4, $7
- ; MM64R6: daddu $2, $[[T1]], $[[T0]]
- ; MM64R6-DAG: dmul $3, $5, $7
-
; MM32: lw $25, %call16(__multi3)($16)
%r = mul i128 %a, %b
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/not.ll b/llvm/test/CodeGen/Mips/llvm-ir/not.ll
index ab7a3c4613a..6a27612c0e2 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/not.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/not.ll
@@ -26,8 +26,6 @@
; RUN: -check-prefixes=ALL,MM,MM32
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
; RUN: -check-prefixes=ALL,MM,MM32
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \
-; RUN: -check-prefixes=ALL,MM,MM64
define signext i1 @not_i1(i1 signext %a) {
entry:
@@ -98,9 +96,6 @@ entry:
; MM32: not16 $2, $4
; MM32: not16 $3, $5
- ; MM64: daddiu $[[T0:[0-9]+]], $zero, -1
- ; MM64: xor $2, $4, $[[T0]]
-
%r = xor i64 %a, -1
ret i64 %r
}
@@ -123,10 +118,6 @@ entry:
; MM32: not16 $4, $6
; MM32: not16 $5, $7
- ; MM64: daddiu $[[T0:[0-9]+]], $zero, -1
- ; MM64: xor $2, $4, $[[T0]]
- ; MM64: xor $3, $5, $[[T0]]
-
%r = xor i128 %a, -1
ret i128 %r
}
@@ -138,7 +129,6 @@ entry:
; GP32: nor $2, $5, $4
; GP64: or $1, $5, $4
; MM32: nor $2, $5, $4
- ; MM64: or $1, $5, $4
%or = or i1 %b, %a
%r = xor i1 %or, -1
@@ -152,7 +142,6 @@ entry:
; GP32: nor $2, $5, $4
; GP64: or $1, $5, $4
; MM32: nor $2, $5, $4
- ; MM64: or $1, $5, $4
%or = or i8 %b, %a
%r = xor i8 %or, -1
@@ -166,7 +155,6 @@ entry:
; GP32: nor $2, $5, $4
; GP64: or $1, $5, $4
; MM32: nor $2, $5, $4
- ; MM64: or $1, $5, $4
%or = or i16 %b, %a
%r = xor i16 %or, -1
@@ -185,10 +173,6 @@ entry:
; MM32: nor $2, $5, $4
- ; MM64: or $[[T0:[0-9]+]], $5, $4
- ; MM64: sll $[[T1:[0-9]+]], $[[T0]], 0
- ; MM64: not16 $2, $[[T1]]
-
%or = or i32 %b, %a
%r = xor i32 %or, -1
ret i32 %r
@@ -207,8 +191,6 @@ entry:
; MM32: nor $2, $6, $4
; MM32: nor $3, $7, $5
- ; MM64: nor $2, $5, $4
-
%or = or i64 %b, %a
%r = xor i64 %or, -1
ret i64 %r
@@ -239,9 +221,6 @@ entry:
; MM32: lw $[[T3:[0-9]+]], 28($sp)
; MM32: nor $5, $[[T3]], $7
- ; MM64: nor $2, $6, $4
- ; MM64: nor $3, $7, $5
-
%or = or i128 %b, %a
%r = xor i128 %or, -1
ret i128 %r
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/or.ll b/llvm/test/CodeGen/Mips/llvm-ir/or.ll
index 609cf0210c3..6850bed9659 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/or.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/or.ll
@@ -15,8 +15,6 @@
; RUN: -check-prefixes=ALL,MM,MM32
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
; RUN: -check-prefixes=ALL,MM,MM32
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \
-; RUN: -check-prefixes=ALL,MM,MM64
define signext i1 @or_i1(i1 signext %a, i1 signext %b) {
entry:
@@ -29,8 +27,6 @@ entry:
; MM32: or16 $[[T0:[0-9]+]], $5
; MM32 move $2, $[[T0]]
- ; MM64: or $1, $4, $5
-
%r = or i1 %a, %b
ret i1 %r
}
@@ -46,8 +42,6 @@ entry:
; MM32: or16 $[[T0:[0-9]+]], $5
; MM32 move $2, $[[T0]]
- ; MM64: or $1, $4, $5
-
%r = or i8 %a, %b
ret i8 %r
}
@@ -63,8 +57,6 @@ entry:
; MM32: or16 $[[T0:[0-9]+]], $5
; MM32 move $2, $[[T0]]
- ; MM64: or $1, $4, $5
-
%r = or i16 %a, %b
ret i16 %r
}
@@ -82,9 +74,6 @@ entry:
; MM32: or16 $[[T0:[0-9]+]], $5
; MM32: move $2, $[[T0]]
- ; MM64: or $[[T0:[0-9]+]], $4, $5
- ; MM64: sll $2, $[[T0]], 0
-
%r = or i32 %a, %b
ret i32 %r
}
@@ -103,8 +92,6 @@ entry:
; MM32: move $2, $[[T0]]
; MM32: move $3, $[[T1]]
- ; MM64: or $2, $4, $5
-
%r = or i64 %a, %b
ret i64 %r
}
@@ -134,9 +121,6 @@ entry:
; MM32: lw $[[T3:[0-9]+]], 28($sp)
; MM32: or16 $[[T3]], $7
- ; MM64: or $2, $4, $6
- ; MM64: or $3, $5, $7
-
%r = or i128 %a, %b
ret i128 %r
}
@@ -193,8 +177,6 @@ entry:
; MM32: ori $3, $5, 4
; MM32: move $2, $4
- ; MM64: ori $2, $4, 4
-
%r = or i64 4, %b
ret i64 %r
}
@@ -218,9 +200,6 @@ entry:
; MM32: move $4, $6
; MM32: move $5, $[[T0]]
- ; MM64: ori $3, $5, 4
- ; MM64: move $2, $4
-
%r = or i128 4, %b
ret i128 %r
}
@@ -281,8 +260,6 @@ entry:
; MM32: ori $3, $5, 31
; MM32: move $2, $4
- ; MM64: ori $2, $4, 31
-
%r = or i64 31, %b
ret i64 %r
}
@@ -306,9 +283,6 @@ entry:
; MM32: move $4, $6
; MM32: move $5, $[[T0]]
- ; MM64: ori $3, $5, 31
- ; MM64: move $2, $4
-
%r = or i128 31, %b
ret i128 %r
}
@@ -373,8 +347,6 @@ entry:
; MM32: ori $3, $5, 255
; MM32: move $2, $4
- ; MM64: ori $2, $4, 255
-
%r = or i64 255, %b
ret i64 %r
}
@@ -398,9 +370,6 @@ entry:
; MM32: move $4, $6
; MM32: move $5, $[[T0]]
- ; MM64: ori $3, $5, 255
- ; MM64: move $2, $4
-
%r = or i128 255, %b
ret i128 %r
}
@@ -464,8 +433,6 @@ entry:
; MM32: ori $3, $5, 32768
; MM32: move $2, $4
- ; MM64: ori $2, $4, 32768
-
%r = or i64 32768, %b
ret i64 %r
}
@@ -489,9 +456,6 @@ entry:
; MM32: move $4, $6
; MM32: move $5, $[[T0]]
- ; MM64: ori $3, $5, 32768
- ; MM64: move $2, $4
-
%r = or i128 32768, %b
ret i128 %r
}
@@ -552,8 +516,6 @@ entry:
; MM32: ori $3, $5, 65
; MM32: move $2, $4
- ; MM64: ori $2, $4, 65
-
%r = or i64 65, %b
ret i64 %r
}
@@ -577,9 +539,6 @@ entry:
; MM32: move $4, $6
; MM32: move $5, $[[T0]]
- ; MM64: ori $3, $5, 65
- ; MM64: move $2, $4
-
%r = or i128 65, %b
ret i128 %r
}
@@ -636,8 +595,6 @@ entry:
; MM32: ori $3, $5, 256
; MM32: move $2, $4
- ; MM64: ori $2, $4, 256
-
%r = or i64 256, %b
ret i64 %r
}
@@ -661,9 +618,6 @@ entry:
; MM32: move $4, $6
; MM32: move $5, $[[T0]]
- ; MM64: ori $3, $5, 256
- ; MM64: move $2, $4
-
%r = or i128 256, %b
ret i128 %r
}
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll b/llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll
index defd25bb41a..11e766319e7 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll
@@ -30,8 +30,6 @@
; RUN: -check-prefixes=ALL,MMR3,MM32
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
; RUN: -check-prefixes=ALL,MMR6,MM32
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic | FileCheck %s \
-; RUN: -check-prefixes=ALL,MMR6,MM64
define signext i1 @sdiv_i1(i1 signext %a, i1 signext %b) {
entry:
@@ -174,9 +172,6 @@ entry:
; MM32: lw $25, %call16(__divdi3)($2)
- ; MM64: ddiv $2, $4, $5
- ; MM64: teq $5, $zero, 7
-
%r = sdiv i64 %a, %b
ret i64 %r
}
@@ -192,8 +187,6 @@ entry:
; MM32: lw $25, %call16(__divti3)($16)
- ; MM64: ld $25, %call16(__divti3)($2)
-
%r = sdiv i128 %a, %b
ret i128 %r
}
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/srem.ll b/llvm/test/CodeGen/Mips/llvm-ir/srem.ll
index 42664d7457e..971b1e00d8a 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/srem.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/srem.ll
@@ -30,8 +30,6 @@
; RUN: -check-prefixes=ALL,MMR3,MM32
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
; RUN: -check-prefixes=ALL,MMR6,MM32
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -relocation-model=pic | FileCheck %s \
-; RUN: -check-prefixes=ALL,MMR6,MM64
define signext i1 @srem_i1(i1 signext %a, i1 signext %b) {
entry:
@@ -166,9 +164,6 @@ entry:
; MM32: lw $25, %call16(__moddi3)($2)
- ; MM64: dmod $2, $4, $5
- ; MM64: teq $5, $zero, 7
-
%r = srem i64 %a, %b
ret i64 %r
}
@@ -184,8 +179,6 @@ entry:
; MM32: lw $25, %call16(__modti3)($16)
- ; MM64: ld $25, %call16(__modti3)($2)
-
%r = srem i128 %a, %b
ret i128 %r
}
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/sub.ll b/llvm/test/CodeGen/Mips/llvm-ir/sub.ll
index 2ab7225f445..d06170f1db1 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/sub.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/sub.ll
@@ -28,8 +28,6 @@
; RUN: -check-prefixes=R2-R6,GP64,NOT-MM,GP64-R2
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
; RUN: -check-prefixes=R2-R6,GP64,NOT-MM,GP64-R2
-; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \
-; RUN: -check-prefixes=GP64,MM64
define signext i1 @sub_i1(i1 signext %a, i1 signext %b) {
entry:
@@ -213,16 +211,6 @@ entry:
; GP64-R2: dsubu $2, $1, $[[T1]]
; GP64-R2: dsubu $3, $5, $7
-; FIXME: Again, redundant sign extension. Also, microMIPSR6 has the
-; dext instruction which should be used here.
-
-; MM64: dsubu $[[T0:[0-9]+]], $4, $6
-; MM64: sltu $[[T1:[0-9]+]], $5, $7
-; MM64: dsll $[[T2:[0-9]+]], $[[T1]], 32
-; MM64: dsrl $[[T3:[0-9]+]], $[[T2]], 32
-; MM64: dsubu $2, $[[T0]], $[[T3]]
-; MM64: dsubu $3, $5, $7
-
%r = sub i128 %a, %b
ret i128 %r
}
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/udiv.ll b/llvm/test/CodeGen/Mips/llvm-ir/udiv.ll
index 78ab36442a9..70882a33869 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/udiv.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/udiv.ll
@@ -30,8 +30,6 @@
; RUN: -check-prefixes=ALL,MMR3,MM32
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
; RUN: -check-prefixes=ALL,MMR6,MM32
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -relocation-model=pic | FileCheck %s \
-; RUN: -check-prefixes=ALL,MMR6,MM64
define zeroext i1 @udiv_i1(i1 zeroext %a, i1 zeroext %b) {
entry:
@@ -136,9 +134,6 @@ entry:
; MM32: lw $25, %call16(__udivdi3)($2)
- ; MM64: ddivu $2, $4, $5
- ; MM64: teq $5, $zero, 7
-
%r = udiv i64 %a, %b
ret i64 %r
}
@@ -154,8 +149,6 @@ entry:
; MM32: lw $25, %call16(__udivti3)($16)
- ; MM64: ld $25, %call16(__udivti3)($2)
-
%r = udiv i128 %a, %b
ret i128 %r
}
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/urem.ll b/llvm/test/CodeGen/Mips/llvm-ir/urem.ll
index 160c126c7e3..d0ac39d61dc 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/urem.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/urem.ll
@@ -30,8 +30,6 @@
; RUN: -check-prefixes=ALL,MMR3,MM32
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
; RUN: -check-prefixes=ALL,MMR6,MM32
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -relocation-model=pic | FileCheck %s \
-; RUN: -check-prefixes=ALL,MMR6,MM64
define signext i1 @urem_i1(i1 signext %a, i1 signext %b) {
entry:
@@ -192,9 +190,6 @@ entry:
; MM32: lw $25, %call16(__umoddi3)($2)
- ; MM64: dmodu $2, $4, $5
- ; MM64: teq $5, $zero, 7
-
%r = urem i64 %a, %b
ret i64 %r
}
@@ -210,8 +205,6 @@ entry:
; MM32: lw $25, %call16(__umodti3)($16)
- ; MM64: ld $25, %call16(__umodti3)($2)
-
%r = urem i128 %a, %b
ret i128 %r
}
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/xor.ll b/llvm/test/CodeGen/Mips/llvm-ir/xor.ll
index 068d390839d..8fcf11feace 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/xor.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/xor.ll
@@ -26,8 +26,6 @@
; RUN: -check-prefixes=ALL,MM,MM32
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
; RUN: -check-prefixes=ALL,MM,MM32
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \
-; RUN: -check-prefixes=ALL,MM,MM64
define signext i1 @xor_i1(i1 signext %a, i1 signext %b) {
entry:
@@ -40,8 +38,6 @@ entry:
; MM32: xor16 $[[T0:[0-9]+]], $5
; MM32: move $2, $[[T0]]
- ; MM64: xor $1, $4, $5
-
%r = xor i1 %a, %b
ret i1 %r
}
@@ -57,8 +53,6 @@ entry:
; MM32: xor16 $[[T0:[0-9]+]], $5
; MM32: move $2, $[[T0]]
- ; MM64: xor $1, $4, $5
-
%r = xor i8 %a, %b
ret i8 %r
}
@@ -74,8 +68,6 @@ entry:
; MM32: xor16 $[[T0:[0-9]+]], $5
; MM32: move $2, $[[T0]]
- ; MM64: xor $1, $4, $5
-
%r = xor i16 %a, %b
ret i16 %r
}
@@ -92,9 +84,6 @@ entry:
; MM32: xor16 $[[T0:[0-9]+]], $5
; MM32: move $2, $[[T0]]
- ; MM64: xor $[[T0:[0-9]+]], $4, $5
- ; MM64: sll $2, $[[T0]], 0
-
%r = xor i32 %a, %b
ret i32 %r
}
@@ -113,8 +102,6 @@ entry:
; MM32: move $2, $[[T0]]
; MM32: move $3, $[[T1]]
- ; MM64: xor $2, $4, $5
-
%r = xor i64 %a, %b
ret i64 %r
}
@@ -144,9 +131,6 @@ entry:
; MM32: lw $[[T3:[0-9]+]], 28($sp)
; MM32: xor16 $[[T3]], $7
- ; MM64: xor $2, $4, $6
- ; MM64: xor $3, $5, $7
-
%r = xor i128 %a, %b
ret i128 %r
}
@@ -203,8 +187,6 @@ entry:
; MM32: xori $3, $5, 4
; MM32: move $2, $4
- ; MM64: xori $2, $4, 4
-
%r = xor i64 4, %b
ret i64 %r
}
@@ -228,9 +210,6 @@ entry:
; MM32: move $4, $6
; MM32: move $5, $[[T0]]
- ; MM64: xori $3, $5, 4
- ; MM64: move $2, $4
-
%r = xor i128 4, %b
ret i128 %r
}
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