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-rw-r--r--llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll17
-rw-r--r--llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll21
-rw-r--r--llvm/test/CodeGen/Mips/llvm-ir/select-int.ll14
3 files changed, 29 insertions, 23 deletions
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll b/llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll
index 6067cfb3b1c..ed8d9030ccf 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll
@@ -29,7 +29,7 @@
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64
-define double @tst_select_i1_double(i1 signext %s, double %x, double %y) {
+define double @tst_select_i1_double(i1 %s, double %x, double %y) {
entry:
; ALL-LABEL: tst_select_i1_double:
@@ -53,8 +53,10 @@ entry:
; SEL-32: mtc1 $7, $[[F0:f[0-9]+]]
; SEL-32: mthc1 $6, $[[F0]]
+ ; SEL-32: sll $[[T0:[0-9]+]], $4, 31
+ ; SEL-32: sra $[[T1:[0-9]+]], $[[T0]], 31
; SEL-32: ldc1 $[[F1:f[0-9]+]], 16($sp)
- ; SEL-32: mtc1 $4, $f0
+ ; SEL-32: mtc1 $[[T1]], $f0
; SEL-32: sel.d $f0, $[[F1]], $[[F0]]
; M3: andi $[[T0:[0-9]+]], $4, 1
@@ -69,14 +71,15 @@ entry:
; CMOV-64: movn.d $f14, $f13, $[[T0]]
; CMOV-64: mov.d $f0, $f14
- ; SEL-64: mtc1 $4, $f0
+ ; SEL-64: dsll $[[T0:[0-9]+]], $4, 63
+ ; SEL-64: dsra $[[T1:[0-9]+]], $[[T0]], 63
+ ; SEL-64: dmtc1 $[[T1]], $f0
; SEL-64: sel.d $f0, $f14, $f13
%r = select i1 %s, double %x, double %y
ret double %r
}
-define double @tst_select_i1_double_reordered(double %x, double %y,
- i1 signext %s) {
+define double @tst_select_i1_double_reordered(double %x, double %y, i1 %s) {
entry:
; ALL-LABEL: tst_select_i1_double_reordered:
@@ -110,7 +113,9 @@ entry:
; CMOV-64: movn.d $f13, $f12, $[[T0]]
; CMOV-64: mov.d $f0, $f13
- ; SEL-64: mtc1 $6, $f0
+ ; SEL-64: dsll $[[T0:[0-9]+]], $6, 63
+ ; SEL-64: dsra $[[T1:[0-9]+]], $[[T0]], 63
+ ; SEL-64: dmtc1 $[[T1]], $f0
; SEL-64: sel.d $f0, $f13, $f12
%r = select i1 %s, double %x, double %y
ret double %r
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll b/llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll
index 173055a5ef5..c554c6983bf 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll
@@ -29,7 +29,7 @@
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64
-define float @tst_select_i1_float(i1 signext %s, float %x, float %y) {
+define float @tst_select_i1_float(i1 %s, float %x, float %y) {
entry:
; ALL-LABEL: tst_select_i1_float:
@@ -51,21 +51,24 @@ entry:
; SEL-32: mtc1 $5, $[[F0:f[0-9]+]]
; SEL-32: mtc1 $6, $[[F1:f[0-9]+]]
- ; SEL-32: mtc1 $4, $f0
+ ; SEL-32: sll $[[T0:[0-9]+]], $4, 31
+ ; SEL-32: sra $[[T1:[0-9]+]], $[[T0]], 31
+ ; SEL-32: mtc1 $[[T1]], $f0
; SEL-32: sel.s $f0, $[[F1]], $[[F0]]
; CMOV-64: andi $[[T0:[0-9]+]], $4, 1
; CMOV-64: movn.s $f14, $f13, $[[T0]]
; CMOV-64: mov.s $f0, $f14
- ; SEL-64: mtc1 $4, $f0
+ ; SEL-64: dsll $[[T0:[0-9]+]], $4, 63
+ ; SEL-64: dsra $[[T1:[0-9]+]], $[[T0]], 63
+ ; SEL-64: dmtc1 $[[T1]], $f0
; SEL-64: sel.s $f0, $f14, $f13
%r = select i1 %s, float %x, float %y
ret float %r
}
-define float @tst_select_i1_float_reordered(float %x, float %y,
- i1 signext %s) {
+define float @tst_select_i1_float_reordered(float %x, float %y, i1 %s) {
entry:
; ALL-LABEL: tst_select_i1_float_reordered:
@@ -82,14 +85,18 @@ entry:
; CMOV-32: movn.s $f14, $f12, $[[T0]]
; CMOV-32: mov.s $f0, $f14
- ; SEL-32: mtc1 $6, $f0
+ ; SEL-32: sll $[[T0:[0-9]+]], $6, 31
+ ; SEL-32: sra $[[T1:[0-9]+]], $[[T0]], 31
+ ; SEL-32: mtc1 $[[T1]], $f0
; SEL-32: sel.s $f0, $f14, $f12
; CMOV-64: andi $[[T0:[0-9]+]], $6, 1
; CMOV-64: movn.s $f13, $f12, $[[T0]]
; CMOV-64: mov.s $f0, $f13
- ; SEL-64: mtc1 $6, $f0
+ ; SEL-64: dsll $[[T0:[0-9]+]], $6, 63
+ ; SEL-64: dsra $[[T1:[0-9]+]], $[[T0]], 63
+ ; SEL-64: dmtc1 $[[T1]], $f0
; SEL-64: sel.s $f0, $f13, $f12
%r = select i1 %s, float %x, float %y
ret float %r
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll b/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll
index 87f2ca4b8a1..c4632fb3c8e 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll
@@ -29,8 +29,7 @@
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64
-define signext i1 @tst_select_i1_i1(i1 signext %s,
- i1 signext %x, i1 signext %y) {
+define signext i1 @tst_select_i1_i1(i1 %s, i1 signext %x, i1 signext %y) {
entry:
; ALL-LABEL: tst_select_i1_i1:
@@ -54,8 +53,7 @@ entry:
ret i1 %r
}
-define signext i8 @tst_select_i1_i8(i1 signext %s,
- i8 signext %x, i8 signext %y) {
+define signext i8 @tst_select_i1_i8(i1 %s, i8 signext %x, i8 signext %y) {
entry:
; ALL-LABEL: tst_select_i1_i8:
@@ -79,8 +77,7 @@ entry:
ret i8 %r
}
-define signext i32 @tst_select_i1_i32(i1 signext %s,
- i32 signext %x, i32 signext %y) {
+define signext i32 @tst_select_i1_i32(i1 %s, i32 signext %x, i32 signext %y) {
entry:
; ALL-LABEL: tst_select_i1_i32:
@@ -104,8 +101,7 @@ entry:
ret i32 %r
}
-define signext i64 @tst_select_i1_i64(i1 signext %s,
- i64 signext %x, i64 signext %y) {
+define signext i64 @tst_select_i1_i64(i1 %s, i64 signext %x, i64 signext %y) {
entry:
; ALL-LABEL: tst_select_i1_i64:
@@ -152,8 +148,6 @@ entry:
; CMOV-64: move $2, $6
; SEL-64: andi $[[T0:[0-9]+]], $4, 1
- ; FIXME: This shift is redundant
- ; SEL-64: sll $[[T0]], $[[T0]], 0
; SEL-64: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
; SEL-64: selnez $[[T0]], $5, $[[T0]]
; SEL-64: or $2, $[[T0]], $[[T1]]
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