diff options
Diffstat (limited to 'llvm/test/CodeGen/Hexagon/memops.ll')
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/memops.ll | 252 |
1 files changed, 126 insertions, 126 deletions
diff --git a/llvm/test/CodeGen/Hexagon/memops.ll b/llvm/test/CodeGen/Hexagon/memops.ll index 011a4e50e5d..c3b8b7bdf98 100644 --- a/llvm/test/CodeGen/Hexagon/memops.ll +++ b/llvm/test/CodeGen/Hexagon/memops.ll @@ -4,7 +4,7 @@ define void @memop_unsigned_char_add5(i8* nocapture %p) nounwind { entry: ; CHECK-LABEL: memop_unsigned_char_add5: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 +; CHECK: memb(r{{[0-9]+}}+#0) += #5 %0 = load i8, i8* %p, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 5 @@ -16,7 +16,7 @@ entry: define void @memop_unsigned_char_add(i8* nocapture %p, i8 zeroext %x) nounwind { entry: ; CHECK-LABEL: memop_unsigned_char_add: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} +; CHECK: memb(r{{[0-9]+}}+#0) += r{{[0-9]+}} %conv = zext i8 %x to i32 %0 = load i8, i8* %p, align 1 %conv1 = zext i8 %0 to i32 @@ -29,7 +29,7 @@ entry: define void @memop_unsigned_char_sub(i8* nocapture %p, i8 zeroext %x) nounwind { entry: ; CHECK-LABEL: memop_unsigned_char_sub: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} +; CHECK: memb(r{{[0-9]+}}+#0) -= r{{[0-9]+}} %conv = zext i8 %x to i32 %0 = load i8, i8* %p, align 1 %conv1 = zext i8 %0 to i32 @@ -42,7 +42,7 @@ entry: define void @memop_unsigned_char_or(i8* nocapture %p, i8 zeroext %x) nounwind { entry: ; CHECK-LABEL: memop_unsigned_char_or: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} +; CHECK: memb(r{{[0-9]+}}+#0) |= r{{[0-9]+}} %0 = load i8, i8* %p, align 1 %or3 = or i8 %0, %x store i8 %or3, i8* %p, align 1 @@ -52,7 +52,7 @@ entry: define void @memop_unsigned_char_and(i8* nocapture %p, i8 zeroext %x) nounwind { entry: ; CHECK-LABEL: memop_unsigned_char_and: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} +; CHECK: memb(r{{[0-9]+}}+#0) &= r{{[0-9]+}} %0 = load i8, i8* %p, align 1 %and3 = and i8 %0, %x store i8 %and3, i8* %p, align 1 @@ -62,7 +62,7 @@ entry: define void @memop_unsigned_char_clrbit(i8* nocapture %p) nounwind { entry: ; CHECK-LABEL: memop_unsigned_char_clrbit: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) +; CHECK: memb(r{{[0-9]+}}+#0) = clrbit(#5) %0 = load i8, i8* %p, align 1 %conv = zext i8 %0 to i32 %and = and i32 %conv, 223 @@ -74,7 +74,7 @@ entry: define void @memop_unsigned_char_setbit(i8* nocapture %p) nounwind { entry: ; CHECK-LABEL: memop_unsigned_char_setbit: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) +; CHECK: memb(r{{[0-9]+}}+#0) = setbit(#7) %0 = load i8, i8* %p, align 1 %conv = zext i8 %0 to i32 %or = or i32 %conv, 128 @@ -86,7 +86,7 @@ entry: define void @memop_unsigned_char_add5_index(i8* nocapture %p, i32 %i) nounwind { entry: ; CHECK-LABEL: memop_unsigned_char_add5_index: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 +; CHECK: memb(r{{[0-9]+}}+#0) += #5 %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i %0 = load i8, i8* %add.ptr, align 1 %conv = zext i8 %0 to i32 @@ -99,7 +99,7 @@ entry: define void @memop_unsigned_char_add_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind { entry: ; CHECK-LABEL: memop_unsigned_char_add_index: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} +; CHECK: memb(r{{[0-9]+}}+#0) += r{{[0-9]+}} %conv = zext i8 %x to i32 %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i %0 = load i8, i8* %add.ptr, align 1 @@ -113,7 +113,7 @@ entry: define void @memop_unsigned_char_sub_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind { entry: ; CHECK-LABEL: memop_unsigned_char_sub_index: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} +; CHECK: memb(r{{[0-9]+}}+#0) -= r{{[0-9]+}} %conv = zext i8 %x to i32 %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i %0 = load i8, i8* %add.ptr, align 1 @@ -127,7 +127,7 @@ entry: define void @memop_unsigned_char_or_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind { entry: ; CHECK-LABEL: memop_unsigned_char_or_index: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} +; CHECK: memb(r{{[0-9]+}}+#0) |= r{{[0-9]+}} %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i %0 = load i8, i8* %add.ptr, align 1 %or3 = or i8 %0, %x @@ -138,7 +138,7 @@ entry: define void @memop_unsigned_char_and_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind { entry: ; CHECK-LABEL: memop_unsigned_char_and_index: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} +; CHECK: memb(r{{[0-9]+}}+#0) &= r{{[0-9]+}} %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i %0 = load i8, i8* %add.ptr, align 1 %and3 = and i8 %0, %x @@ -149,7 +149,7 @@ entry: define void @memop_unsigned_char_clrbit_index(i8* nocapture %p, i32 %i) nounwind { entry: ; CHECK-LABEL: memop_unsigned_char_clrbit_index: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) +; CHECK: memb(r{{[0-9]+}}+#0) = clrbit(#5) %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i %0 = load i8, i8* %add.ptr, align 1 %conv = zext i8 %0 to i32 @@ -162,7 +162,7 @@ entry: define void @memop_unsigned_char_setbit_index(i8* nocapture %p, i32 %i) nounwind { entry: ; CHECK-LABEL: memop_unsigned_char_setbit_index: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) +; CHECK: memb(r{{[0-9]+}}+#0) = setbit(#7) %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i %0 = load i8, i8* %add.ptr, align 1 %conv = zext i8 %0 to i32 @@ -175,7 +175,7 @@ entry: define void @memop_unsigned_char_add5_index5(i8* nocapture %p) nounwind { entry: ; CHECK-LABEL: memop_unsigned_char_add5_index5: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}#5 +; CHECK: memb(r{{[0-9]+}}+#5) += #5 %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 %0 = load i8, i8* %add.ptr, align 1 %conv = zext i8 %0 to i32 @@ -188,7 +188,7 @@ entry: define void @memop_unsigned_char_add_index5(i8* nocapture %p, i8 zeroext %x) nounwind { entry: ; CHECK-LABEL: memop_unsigned_char_add_index5: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}r{{[0-9]+}} +; CHECK: memb(r{{[0-9]+}}+#5) += r{{[0-9]+}} %conv = zext i8 %x to i32 %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 %0 = load i8, i8* %add.ptr, align 1 @@ -202,7 +202,7 @@ entry: define void @memop_unsigned_char_sub_index5(i8* nocapture %p, i8 zeroext %x) nounwind { entry: ; CHECK-LABEL: memop_unsigned_char_sub_index5: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}-={{ *}}r{{[0-9]+}} +; CHECK: memb(r{{[0-9]+}}+#5) -= r{{[0-9]+}} %conv = zext i8 %x to i32 %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 %0 = load i8, i8* %add.ptr, align 1 @@ -216,7 +216,7 @@ entry: define void @memop_unsigned_char_or_index5(i8* nocapture %p, i8 zeroext %x) nounwind { entry: ; CHECK-LABEL: memop_unsigned_char_or_index5: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}|={{ *}}r{{[0-9]+}} +; CHECK: memb(r{{[0-9]+}}+#5) |= r{{[0-9]+}} %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 %0 = load i8, i8* %add.ptr, align 1 %or3 = or i8 %0, %x @@ -227,7 +227,7 @@ entry: define void @memop_unsigned_char_and_index5(i8* nocapture %p, i8 zeroext %x) nounwind { entry: ; CHECK-LABEL: memop_unsigned_char_and_index5: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}&={{ *}}r{{[0-9]+}} +; CHECK: memb(r{{[0-9]+}}+#5) &= r{{[0-9]+}} %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 %0 = load i8, i8* %add.ptr, align 1 %and3 = and i8 %0, %x @@ -238,7 +238,7 @@ entry: define void @memop_unsigned_char_clrbit_index5(i8* nocapture %p) nounwind { entry: ; CHECK-LABEL: memop_unsigned_char_clrbit_index5: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) +; CHECK: memb(r{{[0-9]+}}+#5) = clrbit(#5) %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 %0 = load i8, i8* %add.ptr, align 1 %conv = zext i8 %0 to i32 @@ -251,7 +251,7 @@ entry: define void @memop_unsigned_char_setbit_index5(i8* nocapture %p) nounwind { entry: ; CHECK-LABEL: memop_unsigned_char_setbit_index5: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) +; CHECK: memb(r{{[0-9]+}}+#5) = setbit(#7) %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 %0 = load i8, i8* %add.ptr, align 1 %conv = zext i8 %0 to i32 @@ -264,7 +264,7 @@ entry: define void @memop_signed_char_add5(i8* nocapture %p) nounwind { entry: ; CHECK-LABEL: memop_signed_char_add5: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 +; CHECK: memb(r{{[0-9]+}}+#0) += #5 %0 = load i8, i8* %p, align 1 %conv2 = zext i8 %0 to i32 %add = add nsw i32 %conv2, 5 @@ -276,7 +276,7 @@ entry: define void @memop_signed_char_add(i8* nocapture %p, i8 signext %x) nounwind { entry: ; CHECK-LABEL: memop_signed_char_add: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} +; CHECK: memb(r{{[0-9]+}}+#0) += r{{[0-9]+}} %conv4 = zext i8 %x to i32 %0 = load i8, i8* %p, align 1 %conv13 = zext i8 %0 to i32 @@ -289,7 +289,7 @@ entry: define void @memop_signed_char_sub(i8* nocapture %p, i8 signext %x) nounwind { entry: ; CHECK-LABEL: memop_signed_char_sub: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} +; CHECK: memb(r{{[0-9]+}}+#0) -= r{{[0-9]+}} %conv4 = zext i8 %x to i32 %0 = load i8, i8* %p, align 1 %conv13 = zext i8 %0 to i32 @@ -302,7 +302,7 @@ entry: define void @memop_signed_char_or(i8* nocapture %p, i8 signext %x) nounwind { entry: ; CHECK-LABEL: memop_signed_char_or: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} +; CHECK: memb(r{{[0-9]+}}+#0) |= r{{[0-9]+}} %0 = load i8, i8* %p, align 1 %or3 = or i8 %0, %x store i8 %or3, i8* %p, align 1 @@ -312,7 +312,7 @@ entry: define void @memop_signed_char_and(i8* nocapture %p, i8 signext %x) nounwind { entry: ; CHECK-LABEL: memop_signed_char_and: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} +; CHECK: memb(r{{[0-9]+}}+#0) &= r{{[0-9]+}} %0 = load i8, i8* %p, align 1 %and3 = and i8 %0, %x store i8 %and3, i8* %p, align 1 @@ -322,7 +322,7 @@ entry: define void @memop_signed_char_clrbit(i8* nocapture %p) nounwind { entry: ; CHECK-LABEL: memop_signed_char_clrbit: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) +; CHECK: memb(r{{[0-9]+}}+#0) = clrbit(#5) %0 = load i8, i8* %p, align 1 %conv2 = zext i8 %0 to i32 %and = and i32 %conv2, 223 @@ -334,7 +334,7 @@ entry: define void @memop_signed_char_setbit(i8* nocapture %p) nounwind { entry: ; CHECK-LABEL: memop_signed_char_setbit: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) +; CHECK: memb(r{{[0-9]+}}+#0) = setbit(#7) %0 = load i8, i8* %p, align 1 %conv2 = zext i8 %0 to i32 %or = or i32 %conv2, 128 @@ -346,7 +346,7 @@ entry: define void @memop_signed_char_add5_index(i8* nocapture %p, i32 %i) nounwind { entry: ; CHECK-LABEL: memop_signed_char_add5_index: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 +; CHECK: memb(r{{[0-9]+}}+#0) += #5 %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i %0 = load i8, i8* %add.ptr, align 1 %conv2 = zext i8 %0 to i32 @@ -359,7 +359,7 @@ entry: define void @memop_signed_char_add_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind { entry: ; CHECK-LABEL: memop_signed_char_add_index: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} +; CHECK: memb(r{{[0-9]+}}+#0) += r{{[0-9]+}} %conv4 = zext i8 %x to i32 %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i %0 = load i8, i8* %add.ptr, align 1 @@ -373,7 +373,7 @@ entry: define void @memop_signed_char_sub_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind { entry: ; CHECK-LABEL: memop_signed_char_sub_index: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} +; CHECK: memb(r{{[0-9]+}}+#0) -= r{{[0-9]+}} %conv4 = zext i8 %x to i32 %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i %0 = load i8, i8* %add.ptr, align 1 @@ -387,7 +387,7 @@ entry: define void @memop_signed_char_or_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind { entry: ; CHECK-LABEL: memop_signed_char_or_index: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} +; CHECK: memb(r{{[0-9]+}}+#0) |= r{{[0-9]+}} %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i %0 = load i8, i8* %add.ptr, align 1 %or3 = or i8 %0, %x @@ -398,7 +398,7 @@ entry: define void @memop_signed_char_and_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind { entry: ; CHECK-LABEL: memop_signed_char_and_index: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} +; CHECK: memb(r{{[0-9]+}}+#0) &= r{{[0-9]+}} %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i %0 = load i8, i8* %add.ptr, align 1 %and3 = and i8 %0, %x @@ -409,7 +409,7 @@ entry: define void @memop_signed_char_clrbit_index(i8* nocapture %p, i32 %i) nounwind { entry: ; CHECK-LABEL: memop_signed_char_clrbit_index: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) +; CHECK: memb(r{{[0-9]+}}+#0) = clrbit(#5) %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i %0 = load i8, i8* %add.ptr, align 1 %conv2 = zext i8 %0 to i32 @@ -422,7 +422,7 @@ entry: define void @memop_signed_char_setbit_index(i8* nocapture %p, i32 %i) nounwind { entry: ; CHECK-LABEL: memop_signed_char_setbit_index: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) +; CHECK: memb(r{{[0-9]+}}+#0) = setbit(#7) %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i %0 = load i8, i8* %add.ptr, align 1 %conv2 = zext i8 %0 to i32 @@ -435,7 +435,7 @@ entry: define void @memop_signed_char_add5_index5(i8* nocapture %p) nounwind { entry: ; CHECK-LABEL: memop_signed_char_add5_index5: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}#5 +; CHECK: memb(r{{[0-9]+}}+#5) += #5 %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 %0 = load i8, i8* %add.ptr, align 1 %conv2 = zext i8 %0 to i32 @@ -448,7 +448,7 @@ entry: define void @memop_signed_char_add_index5(i8* nocapture %p, i8 signext %x) nounwind { entry: ; CHECK-LABEL: memop_signed_char_add_index5: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}r{{[0-9]+}} +; CHECK: memb(r{{[0-9]+}}+#5) += r{{[0-9]+}} %conv4 = zext i8 %x to i32 %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 %0 = load i8, i8* %add.ptr, align 1 @@ -462,7 +462,7 @@ entry: define void @memop_signed_char_sub_index5(i8* nocapture %p, i8 signext %x) nounwind { entry: ; CHECK-LABEL: memop_signed_char_sub_index5: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}-={{ *}}r{{[0-9]+}} +; CHECK: memb(r{{[0-9]+}}+#5) -= r{{[0-9]+}} %conv4 = zext i8 %x to i32 %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 %0 = load i8, i8* %add.ptr, align 1 @@ -476,7 +476,7 @@ entry: define void @memop_signed_char_or_index5(i8* nocapture %p, i8 signext %x) nounwind { entry: ; CHECK-LABEL: memop_signed_char_or_index5: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}|={{ *}}r{{[0-9]+}} +; CHECK: memb(r{{[0-9]+}}+#5) |= r{{[0-9]+}} %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 %0 = load i8, i8* %add.ptr, align 1 %or3 = or i8 %0, %x @@ -487,7 +487,7 @@ entry: define void @memop_signed_char_and_index5(i8* nocapture %p, i8 signext %x) nounwind { entry: ; CHECK-LABEL: memop_signed_char_and_index5: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}&={{ *}}r{{[0-9]+}} +; CHECK: memb(r{{[0-9]+}}+#5) &= r{{[0-9]+}} %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 %0 = load i8, i8* %add.ptr, align 1 %and3 = and i8 %0, %x @@ -498,7 +498,7 @@ entry: define void @memop_signed_char_clrbit_index5(i8* nocapture %p) nounwind { entry: ; CHECK-LABEL: memop_signed_char_clrbit_index5: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) +; CHECK: memb(r{{[0-9]+}}+#5) = clrbit(#5) %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 %0 = load i8, i8* %add.ptr, align 1 %conv2 = zext i8 %0 to i32 @@ -511,7 +511,7 @@ entry: define void @memop_signed_char_setbit_index5(i8* nocapture %p) nounwind { entry: ; CHECK-LABEL: memop_signed_char_setbit_index5: -; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) +; CHECK: memb(r{{[0-9]+}}+#5) = setbit(#7) %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 %0 = load i8, i8* %add.ptr, align 1 %conv2 = zext i8 %0 to i32 @@ -524,7 +524,7 @@ entry: define void @memop_unsigned_short_add5(i16* nocapture %p) nounwind { entry: ; CHECK-LABEL: memop_unsigned_short_add5: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 +; CHECK: memh(r{{[0-9]+}}+#0) += #5 %0 = load i16, i16* %p, align 2 %conv = zext i16 %0 to i32 %add = add nsw i32 %conv, 5 @@ -536,7 +536,7 @@ entry: define void @memop_unsigned_short_add(i16* nocapture %p, i16 zeroext %x) nounwind { entry: ; CHECK-LABEL: memop_unsigned_short_add: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} +; CHECK: memh(r{{[0-9]+}}+#0) += r{{[0-9]+}} %conv = zext i16 %x to i32 %0 = load i16, i16* %p, align 2 %conv1 = zext i16 %0 to i32 @@ -549,7 +549,7 @@ entry: define void @memop_unsigned_short_sub(i16* nocapture %p, i16 zeroext %x) nounwind { entry: ; CHECK-LABEL: memop_unsigned_short_sub: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} +; CHECK: memh(r{{[0-9]+}}+#0) -= r{{[0-9]+}} %conv = zext i16 %x to i32 %0 = load i16, i16* %p, align 2 %conv1 = zext i16 %0 to i32 @@ -562,7 +562,7 @@ entry: define void @memop_unsigned_short_or(i16* nocapture %p, i16 zeroext %x) nounwind { entry: ; CHECK-LABEL: memop_unsigned_short_or: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} +; CHECK: memh(r{{[0-9]+}}+#0) |= r{{[0-9]+}} %0 = load i16, i16* %p, align 2 %or3 = or i16 %0, %x store i16 %or3, i16* %p, align 2 @@ -572,7 +572,7 @@ entry: define void @memop_unsigned_short_and(i16* nocapture %p, i16 zeroext %x) nounwind { entry: ; CHECK-LABEL: memop_unsigned_short_and: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} +; CHECK: memh(r{{[0-9]+}}+#0) &= r{{[0-9]+}} %0 = load i16, i16* %p, align 2 %and3 = and i16 %0, %x store i16 %and3, i16* %p, align 2 @@ -582,7 +582,7 @@ entry: define void @memop_unsigned_short_clrbit(i16* nocapture %p) nounwind { entry: ; CHECK-LABEL: memop_unsigned_short_clrbit: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) +; CHECK: memh(r{{[0-9]+}}+#0) = clrbit(#5) %0 = load i16, i16* %p, align 2 %conv = zext i16 %0 to i32 %and = and i32 %conv, 65503 @@ -594,7 +594,7 @@ entry: define void @memop_unsigned_short_setbit(i16* nocapture %p) nounwind { entry: ; CHECK-LABEL: memop_unsigned_short_setbit: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) +; CHECK: memh(r{{[0-9]+}}+#0) = setbit(#7) %0 = load i16, i16* %p, align 2 %conv = zext i16 %0 to i32 %or = or i32 %conv, 128 @@ -606,7 +606,7 @@ entry: define void @memop_unsigned_short_add5_index(i16* nocapture %p, i32 %i) nounwind { entry: ; CHECK-LABEL: memop_unsigned_short_add5_index: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 +; CHECK: memh(r{{[0-9]+}}+#0) += #5 %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i %0 = load i16, i16* %add.ptr, align 2 %conv = zext i16 %0 to i32 @@ -619,7 +619,7 @@ entry: define void @memop_unsigned_short_add_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind { entry: ; CHECK-LABEL: memop_unsigned_short_add_index: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} +; CHECK: memh(r{{[0-9]+}}+#0) += r{{[0-9]+}} %conv = zext i16 %x to i32 %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i %0 = load i16, i16* %add.ptr, align 2 @@ -633,7 +633,7 @@ entry: define void @memop_unsigned_short_sub_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind { entry: ; CHECK-LABEL: memop_unsigned_short_sub_index: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} +; CHECK: memh(r{{[0-9]+}}+#0) -= r{{[0-9]+}} %conv = zext i16 %x to i32 %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i %0 = load i16, i16* %add.ptr, align 2 @@ -647,7 +647,7 @@ entry: define void @memop_unsigned_short_or_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind { entry: ; CHECK-LABEL: memop_unsigned_short_or_index: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} +; CHECK: memh(r{{[0-9]+}}+#0) |= r{{[0-9]+}} %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i %0 = load i16, i16* %add.ptr, align 2 %or3 = or i16 %0, %x @@ -658,7 +658,7 @@ entry: define void @memop_unsigned_short_and_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind { entry: ; CHECK-LABEL: memop_unsigned_short_and_index: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} +; CHECK: memh(r{{[0-9]+}}+#0) &= r{{[0-9]+}} %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i %0 = load i16, i16* %add.ptr, align 2 %and3 = and i16 %0, %x @@ -669,7 +669,7 @@ entry: define void @memop_unsigned_short_clrbit_index(i16* nocapture %p, i32 %i) nounwind { entry: ; CHECK-LABEL: memop_unsigned_short_clrbit_index: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) +; CHECK: memh(r{{[0-9]+}}+#0) = clrbit(#5) %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i %0 = load i16, i16* %add.ptr, align 2 %conv = zext i16 %0 to i32 @@ -682,7 +682,7 @@ entry: define void @memop_unsigned_short_setbit_index(i16* nocapture %p, i32 %i) nounwind { entry: ; CHECK-LABEL: memop_unsigned_short_setbit_index: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) +; CHECK: memh(r{{[0-9]+}}+#0) = setbit(#7) %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i %0 = load i16, i16* %add.ptr, align 2 %conv = zext i16 %0 to i32 @@ -695,7 +695,7 @@ entry: define void @memop_unsigned_short_add5_index5(i16* nocapture %p) nounwind { entry: ; CHECK-LABEL: memop_unsigned_short_add5_index5: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}#5 +; CHECK: memh(r{{[0-9]+}}+#10) += #5 %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 %0 = load i16, i16* %add.ptr, align 2 %conv = zext i16 %0 to i32 @@ -708,7 +708,7 @@ entry: define void @memop_unsigned_short_add_index5(i16* nocapture %p, i16 zeroext %x) nounwind { entry: ; CHECK-LABEL: memop_unsigned_short_add_index5: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}r{{[0-9]+}} +; CHECK: memh(r{{[0-9]+}}+#10) += r{{[0-9]+}} %conv = zext i16 %x to i32 %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 %0 = load i16, i16* %add.ptr, align 2 @@ -722,7 +722,7 @@ entry: define void @memop_unsigned_short_sub_index5(i16* nocapture %p, i16 zeroext %x) nounwind { entry: ; CHECK-LABEL: memop_unsigned_short_sub_index5: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}-={{ *}}r{{[0-9]+}} +; CHECK: memh(r{{[0-9]+}}+#10) -= r{{[0-9]+}} %conv = zext i16 %x to i32 %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 %0 = load i16, i16* %add.ptr, align 2 @@ -736,7 +736,7 @@ entry: define void @memop_unsigned_short_or_index5(i16* nocapture %p, i16 zeroext %x) nounwind { entry: ; CHECK-LABEL: memop_unsigned_short_or_index5: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}|={{ *}}r{{[0-9]+}} +; CHECK: memh(r{{[0-9]+}}+#10) |= r{{[0-9]+}} %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 %0 = load i16, i16* %add.ptr, align 2 %or3 = or i16 %0, %x @@ -747,7 +747,7 @@ entry: define void @memop_unsigned_short_and_index5(i16* nocapture %p, i16 zeroext %x) nounwind { entry: ; CHECK-LABEL: memop_unsigned_short_and_index5: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}&={{ *}}r{{[0-9]+}} +; CHECK: memh(r{{[0-9]+}}+#10) &= r{{[0-9]+}} %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 %0 = load i16, i16* %add.ptr, align 2 %and3 = and i16 %0, %x @@ -758,7 +758,7 @@ entry: define void @memop_unsigned_short_clrbit_index5(i16* nocapture %p) nounwind { entry: ; CHECK-LABEL: memop_unsigned_short_clrbit_index5: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) +; CHECK: memh(r{{[0-9]+}}+#10) = clrbit(#5) %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 %0 = load i16, i16* %add.ptr, align 2 %conv = zext i16 %0 to i32 @@ -771,7 +771,7 @@ entry: define void @memop_unsigned_short_setbit_index5(i16* nocapture %p) nounwind { entry: ; CHECK-LABEL: memop_unsigned_short_setbit_index5: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) +; CHECK: memh(r{{[0-9]+}}+#10) = setbit(#7) %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 %0 = load i16, i16* %add.ptr, align 2 %conv = zext i16 %0 to i32 @@ -784,7 +784,7 @@ entry: define void @memop_signed_short_add5(i16* nocapture %p) nounwind { entry: ; CHECK-LABEL: memop_signed_short_add5: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 +; CHECK: memh(r{{[0-9]+}}+#0) += #5 %0 = load i16, i16* %p, align 2 %conv2 = zext i16 %0 to i32 %add = add nsw i32 %conv2, 5 @@ -796,7 +796,7 @@ entry: define void @memop_signed_short_add(i16* nocapture %p, i16 signext %x) nounwind { entry: ; CHECK-LABEL: memop_signed_short_add: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} +; CHECK: memh(r{{[0-9]+}}+#0) += r{{[0-9]+}} %conv4 = zext i16 %x to i32 %0 = load i16, i16* %p, align 2 %conv13 = zext i16 %0 to i32 @@ -809,7 +809,7 @@ entry: define void @memop_signed_short_sub(i16* nocapture %p, i16 signext %x) nounwind { entry: ; CHECK-LABEL: memop_signed_short_sub: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} +; CHECK: memh(r{{[0-9]+}}+#0) -= r{{[0-9]+}} %conv4 = zext i16 %x to i32 %0 = load i16, i16* %p, align 2 %conv13 = zext i16 %0 to i32 @@ -822,7 +822,7 @@ entry: define void @memop_signed_short_or(i16* nocapture %p, i16 signext %x) nounwind { entry: ; CHECK-LABEL: memop_signed_short_or: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} +; CHECK: memh(r{{[0-9]+}}+#0) |= r{{[0-9]+}} %0 = load i16, i16* %p, align 2 %or3 = or i16 %0, %x store i16 %or3, i16* %p, align 2 @@ -832,7 +832,7 @@ entry: define void @memop_signed_short_and(i16* nocapture %p, i16 signext %x) nounwind { entry: ; CHECK-LABEL: memop_signed_short_and: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} +; CHECK: memh(r{{[0-9]+}}+#0) &= r{{[0-9]+}} %0 = load i16, i16* %p, align 2 %and3 = and i16 %0, %x store i16 %and3, i16* %p, align 2 @@ -842,7 +842,7 @@ entry: define void @memop_signed_short_clrbit(i16* nocapture %p) nounwind { entry: ; CHECK-LABEL: memop_signed_short_clrbit: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) +; CHECK: memh(r{{[0-9]+}}+#0) = clrbit(#5) %0 = load i16, i16* %p, align 2 %conv2 = zext i16 %0 to i32 %and = and i32 %conv2, 65503 @@ -854,7 +854,7 @@ entry: define void @memop_signed_short_setbit(i16* nocapture %p) nounwind { entry: ; CHECK-LABEL: memop_signed_short_setbit: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) +; CHECK: memh(r{{[0-9]+}}+#0) = setbit(#7) %0 = load i16, i16* %p, align 2 %conv2 = zext i16 %0 to i32 %or = or i32 %conv2, 128 @@ -866,7 +866,7 @@ entry: define void @memop_signed_short_add5_index(i16* nocapture %p, i32 %i) nounwind { entry: ; CHECK-LABEL: memop_signed_short_add5_index: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 +; CHECK: memh(r{{[0-9]+}}+#0) += #5 %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i %0 = load i16, i16* %add.ptr, align 2 %conv2 = zext i16 %0 to i32 @@ -879,7 +879,7 @@ entry: define void @memop_signed_short_add_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind { entry: ; CHECK-LABEL: memop_signed_short_add_index: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} +; CHECK: memh(r{{[0-9]+}}+#0) += r{{[0-9]+}} %conv4 = zext i16 %x to i32 %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i %0 = load i16, i16* %add.ptr, align 2 @@ -893,7 +893,7 @@ entry: define void @memop_signed_short_sub_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind { entry: ; CHECK-LABEL: memop_signed_short_sub_index: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} +; CHECK: memh(r{{[0-9]+}}+#0) -= r{{[0-9]+}} %conv4 = zext i16 %x to i32 %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i %0 = load i16, i16* %add.ptr, align 2 @@ -907,7 +907,7 @@ entry: define void @memop_signed_short_or_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind { entry: ; CHECK-LABEL: memop_signed_short_or_index: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} +; CHECK: memh(r{{[0-9]+}}+#0) |= r{{[0-9]+}} %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i %0 = load i16, i16* %add.ptr, align 2 %or3 = or i16 %0, %x @@ -918,7 +918,7 @@ entry: define void @memop_signed_short_and_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind { entry: ; CHECK-LABEL: memop_signed_short_and_index: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} +; CHECK: memh(r{{[0-9]+}}+#0) &= r{{[0-9]+}} %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i %0 = load i16, i16* %add.ptr, align 2 %and3 = and i16 %0, %x @@ -929,7 +929,7 @@ entry: define void @memop_signed_short_clrbit_index(i16* nocapture %p, i32 %i) nounwind { entry: ; CHECK-LABEL: memop_signed_short_clrbit_index: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) +; CHECK: memh(r{{[0-9]+}}+#0) = clrbit(#5) %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i %0 = load i16, i16* %add.ptr, align 2 %conv2 = zext i16 %0 to i32 @@ -942,7 +942,7 @@ entry: define void @memop_signed_short_setbit_index(i16* nocapture %p, i32 %i) nounwind { entry: ; CHECK-LABEL: memop_signed_short_setbit_index: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) +; CHECK: memh(r{{[0-9]+}}+#0) = setbit(#7) %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i %0 = load i16, i16* %add.ptr, align 2 %conv2 = zext i16 %0 to i32 @@ -955,7 +955,7 @@ entry: define void @memop_signed_short_add5_index5(i16* nocapture %p) nounwind { entry: ; CHECK-LABEL: memop_signed_short_add5_index5: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}#5 +; CHECK: memh(r{{[0-9]+}}+#10) += #5 %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 %0 = load i16, i16* %add.ptr, align 2 %conv2 = zext i16 %0 to i32 @@ -968,7 +968,7 @@ entry: define void @memop_signed_short_add_index5(i16* nocapture %p, i16 signext %x) nounwind { entry: ; CHECK-LABEL: memop_signed_short_add_index5: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}r{{[0-9]+}} +; CHECK: memh(r{{[0-9]+}}+#10) += r{{[0-9]+}} %conv4 = zext i16 %x to i32 %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 %0 = load i16, i16* %add.ptr, align 2 @@ -982,7 +982,7 @@ entry: define void @memop_signed_short_sub_index5(i16* nocapture %p, i16 signext %x) nounwind { entry: ; CHECK-LABEL: memop_signed_short_sub_index5: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}-={{ *}}r{{[0-9]+}} +; CHECK: memh(r{{[0-9]+}}+#10) -= r{{[0-9]+}} %conv4 = zext i16 %x to i32 %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 %0 = load i16, i16* %add.ptr, align 2 @@ -996,7 +996,7 @@ entry: define void @memop_signed_short_or_index5(i16* nocapture %p, i16 signext %x) nounwind { entry: ; CHECK-LABEL: memop_signed_short_or_index5: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}|={{ *}}r{{[0-9]+}} +; CHECK: memh(r{{[0-9]+}}+#10) |= r{{[0-9]+}} %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 %0 = load i16, i16* %add.ptr, align 2 %or3 = or i16 %0, %x @@ -1007,7 +1007,7 @@ entry: define void @memop_signed_short_and_index5(i16* nocapture %p, i16 signext %x) nounwind { entry: ; CHECK-LABEL: memop_signed_short_and_index5: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}&={{ *}}r{{[0-9]+}} +; CHECK: memh(r{{[0-9]+}}+#10) &= r{{[0-9]+}} %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 %0 = load i16, i16* %add.ptr, align 2 %and3 = and i16 %0, %x @@ -1018,7 +1018,7 @@ entry: define void @memop_signed_short_clrbit_index5(i16* nocapture %p) nounwind { entry: ; CHECK-LABEL: memop_signed_short_clrbit_index5: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) +; CHECK: memh(r{{[0-9]+}}+#10) = clrbit(#5) %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 %0 = load i16, i16* %add.ptr, align 2 %conv2 = zext i16 %0 to i32 @@ -1031,7 +1031,7 @@ entry: define void @memop_signed_short_setbit_index5(i16* nocapture %p) nounwind { entry: ; CHECK-LABEL: memop_signed_short_setbit_index5: -; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) +; CHECK: memh(r{{[0-9]+}}+#10) = setbit(#7) %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 %0 = load i16, i16* %add.ptr, align 2 %conv2 = zext i16 %0 to i32 @@ -1044,7 +1044,7 @@ entry: define void @memop_signed_int_add5(i32* nocapture %p) nounwind { entry: ; CHECK-LABEL: memop_signed_int_add5: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 +; CHECK: memw(r{{[0-9]+}}+#0) += #5 %0 = load i32, i32* %p, align 4 %add = add i32 %0, 5 store i32 %add, i32* %p, align 4 @@ -1054,7 +1054,7 @@ entry: define void @memop_signed_int_add(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK-LABEL: memop_signed_int_add: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} +; CHECK: memw(r{{[0-9]+}}+#0) += r{{[0-9]+}} %0 = load i32, i32* %p, align 4 %add = add i32 %0, %x store i32 %add, i32* %p, align 4 @@ -1064,7 +1064,7 @@ entry: define void @memop_signed_int_sub(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK-LABEL: memop_signed_int_sub: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} +; CHECK: memw(r{{[0-9]+}}+#0) -= r{{[0-9]+}} %0 = load i32, i32* %p, align 4 %sub = sub i32 %0, %x store i32 %sub, i32* %p, align 4 @@ -1074,7 +1074,7 @@ entry: define void @memop_signed_int_or(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK-LABEL: memop_signed_int_or: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} +; CHECK: memw(r{{[0-9]+}}+#0) |= r{{[0-9]+}} %0 = load i32, i32* %p, align 4 %or = or i32 %0, %x store i32 %or, i32* %p, align 4 @@ -1084,7 +1084,7 @@ entry: define void @memop_signed_int_and(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK-LABEL: memop_signed_int_and: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} +; CHECK: memw(r{{[0-9]+}}+#0) &= r{{[0-9]+}} %0 = load i32, i32* %p, align 4 %and = and i32 %0, %x store i32 %and, i32* %p, align 4 @@ -1094,7 +1094,7 @@ entry: define void @memop_signed_int_clrbit(i32* nocapture %p) nounwind { entry: ; CHECK-LABEL: memop_signed_int_clrbit: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) +; CHECK: memw(r{{[0-9]+}}+#0) = clrbit(#5) %0 = load i32, i32* %p, align 4 %and = and i32 %0, -33 store i32 %and, i32* %p, align 4 @@ -1104,7 +1104,7 @@ entry: define void @memop_signed_int_setbit(i32* nocapture %p) nounwind { entry: ; CHECK-LABEL: memop_signed_int_setbit: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) +; CHECK: memw(r{{[0-9]+}}+#0) = setbit(#7) %0 = load i32, i32* %p, align 4 %or = or i32 %0, 128 store i32 %or, i32* %p, align 4 @@ -1114,7 +1114,7 @@ entry: define void @memop_signed_int_add5_index(i32* nocapture %p, i32 %i) nounwind { entry: ; CHECK-LABEL: memop_signed_int_add5_index: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 +; CHECK: memw(r{{[0-9]+}}+#0) += #5 %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i %0 = load i32, i32* %add.ptr, align 4 %add = add i32 %0, 5 @@ -1125,7 +1125,7 @@ entry: define void @memop_signed_int_add_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { entry: ; CHECK-LABEL: memop_signed_int_add_index: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} +; CHECK: memw(r{{[0-9]+}}+#0) += r{{[0-9]+}} %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i %0 = load i32, i32* %add.ptr, align 4 %add = add i32 %0, %x @@ -1136,7 +1136,7 @@ entry: define void @memop_signed_int_sub_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { entry: ; CHECK-LABEL: memop_signed_int_sub_index: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} +; CHECK: memw(r{{[0-9]+}}+#0) -= r{{[0-9]+}} %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i %0 = load i32, i32* %add.ptr, align 4 %sub = sub i32 %0, %x @@ -1147,7 +1147,7 @@ entry: define void @memop_signed_int_or_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { entry: ; CHECK-LABEL: memop_signed_int_or_index: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} +; CHECK: memw(r{{[0-9]+}}+#0) |= r{{[0-9]+}} %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i %0 = load i32, i32* %add.ptr, align 4 %or = or i32 %0, %x @@ -1158,7 +1158,7 @@ entry: define void @memop_signed_int_and_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { entry: ; CHECK-LABEL: memop_signed_int_and_index: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} +; CHECK: memw(r{{[0-9]+}}+#0) &= r{{[0-9]+}} %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i %0 = load i32, i32* %add.ptr, align 4 %and = and i32 %0, %x @@ -1169,7 +1169,7 @@ entry: define void @memop_signed_int_clrbit_index(i32* nocapture %p, i32 %i) nounwind { entry: ; CHECK-LABEL: memop_signed_int_clrbit_index: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) +; CHECK: memw(r{{[0-9]+}}+#0) = clrbit(#5) %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i %0 = load i32, i32* %add.ptr, align 4 %and = and i32 %0, -33 @@ -1180,7 +1180,7 @@ entry: define void @memop_signed_int_setbit_index(i32* nocapture %p, i32 %i) nounwind { entry: ; CHECK-LABEL: memop_signed_int_setbit_index: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) +; CHECK: memw(r{{[0-9]+}}+#0) = setbit(#7) %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i %0 = load i32, i32* %add.ptr, align 4 %or = or i32 %0, 128 @@ -1191,7 +1191,7 @@ entry: define void @memop_signed_int_add5_index5(i32* nocapture %p) nounwind { entry: ; CHECK-LABEL: memop_signed_int_add5_index5: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}#5 +; CHECK: memw(r{{[0-9]+}}+#20) += #5 %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 %0 = load i32, i32* %add.ptr, align 4 %add = add i32 %0, 5 @@ -1202,7 +1202,7 @@ entry: define void @memop_signed_int_add_index5(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK-LABEL: memop_signed_int_add_index5: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}r{{[0-9]+}} +; CHECK: memw(r{{[0-9]+}}+#20) += r{{[0-9]+}} %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 %0 = load i32, i32* %add.ptr, align 4 %add = add i32 %0, %x @@ -1213,7 +1213,7 @@ entry: define void @memop_signed_int_sub_index5(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK-LABEL: memop_signed_int_sub_index5: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}-={{ *}}r{{[0-9]+}} +; CHECK: memw(r{{[0-9]+}}+#20) -= r{{[0-9]+}} %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 %0 = load i32, i32* %add.ptr, align 4 %sub = sub i32 %0, %x @@ -1224,7 +1224,7 @@ entry: define void @memop_signed_int_or_index5(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK-LABEL: memop_signed_int_or_index5: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}|={{ *}}r{{[0-9]+}} +; CHECK: memw(r{{[0-9]+}}+#20) |= r{{[0-9]+}} %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 %0 = load i32, i32* %add.ptr, align 4 %or = or i32 %0, %x @@ -1235,7 +1235,7 @@ entry: define void @memop_signed_int_and_index5(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK-LABEL: memop_signed_int_and_index5: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}&={{ *}}r{{[0-9]+}} +; CHECK: memw(r{{[0-9]+}}+#20) &= r{{[0-9]+}} %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 %0 = load i32, i32* %add.ptr, align 4 %and = and i32 %0, %x @@ -1246,7 +1246,7 @@ entry: define void @memop_signed_int_clrbit_index5(i32* nocapture %p) nounwind { entry: ; CHECK-LABEL: memop_signed_int_clrbit_index5: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) +; CHECK: memw(r{{[0-9]+}}+#20) = clrbit(#5) %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 %0 = load i32, i32* %add.ptr, align 4 %and = and i32 %0, -33 @@ -1257,7 +1257,7 @@ entry: define void @memop_signed_int_setbit_index5(i32* nocapture %p) nounwind { entry: ; CHECK-LABEL: memop_signed_int_setbit_index5: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) +; CHECK: memw(r{{[0-9]+}}+#20) = setbit(#7) %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 %0 = load i32, i32* %add.ptr, align 4 %or = or i32 %0, 128 @@ -1268,7 +1268,7 @@ entry: define void @memop_unsigned_int_add5(i32* nocapture %p) nounwind { entry: ; CHECK-LABEL: memop_unsigned_int_add5: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 +; CHECK: memw(r{{[0-9]+}}+#0) += #5 %0 = load i32, i32* %p, align 4 %add = add nsw i32 %0, 5 store i32 %add, i32* %p, align 4 @@ -1278,7 +1278,7 @@ entry: define void @memop_unsigned_int_add(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK-LABEL: memop_unsigned_int_add: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} +; CHECK: memw(r{{[0-9]+}}+#0) += r{{[0-9]+}} %0 = load i32, i32* %p, align 4 %add = add nsw i32 %0, %x store i32 %add, i32* %p, align 4 @@ -1288,7 +1288,7 @@ entry: define void @memop_unsigned_int_sub(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK-LABEL: memop_unsigned_int_sub: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} +; CHECK: memw(r{{[0-9]+}}+#0) -= r{{[0-9]+}} %0 = load i32, i32* %p, align 4 %sub = sub nsw i32 %0, %x store i32 %sub, i32* %p, align 4 @@ -1298,7 +1298,7 @@ entry: define void @memop_unsigned_int_or(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK-LABEL: memop_unsigned_int_or: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} +; CHECK: memw(r{{[0-9]+}}+#0) |= r{{[0-9]+}} %0 = load i32, i32* %p, align 4 %or = or i32 %0, %x store i32 %or, i32* %p, align 4 @@ -1308,7 +1308,7 @@ entry: define void @memop_unsigned_int_and(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK-LABEL: memop_unsigned_int_and: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} +; CHECK: memw(r{{[0-9]+}}+#0) &= r{{[0-9]+}} %0 = load i32, i32* %p, align 4 %and = and i32 %0, %x store i32 %and, i32* %p, align 4 @@ -1318,7 +1318,7 @@ entry: define void @memop_unsigned_int_clrbit(i32* nocapture %p) nounwind { entry: ; CHECK-LABEL: memop_unsigned_int_clrbit: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) +; CHECK: memw(r{{[0-9]+}}+#0) = clrbit(#5) %0 = load i32, i32* %p, align 4 %and = and i32 %0, -33 store i32 %and, i32* %p, align 4 @@ -1328,7 +1328,7 @@ entry: define void @memop_unsigned_int_setbit(i32* nocapture %p) nounwind { entry: ; CHECK-LABEL: memop_unsigned_int_setbit: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) +; CHECK: memw(r{{[0-9]+}}+#0) = setbit(#7) %0 = load i32, i32* %p, align 4 %or = or i32 %0, 128 store i32 %or, i32* %p, align 4 @@ -1338,7 +1338,7 @@ entry: define void @memop_unsigned_int_add5_index(i32* nocapture %p, i32 %i) nounwind { entry: ; CHECK-LABEL: memop_unsigned_int_add5_index: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 +; CHECK: memw(r{{[0-9]+}}+#0) += #5 %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i %0 = load i32, i32* %add.ptr, align 4 %add = add nsw i32 %0, 5 @@ -1349,7 +1349,7 @@ entry: define void @memop_unsigned_int_add_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { entry: ; CHECK-LABEL: memop_unsigned_int_add_index: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} +; CHECK: memw(r{{[0-9]+}}+#0) += r{{[0-9]+}} %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i %0 = load i32, i32* %add.ptr, align 4 %add = add nsw i32 %0, %x @@ -1360,7 +1360,7 @@ entry: define void @memop_unsigned_int_sub_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { entry: ; CHECK-LABEL: memop_unsigned_int_sub_index: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} +; CHECK: memw(r{{[0-9]+}}+#0) -= r{{[0-9]+}} %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i %0 = load i32, i32* %add.ptr, align 4 %sub = sub nsw i32 %0, %x @@ -1371,7 +1371,7 @@ entry: define void @memop_unsigned_int_or_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { entry: ; CHECK-LABEL: memop_unsigned_int_or_index: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} +; CHECK: memw(r{{[0-9]+}}+#0) |= r{{[0-9]+}} %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i %0 = load i32, i32* %add.ptr, align 4 %or = or i32 %0, %x @@ -1382,7 +1382,7 @@ entry: define void @memop_unsigned_int_and_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { entry: ; CHECK-LABEL: memop_unsigned_int_and_index: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} +; CHECK: memw(r{{[0-9]+}}+#0) &= r{{[0-9]+}} %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i %0 = load i32, i32* %add.ptr, align 4 %and = and i32 %0, %x @@ -1393,7 +1393,7 @@ entry: define void @memop_unsigned_int_clrbit_index(i32* nocapture %p, i32 %i) nounwind { entry: ; CHECK-LABEL: memop_unsigned_int_clrbit_index: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) +; CHECK: memw(r{{[0-9]+}}+#0) = clrbit(#5) %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i %0 = load i32, i32* %add.ptr, align 4 %and = and i32 %0, -33 @@ -1404,7 +1404,7 @@ entry: define void @memop_unsigned_int_setbit_index(i32* nocapture %p, i32 %i) nounwind { entry: ; CHECK-LABEL: memop_unsigned_int_setbit_index: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) +; CHECK: memw(r{{[0-9]+}}+#0) = setbit(#7) %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i %0 = load i32, i32* %add.ptr, align 4 %or = or i32 %0, 128 @@ -1415,7 +1415,7 @@ entry: define void @memop_unsigned_int_add5_index5(i32* nocapture %p) nounwind { entry: ; CHECK-LABEL: memop_unsigned_int_add5_index5: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}#5 +; CHECK: memw(r{{[0-9]+}}+#20) += #5 %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 %0 = load i32, i32* %add.ptr, align 4 %add = add nsw i32 %0, 5 @@ -1426,7 +1426,7 @@ entry: define void @memop_unsigned_int_add_index5(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK-LABEL: memop_unsigned_int_add_index5: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}r{{[0-9]+}} +; CHECK: memw(r{{[0-9]+}}+#20) += r{{[0-9]+}} %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 %0 = load i32, i32* %add.ptr, align 4 %add = add nsw i32 %0, %x @@ -1437,7 +1437,7 @@ entry: define void @memop_unsigned_int_sub_index5(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK-LABEL: memop_unsigned_int_sub_index5: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}-={{ *}}r{{[0-9]+}} +; CHECK: memw(r{{[0-9]+}}+#20) -= r{{[0-9]+}} %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 %0 = load i32, i32* %add.ptr, align 4 %sub = sub nsw i32 %0, %x @@ -1448,7 +1448,7 @@ entry: define void @memop_unsigned_int_or_index5(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK-LABEL: memop_unsigned_int_or_index5: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}|={{ *}}r{{[0-9]+}} +; CHECK: memw(r{{[0-9]+}}+#20) |= r{{[0-9]+}} %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 %0 = load i32, i32* %add.ptr, align 4 %or = or i32 %0, %x @@ -1459,7 +1459,7 @@ entry: define void @memop_unsigned_int_and_index5(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK-LABEL: memop_unsigned_int_and_index5: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}&={{ *}}r{{[0-9]+}} +; CHECK: memw(r{{[0-9]+}}+#20) &= r{{[0-9]+}} %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 %0 = load i32, i32* %add.ptr, align 4 %and = and i32 %0, %x @@ -1470,7 +1470,7 @@ entry: define void @memop_unsigned_int_clrbit_index5(i32* nocapture %p) nounwind { entry: ; CHECK-LABEL: memop_unsigned_int_clrbit_index5: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) +; CHECK: memw(r{{[0-9]+}}+#20) = clrbit(#5) %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 %0 = load i32, i32* %add.ptr, align 4 %and = and i32 %0, -33 @@ -1481,7 +1481,7 @@ entry: define void @memop_unsigned_int_setbit_index5(i32* nocapture %p) nounwind { entry: ; CHECK-LABEL: memop_unsigned_int_setbit_index5: -; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) +; CHECK: memw(r{{[0-9]+}}+#20) = setbit(#7) %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 %0 = load i32, i32* %add.ptr, align 4 %or = or i32 %0, 128 |
