diff options
Diffstat (limited to 'llvm/test/CodeGen/ARM/GlobalISel/thumb-select-load-store.mir')
| -rw-r--r-- | llvm/test/CodeGen/ARM/GlobalISel/thumb-select-load-store.mir | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-load-store.mir b/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-load-store.mir index ec64c8a2c1e..0a6ddb352a6 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-load-store.mir +++ b/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-load-store.mir @@ -5,6 +5,8 @@ define void @test_s32() { ret void } define void @test_gep() { ret void } + + define void @test_load_from_stack() { ret void } ... --- name: test_s8 @@ -114,3 +116,50 @@ body: | BX_RET 14, $noreg, implicit $r0 ; CHECK: BX_RET 14, $noreg, implicit $r0 ... +--- +name: test_load_from_stack +# CHECK-LABEL: name: test_load_from_stack +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: gprb } + - { id: 1, class: gprb } + - { id: 2, class: gprb } + - { id: 3, class: gprb } + - { id: 4, class: gprb } +fixedStack: + - { id: 0, offset: 0, size: 1, alignment: 4, isImmutable: true, isAliased: false } + - { id: 1, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false } + - { id: 2, offset: 8, size: 4, alignment: 4, isImmutable: true, isAliased: false } +# CHECK-DAG: id: [[FI1:[0-9]+]], type: default, offset: 0, size: 1 +# CHECK-DAG: id: [[FI32:[0-9]+]], type: default, offset: 8 +body: | + bb.0: + liveins: $r0, $r1, $r2, $r3 + + %0(p0) = G_FRAME_INDEX %fixed-stack.2 + ; CHECK: [[FI32VREG:%[0-9]+]]:gprnopc = t2ADDri %fixed-stack.[[FI32]], 0, 14, $noreg, $noreg + + %1(s32) = G_LOAD %0(p0) :: (load 4) + ; CHECK: [[LD32VREG:%[0-9]+]]:gpr = t2LDRi12 [[FI32VREG]], 0, 14, $noreg + + $r0 = COPY %1 + ; CHECK: $r0 = COPY [[LD32VREG]] + + %2(p0) = G_FRAME_INDEX %fixed-stack.0 + ; CHECK: [[FI1VREG:%[0-9]+]]:gprnopc = t2ADDri %fixed-stack.[[FI1]], 0, 14, $noreg, $noreg + + %3(s1) = G_LOAD %2(p0) :: (load 1) + ; CHECK: [[LD1VREG:%[0-9]+]]:gprnopc = t2LDRBi12 [[FI1VREG]], 0, 14, $noreg + + %4(s32) = G_ANYEXT %3(s1) + ; CHECK: [[RES:%[0-9]+]]:gpr = COPY [[LD1VREG]] + + $r0 = COPY %4 + ; CHECK: $r0 = COPY [[RES]] + + BX_RET 14, $noreg + ; CHECK: BX_RET 14, $noreg +... |

