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-rw-r--r--llvm/test/CodeGen/AMDGPU/detect-dead-lanes.mir6
-rw-r--r--llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir20
-rw-r--r--llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir3
-rw-r--r--llvm/test/CodeGen/AMDGPU/liveness.mir2
-rw-r--r--llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir20
-rw-r--r--llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir1
-rw-r--r--llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir3
-rw-r--r--llvm/test/CodeGen/AMDGPU/subreg-intervals.mir3
-rw-r--r--llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir6
9 files changed, 0 insertions, 64 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/detect-dead-lanes.mir b/llvm/test/CodeGen/AMDGPU/detect-dead-lanes.mir
index 32e6f7cc0cd..3148b9b8ff9 100644
--- a/llvm/test/CodeGen/AMDGPU/detect-dead-lanes.mir
+++ b/llvm/test/CodeGen/AMDGPU/detect-dead-lanes.mir
@@ -294,7 +294,6 @@ registers:
- { id: 5, class: sreg_128 }
body: |
bb.0:
- successors: %bb.1
S_NOP 0, implicit-def %0
S_NOP 0, implicit-def %1
S_NOP 0, implicit-def %2
@@ -302,7 +301,6 @@ body: |
S_BRANCH %bb.1
bb.1:
- successors: %bb.1, %bb.2
%4 = PHI %3, %bb.0, %5, %bb.1
; let's swiffle some lanes around for fun...
@@ -348,7 +346,6 @@ registers:
- { id: 6, class: sreg_128 }
body: |
bb.0:
- successors: %bb.1
S_NOP 0, implicit-def %0
S_NOP 0, implicit-def %1
S_NOP 0, implicit-def dead %2
@@ -357,7 +354,6 @@ body: |
S_BRANCH %bb.1
bb.1:
- successors: %bb.1, %bb.2
%5 = PHI %4, %bb.0, %6, %bb.1
; rotate lanes, but skip sub2 lane...
@@ -396,13 +392,11 @@ registers:
- { id: 3, class: sreg_128 }
body: |
bb.0:
- successors: %bb.1
S_NOP 0, implicit-def %0
%1 = REG_SEQUENCE %0, %subreg.sub0
S_BRANCH %bb.1
bb.1:
- successors: %bb.1, %bb.2
%2 = PHI %1, %bb.0, %3, %bb.1
; rotate subreg lanes, skipping sub1
diff --git a/llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir b/llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir
index 1479303712d..c6fe6debd22 100644
--- a/llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir
+++ b/llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir
@@ -77,19 +77,16 @@ name: div_fmas
body: |
bb.0:
- successors: %bb.1
%vcc = S_MOV_B64 0
%vgpr0 = V_DIV_FMAS_F32 0, %vgpr1, 0, %vgpr2, 0, %vgpr3, 0, 0, implicit %vcc, implicit %exec
S_BRANCH %bb.1
bb.1:
- successors: %bb.2
implicit %vcc = V_CMP_EQ_I32_e32 %vgpr1, %vgpr2, implicit %exec
%vgpr0 = V_DIV_FMAS_F32 0, %vgpr1, 0, %vgpr2, 0, %vgpr3, 0, 0, implicit %vcc, implicit %exec
S_BRANCH %bb.2
bb.2:
- successors: %bb.3
%vcc = V_CMP_EQ_I32_e64 %vgpr1, %vgpr2, implicit %exec
%vgpr0 = V_DIV_FMAS_F32 0, %vgpr1, 0, %vgpr2, 0, %vgpr3, 0, 0, implicit %vcc, implicit %exec
S_BRANCH %bb.3
@@ -130,19 +127,16 @@ name: s_getreg
body: |
bb.0:
- successors: %bb.1
S_SETREG_B32 %sgpr0, 1
%sgpr1 = S_GETREG_B32 1
S_BRANCH %bb.1
bb.1:
- successors: %bb.2
S_SETREG_IMM32_B32 0, 1
%sgpr1 = S_GETREG_B32 1
S_BRANCH %bb.2
bb.2:
- successors: %bb.3
S_SETREG_B32 %sgpr0, 1
%sgpr1 = S_MOV_B32 0
%sgpr2 = S_GETREG_B32 1
@@ -178,13 +172,11 @@ name: s_setreg
body: |
bb.0:
- successors: %bb.1
S_SETREG_B32 %sgpr0, 1
S_SETREG_B32 %sgpr1, 1
S_BRANCH %bb.1
bb.1:
- successors: %bb.2
S_SETREG_B32 %sgpr0, 64
S_SETREG_B32 %sgpr1, 128
S_BRANCH %bb.2
@@ -237,7 +229,6 @@ name: vmem_gt_8dw_store
body: |
bb.0:
- successors: %bb.1
BUFFER_STORE_DWORD_OFFSET %vgpr3, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4, 0, 0, 0, 0, implicit %exec
%vgpr3 = V_MOV_B32_e32 0, implicit %exec
BUFFER_STORE_DWORDX3_OFFSET %vgpr2_vgpr3_vgpr4, %sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit %exec
@@ -310,19 +301,16 @@ name: readwrite_lane
body: |
bb.0:
- successors: %bb.1
%vgpr0,%sgpr0_sgpr1 = V_ADD_I32_e64 %vgpr1, %vgpr2, implicit %vcc, implicit %exec
%sgpr4 = V_READLANE_B32 %vgpr4, %sgpr0
S_BRANCH %bb.1
bb.1:
- successors: %bb.2
%vgpr0,%sgpr0_sgpr1 = V_ADD_I32_e64 %vgpr1, %vgpr2, implicit %vcc, implicit %exec
%vgpr4 = V_WRITELANE_B32 %sgpr0, %sgpr0
S_BRANCH %bb.2
bb.2:
- successors: %bb.3
%vgpr0,implicit %vcc = V_ADD_I32_e32 %vgpr1, %vgpr2, implicit %vcc, implicit %exec
%sgpr4 = V_READLANE_B32 %vgpr4, %vcc_lo
S_BRANCH %bb.3
@@ -352,7 +340,6 @@ name: rfe
body: |
bb.0:
- successors: %bb.1
S_SETREG_B32 %sgpr0, 3
S_RFE_B64 %sgpr2_sgpr3
S_BRANCH %bb.1
@@ -382,7 +369,6 @@ name: s_mov_fed_b32
body: |
bb.0:
- successors: %bb.1
%sgpr0 = S_MOV_FED_B32 %sgpr0
%sgpr0 = S_MOV_B32 %sgpr0
S_BRANCH %bb.1
@@ -423,19 +409,16 @@ name: s_movrel
body: |
bb.0:
- successors: %bb.1
%m0 = S_MOV_B32 0
%sgpr0 = S_MOVRELS_B32 %sgpr0, implicit %m0
S_BRANCH %bb.1
bb.1:
- successors: %bb.2
%m0 = S_MOV_B32 0
%sgpr0_sgpr1 = S_MOVRELS_B64 %sgpr0_sgpr1, implicit %m0
S_BRANCH %bb.2
bb.2:
- successors: %bb.3
%m0 = S_MOV_B32 0
%sgpr0 = S_MOVRELD_B32 %sgpr0, implicit %m0
S_BRANCH %bb.3
@@ -475,19 +458,16 @@ name: v_interp
body: |
bb.0:
- successors: %bb.1
%m0 = S_MOV_B32 0
%vgpr0 = V_INTERP_P1_F32 %vgpr0, 0, 0, implicit %m0, implicit %exec
S_BRANCH %bb.1
bb.1:
- successors: %bb.2
%m0 = S_MOV_B32 0
%vgpr0 = V_INTERP_P2_F32 %vgpr0, %vgpr1, 0, 0, implicit %m0, implicit %exec
S_BRANCH %bb.2
bb.2:
- successors: %bb.3
%m0 = S_MOV_B32 0
%vgpr0 = V_INTERP_P1_F32_16bank %vgpr0, 0, 0, implicit %m0, implicit %exec
S_BRANCH %bb.3
diff --git a/llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir b/llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir
index bc1dafe0ea1..67642282f75 100644
--- a/llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir
+++ b/llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir
@@ -53,7 +53,6 @@ frameInfo:
hasMustTailInVarArgFunc: false
body: |
bb.0.entry:
- successors: %bb.2.if, %bb.1.else
liveins: %sgpr0_sgpr1
%sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
@@ -62,7 +61,6 @@ body: |
S_CBRANCH_VCCNZ %bb.2.if, implicit undef %vcc
bb.1.else:
- successors: %bb.3.done
liveins: %sgpr6, %sgpr7, %sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
%vgpr0 = V_MOV_B32_e32 100, implicit %exec
@@ -71,7 +69,6 @@ body: |
S_BRANCH %bb.3.done
bb.2.if:
- successors: %bb.3.done
liveins: %sgpr6, %sgpr7, %sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
%vgpr0 = V_MOV_B32_e32 9, implicit %exec
diff --git a/llvm/test/CodeGen/AMDGPU/liveness.mir b/llvm/test/CodeGen/AMDGPU/liveness.mir
index 48762e3f2ab..6fd8466492d 100644
--- a/llvm/test/CodeGen/AMDGPU/liveness.mir
+++ b/llvm/test/CodeGen/AMDGPU/liveness.mir
@@ -16,13 +16,11 @@ registers:
- { id: 0, class: sreg_64 }
body: |
bb.0:
- successors: %bb.1, %bb.2
S_NOP 0, implicit-def undef %0.sub0
S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
S_BRANCH %bb.2
bb.1:
- successors: %bb.2
S_NOP 0, implicit-def %0.sub1
S_NOP 0, implicit %0.sub1
S_BRANCH %bb.2
diff --git a/llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir b/llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir
index 2de6b59e59e..b5dc9d9dac8 100644
--- a/llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir
+++ b/llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir
@@ -176,7 +176,6 @@ frameInfo:
hasMustTailInVarArgFunc: false
body: |
bb.0.main_body:
- successors: %bb.1.if, %bb.2.end
liveins: %vgpr0
%sgpr0_sgpr1 = COPY %exec
@@ -189,7 +188,6 @@ body: |
S_BRANCH %bb.1.if
bb.1.if:
- successors: %bb.2.end
liveins: %sgpr0_sgpr1
%sgpr7 = S_MOV_B32 61440
@@ -236,7 +234,6 @@ frameInfo:
hasMustTailInVarArgFunc: false
body: |
bb.0.main_body:
- successors: %bb.1.if, %bb.2.end
liveins: %vgpr0
%sgpr0_sgpr1 = COPY %exec
@@ -248,7 +245,6 @@ body: |
S_BRANCH %bb.1.if
bb.1.if:
- successors: %bb.2.end
liveins: %sgpr0_sgpr1
%sgpr7 = S_MOV_B32 61440
@@ -295,7 +291,6 @@ frameInfo:
hasMustTailInVarArgFunc: false
body: |
bb.0.main_body:
- successors: %bb.1.if, %bb.2.end
liveins: %vgpr0
%sgpr0_sgpr1 = COPY %exec
@@ -307,7 +302,6 @@ body: |
S_BRANCH %bb.1.if
bb.1.if:
- successors: %bb.2.end
liveins: %sgpr0_sgpr1
%sgpr7 = S_MOV_B32 61440
@@ -356,7 +350,6 @@ frameInfo:
hasMustTailInVarArgFunc: false
body: |
bb.0.main_body:
- successors: %bb.1.if, %bb.2.end
liveins: %vgpr0
%sgpr0_sgpr1 = COPY %exec
@@ -370,7 +363,6 @@ body: |
S_BRANCH %bb.1.if
bb.1.if:
- successors: %bb.2.end
liveins: %sgpr0_sgpr1
%sgpr7 = S_MOV_B32 61440
@@ -418,7 +410,6 @@ frameInfo:
hasMustTailInVarArgFunc: false
body: |
bb.0.main_body:
- successors: %bb.1.if, %bb.2.end
liveins: %vgpr0
%sgpr6 = S_MOV_B32 -1
@@ -433,7 +424,6 @@ body: |
S_BRANCH %bb.1.if
bb.1.if:
- successors: %bb.2.end
liveins: %sgpr0_sgpr1 , %sgpr4_sgpr5_sgpr6_sgpr7
%vgpr0 = BUFFER_LOAD_DWORD_OFFSET %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from `i32 addrspace(1)* undef`)
@@ -480,7 +470,6 @@ frameInfo:
hasMustTailInVarArgFunc: false
body: |
bb.0.main_body:
- successors: %bb.1.if, %bb.2.end
liveins: %vgpr0
%sgpr0_sgpr1 = COPY %exec
@@ -494,7 +483,6 @@ body: |
S_BRANCH %bb.1.if
bb.1.if:
- successors: %bb.2.end
liveins: %sgpr0_sgpr1
%sgpr7 = S_MOV_B32 61440
@@ -544,7 +532,6 @@ frameInfo:
hasMustTailInVarArgFunc: false
body: |
bb.0.main_body:
- successors: %bb.1.if, %bb.2.end
liveins: %vgpr0
%sgpr0_sgpr1 = COPY %exec
@@ -557,7 +544,6 @@ body: |
S_BRANCH %bb.1.if
bb.1.if:
- successors: %bb.2.end
liveins: %sgpr0_sgpr1, %sgpr2_sgpr3
S_SLEEP 0, implicit %sgpr2_sgpr3
%sgpr7 = S_MOV_B32 61440
@@ -606,7 +592,6 @@ frameInfo:
hasMustTailInVarArgFunc: false
body: |
bb.0.main_body:
- successors: %bb.1.if, %bb.2.end
liveins: %vgpr0
%sgpr0_sgpr1 = COPY %exec
@@ -618,7 +603,6 @@ body: |
S_BRANCH %bb.1.if
bb.1.if:
- successors: %bb.2.end
liveins: %sgpr0_sgpr1
%sgpr7 = S_MOV_B32 61440
@@ -665,7 +649,6 @@ frameInfo:
hasMustTailInVarArgFunc: false
body: |
bb.0.main_body:
- successors: %bb.1.if, %bb.2.end
liveins: %vgpr0
%sgpr0_sgpr1 = COPY %exec
@@ -677,7 +660,6 @@ body: |
S_BRANCH %bb.1.if
bb.1.if:
- successors: %bb.2.end
liveins: %sgpr0_sgpr1
%sgpr7 = S_MOV_B32 61440
@@ -724,7 +706,6 @@ frameInfo:
hasMustTailInVarArgFunc: false
body: |
bb.0.main_body:
- successors: %bb.1.if, %bb.2.end
liveins: %vgpr0
%sgpr0_sgpr1 = COPY %exec
@@ -736,7 +717,6 @@ body: |
S_BRANCH %bb.1.if
bb.1.if:
- successors: %bb.2.end
liveins: %sgpr0_sgpr1
%sgpr7 = S_MOV_B32 61440
diff --git a/llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir b/llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir
index fc2e4426ba4..31ad26e7697 100644
--- a/llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir
+++ b/llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir
@@ -49,7 +49,6 @@ registers:
- { id: 1, class: sreg_128 }
body: |
bb.0:
- successors: %bb.1, %bb.2
S_NOP 0, implicit-def undef %0.sub2
S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
S_BRANCH %bb.2
diff --git a/llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir b/llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir
index 20052e865a5..18176de5379 100644
--- a/llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir
+++ b/llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir
@@ -20,12 +20,10 @@ body: |
; GCN: V_ADD_I32
bb.0:
liveins: %vgpr0
- successors: %bb.1
%7 = COPY %vgpr0
%8 = S_MOV_B32 0
bb.1:
- successors: %bb.1, %bb.2
%0 = PHI %8, %bb.0, %0, %bb.1, %2, %bb.2
%9 = V_MOV_B32_e32 9, implicit %exec
%10 = V_CMP_EQ_U32_e64 %7, %9, implicit %exec
@@ -33,7 +31,6 @@ body: |
S_BRANCH %bb.1
bb.2:
- successors: %bb.1
SI_END_CF %1, implicit-def %exec, implicit-def %scc, implicit %exec
%11 = S_MOV_B32 1
%2 = S_ADD_I32 %0, %11, implicit-def %scc
diff --git a/llvm/test/CodeGen/AMDGPU/subreg-intervals.mir b/llvm/test/CodeGen/AMDGPU/subreg-intervals.mir
index c477fe9bc6d..62816da25b2 100644
--- a/llvm/test/CodeGen/AMDGPU/subreg-intervals.mir
+++ b/llvm/test/CodeGen/AMDGPU/subreg-intervals.mir
@@ -31,17 +31,14 @@ registers:
- { id: 0, class: sreg_64 }
body: |
bb.0:
- successors: %bb.1, %bb.2
S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
S_BRANCH %bb.2
bb.1:
- successors: %bb.3
S_NOP 0, implicit-def undef %0.sub0
S_BRANCH %bb.3
bb.2:
- successors: %bb.3
S_NOP 0, implicit-def %0
S_BRANCH %bb.3
diff --git a/llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir b/llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
index 5e5465800c3..6eb937e71b1 100644
--- a/llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
+++ b/llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
@@ -75,7 +75,6 @@ frameInfo:
hasMustTailInVarArgFunc: false
body: |
bb.0.entry:
- successors: %bb.2.if, %bb.1.else
liveins: %sgpr0_sgpr1
%sgpr2 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 9, 0 :: (non-temporal dereferenceable invariant load 4 from `float addrspace(2)* undef`)
@@ -86,7 +85,6 @@ body: |
S_CBRANCH_VCCZ %bb.1.else, implicit killed %vcc
bb.2.if:
- successors: %bb.3.done
liveins: %sgpr6, %sgpr7, %sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
%vgpr0 = V_MOV_B32_e32 9, implicit %exec
@@ -95,7 +93,6 @@ body: |
S_BRANCH %bb.3.done
bb.1.else:
- successors: %bb.3.done
liveins: %sgpr6, %sgpr7, %sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
%vgpr0 = V_MOV_B32_e32 100, implicit %exec
@@ -141,7 +138,6 @@ frameInfo:
hasMustTailInVarArgFunc: false
body: |
bb.0.entry:
- successors: %bb.2.if, %bb.1.else
liveins: %sgpr0_sgpr1
%sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
@@ -150,7 +146,6 @@ body: |
S_CBRANCH_VCCZ %bb.1.else, implicit undef %vcc
bb.2.if:
- successors: %bb.3.done
liveins: %sgpr6, %sgpr7, %sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
%vgpr0 = V_MOV_B32_e32 9, implicit %exec
@@ -159,7 +154,6 @@ body: |
S_BRANCH %bb.3.done
bb.1.else:
- successors: %bb.3.done
liveins: %sgpr6, %sgpr7, %sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
%vgpr0 = V_MOV_B32_e32 100, implicit %exec
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