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-rw-r--r--llvm/test/CodeGen/AMDGPU/udivrem.ll102
1 files changed, 51 insertions, 51 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/udivrem.ll b/llvm/test/CodeGen/AMDGPU/udivrem.ll
index b89f3268976..08b764824ca 100644
--- a/llvm/test/CodeGen/AMDGPU/udivrem.ll
+++ b/llvm/test/CodeGen/AMDGPU/udivrem.ll
@@ -30,24 +30,24 @@
; SI: v_rcp_iflag_f32_e32 [[RCP:v[0-9]+]]
; SI-DAG: v_mul_hi_u32 [[RCP_HI:v[0-9]+]], [[RCP]]
; SI-DAG: v_mul_lo_i32 [[RCP_LO:v[0-9]+]], [[RCP]]
-; SI-DAG: v_sub_i32_e32 [[NEG_RCP_LO:v[0-9]+]], vcc, 0, [[RCP_LO]]
+; SI-DAG: v_sub_{{[iu]}}32_e32 [[NEG_RCP_LO:v[0-9]+]], vcc, 0, [[RCP_LO]]
; SI: v_cndmask_b32_e64
; SI: v_mul_hi_u32 [[E:v[0-9]+]], {{v[0-9]+}}, [[RCP]]
-; SI-DAG: v_add_i32_e32 [[RCP_A_E:v[0-9]+]], vcc, [[E]], [[RCP]]
-; SI-DAG: v_subrev_i32_e32 [[RCP_S_E:v[0-9]+]], vcc, [[E]], [[RCP]]
+; SI-DAG: v_add_{{[iu]}}32_e32 [[RCP_A_E:v[0-9]+]], vcc, [[E]], [[RCP]]
+; SI-DAG: v_subrev_{{[iu]}}32_e32 [[RCP_S_E:v[0-9]+]], vcc, [[E]], [[RCP]]
; SI: v_cndmask_b32_e64
; SI: v_mul_hi_u32 [[Quotient:v[0-9]+]]
; SI: v_mul_lo_i32 [[Num_S_Remainder:v[0-9]+]]
-; SI-DAG: v_add_i32_e32 [[Quotient_A_One:v[0-9]+]], vcc, 1, [[Quotient]]
-; SI-DAG: v_sub_i32_e32 [[Remainder:v[0-9]+]], vcc, {{[vs][0-9]+}}, [[Num_S_Remainder]]
+; SI-DAG: v_add_{{[iu]}}32_e32 [[Quotient_A_One:v[0-9]+]], vcc, 1, [[Quotient]]
+; SI-DAG: v_sub_{{[iu]}}32_e32 [[Remainder:v[0-9]+]], vcc, {{[vs][0-9]+}}, [[Num_S_Remainder]]
; SI-DAG: v_cndmask_b32_e64
; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_subrev_i32_e32 [[Quotient_S_One:v[0-9]+]],
-; SI-DAG: v_subrev_i32_e32 [[Remainder_S_Den:v[0-9]+]],
+; SI-DAG: v_subrev_{{[iu]}}32_e32 [[Quotient_S_One:v[0-9]+]],
+; SI-DAG: v_subrev_{{[iu]}}32_e32 [[Remainder_S_Den:v[0-9]+]],
; SI: v_and_b32_e32 [[Tmp1:v[0-9]+]]
; SI-DAG: v_cndmask_b32_e64
; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_add_i32_e32 [[Remainder_A_Den:v[0-9]+]],
+; SI-DAG: v_add_{{[iu]}}32_e32 [[Remainder_A_Den:v[0-9]+]],
; SI-DAG: v_cndmask_b32_e64
; SI-DAG: v_cndmask_b32_e64
; SI: s_endpgm
@@ -114,47 +114,47 @@ define amdgpu_kernel void @test_udivrem(i32 addrspace(1)* %out0, i32 addrspace(1
; SI-DAG: v_rcp_iflag_f32_e32
; SI-DAG: v_mul_hi_u32
; SI-DAG: v_mul_lo_i32
-; SI-DAG: v_sub_i32_e32
+; SI-DAG: v_sub_{{[iu]}}32_e32
; SI-DAG: v_cndmask_b32_e64
; SI-DAG: v_mul_hi_u32
-; SI-DAG: v_add_i32_e32
-; SI-DAG: v_subrev_i32_e32
+; SI-DAG: v_add_{{[iu]}}32_e32
+; SI-DAG: v_subrev_{{[iu]}}32_e32
; SI-DAG: v_cndmask_b32_e64
; SI-DAG: v_mul_hi_u32
; SI-DAG: v_mul_lo_i32
-; SI-DAG: v_subrev_i32_e32
+; SI-DAG: v_subrev_{{[iu]}}32_e32
; SI-DAG: v_cndmask_b32_e64
; SI-DAG: v_cndmask_b32_e64
; SI-DAG: v_and_b32_e32
-; SI-DAG: v_add_i32_e32
-; SI-DAG: v_subrev_i32_e32
+; SI-DAG: v_add_{{[iu]}}32_e32
+; SI-DAG: v_subrev_{{[iu]}}32_e32
; SI-DAG: v_cndmask_b32_e64
; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_add_i32_e32
-; SI-DAG: v_subrev_i32_e32
+; SI-DAG: v_add_{{[iu]}}32_e32
+; SI-DAG: v_subrev_{{[iu]}}32_e32
; SI-DAG: v_cndmask_b32_e64
; SI-DAG: v_cndmask_b32_e64
; SI-DAG: v_rcp_iflag_f32_e32
; SI-DAG: v_mul_hi_u32
; SI-DAG: v_mul_lo_i32
-; SI-DAG: v_sub_i32_e32
+; SI-DAG: v_sub_{{[iu]}}32_e32
; SI-DAG: v_cndmask_b32_e64
; SI-DAG: v_mul_hi_u32
-; SI-DAG: v_add_i32_e32
-; SI-DAG: v_subrev_i32_e32
+; SI-DAG: v_add_{{[iu]}}32_e32
+; SI-DAG: v_subrev_{{[iu]}}32_e32
; SI-DAG: v_cndmask_b32_e64
; SI-DAG: v_mul_hi_u32
; SI-DAG: v_mul_lo_i32
-; SI-DAG: v_subrev_i32_e32
+; SI-DAG: v_subrev_{{[iu]}}32_e32
; SI-DAG: v_cndmask_b32_e64
; SI-DAG: v_cndmask_b32_e64
; SI-DAG: v_and_b32_e32
-; SI-DAG: v_add_i32_e32
-; SI-DAG: v_subrev_i32_e32
+; SI-DAG: v_add_{{[iu]}}32_e32
+; SI-DAG: v_subrev_{{[iu]}}32_e32
; SI-DAG: v_cndmask_b32_e64
; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_add_i32_e32
-; SI-DAG: v_subrev_i32_e32
+; SI-DAG: v_add_{{[iu]}}32_e32
+; SI-DAG: v_subrev_{{[iu]}}32_e32
; SI-DAG: v_cndmask_b32_e64
; SI-DAG: v_cndmask_b32_e64
; SI: s_endpgm
@@ -264,80 +264,80 @@ define amdgpu_kernel void @test_udivrem_v2(<2 x i32> addrspace(1)* %out, <2 x i3
; SI-DAG: v_rcp_iflag_f32_e32
; SI-DAG: v_mul_hi_u32
; SI-DAG: v_mul_lo_i32
-; SI-DAG: v_sub_i32_e32
+; SI-DAG: v_sub_{{[iu]}}32_e32
; SI-DAG: v_cndmask_b32_e64
; SI-DAG: v_mul_hi_u32
-; SI-DAG: v_add_i32_e32
-; SI-DAG: v_subrev_i32_e32
+; SI-DAG: v_add_{{[iu]}}32_e32
+; SI-DAG: v_subrev_{{[iu]}}32_e32
; SI-DAG: v_cndmask_b32_e64
; SI-DAG: v_mul_hi_u32
; SI-DAG: v_mul_lo_i32
-; SI-DAG: v_subrev_i32_e32
+; SI-DAG: v_subrev_{{[iu]}}32_e32
; SI-DAG: v_cndmask_b32_e64
; SI-DAG: v_cndmask_b32_e64
; SI-DAG: v_and_b32_e32
-; SI-DAG: v_add_i32_e32
-; SI-DAG: v_subrev_i32_e32
+; SI-DAG: v_add_{{[iu]}}32_e32
+; SI-DAG: v_subrev_{{[iu]}}32_e32
; SI-DAG: v_cndmask_b32_e64
; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_add_i32_e32
-; SI-DAG: v_subrev_i32_e32
+; SI-DAG: v_add_{{[iu]}}32_e32
+; SI-DAG: v_subrev_{{[iu]}}32_e32
; SI-DAG: v_cndmask_b32_e64
; SI-DAG: v_cndmask_b32_e64
; SI-DAG: v_rcp_iflag_f32_e32
; SI-DAG: v_mul_hi_u32
; SI-DAG: v_mul_lo_i32
-; SI-DAG: v_sub_i32_e32
+; SI-DAG: v_sub_{{[iu]}}32_e32
; SI-DAG: v_cndmask_b32_e64
; SI-DAG: v_mul_hi_u32
-; SI-DAG: v_add_i32_e32
-; SI-DAG: v_subrev_i32_e32
+; SI-DAG: v_add_{{[iu]}}32_e32
+; SI-DAG: v_subrev_{{[iu]}}32_e32
; SI-DAG: v_cndmask_b32_e64
; SI-DAG: v_mul_hi_u32
; SI-DAG: v_mul_lo_i32
-; SI-DAG: v_subrev_i32_e32
+; SI-DAG: v_subrev_{{[iu]}}32_e32
; SI-DAG: v_cndmask_b32_e64
; SI-DAG: v_cndmask_b32_e64
; SI-DAG: v_and_b32_e32
-; SI-DAG: v_add_i32_e32
-; SI-DAG: v_subrev_i32_e32
+; SI-DAG: v_add_{{[iu]}}32_e32
+; SI-DAG: v_subrev_{{[iu]}}32_e32
; SI-DAG: v_cndmask_b32_e64
; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_add_i32_e32
-; SI-DAG: v_subrev_i32_e32
+; SI-DAG: v_add_{{[iu]}}32_e32
+; SI-DAG: v_subrev_{{[iu]}}32_e32
; SI-DAG: v_cndmask_b32_e64
; SI-DAG: v_cndmask_b32_e64
; SI-DAG: v_rcp_iflag_f32_e32
; SI-DAG: v_mul_hi_u32
; SI-DAG: v_mul_lo_i32
-; SI-DAG: v_sub_i32_e32
+; SI-DAG: v_sub_{{[iu]}}32_e32
; SI-DAG: v_cndmask_b32_e64
; SI-DAG: v_mul_hi_u32
-; SI-DAG: v_add_i32_e32
-; SI-DAG: v_subrev_i32_e32
+; SI-DAG: v_add_{{[iu]}}32_e32
+; SI-DAG: v_subrev_{{[iu]}}32_e32
; SI-DAG: v_cndmask_b32_e64
; SI-DAG: v_mul_hi_u32
; SI-DAG: v_mul_lo_i32
-; SI-DAG: v_subrev_i32_e32
+; SI-DAG: v_subrev_{{[iu]}}32_e32
; SI-DAG: v_cndmask_b32_e64
; SI-DAG: v_cndmask_b32_e64
; SI-DAG: v_and_b32_e32
-; SI-DAG: v_add_i32_e32
-; SI-DAG: v_subrev_i32_e32
+; SI-DAG: v_add_{{[iu]}}32_e32
+; SI-DAG: v_subrev_{{[iu]}}32_e32
; SI-DAG: v_cndmask_b32_e64
; SI-DAG: v_cndmask_b32_e64
-; SI-DAG: v_add_i32_e32
-; SI-DAG: v_subrev_i32_e32
+; SI-DAG: v_add_{{[iu]}}32_e32
+; SI-DAG: v_subrev_{{[iu]}}32_e32
; SI-DAG: v_cndmask_b32_e64
; SI-DAG: v_cndmask_b32_e64
; SI-DAG: v_rcp_iflag_f32_e32
; SI-DAG: v_mul_hi_u32
; SI-DAG: v_mul_lo_i32
-; SI-DAG: v_sub_i32_e32
+; SI-DAG: v_sub_{{[iu]}}32_e32
; SI-DAG: v_cndmask_b32_e64
; SI-DAG: v_mul_hi_u32
-; SI-DAG: v_add_i32_e32
-; SI-DAG: v_subrev_i32_e32
+; SI-DAG: v_add_{{[iu]}}32_e32
+; SI-DAG: v_subrev_{{[iu]}}32_e32
; SI-DAG: v_cndmask_b32_e64
; SI: s_endpgm
define amdgpu_kernel void @test_udivrem_v4(<4 x i32> addrspace(1)* %out, <4 x i32> %x, <4 x i32> %y) {
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