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-rw-r--r--llvm/test/CodeGen/AMDGPU/store-private.ll114
1 files changed, 57 insertions, 57 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/store-private.ll b/llvm/test/CodeGen/AMDGPU/store-private.ll
index ce7656adc0b..617511a24b1 100644
--- a/llvm/test/CodeGen/AMDGPU/store-private.ll
+++ b/llvm/test/CodeGen/AMDGPU/store-private.ll
@@ -15,9 +15,9 @@
; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
; SI: buffer_store_byte
-define amdgpu_kernel void @store_i1(i1 addrspace(0)* %out) {
+define amdgpu_kernel void @store_i1(i1 addrspace(5)* %out) {
entry:
- store i1 true, i1 addrspace(0)* %out
+ store i1 true, i1 addrspace(5)* %out
ret void
}
@@ -44,9 +44,9 @@ entry:
; SI: buffer_store_byte
-define amdgpu_kernel void @store_i8(i8 addrspace(0)* %out, i8 %in) {
+define amdgpu_kernel void @store_i8(i8 addrspace(5)* %out, i8 %in) {
entry:
- store i8 %in, i8 addrspace(0)* %out
+ store i8 %in, i8 addrspace(5)* %out
ret void
}
@@ -72,9 +72,9 @@ entry:
; EG: MOV * T(0 + AR.x).X+, [[RES]]
; SI: buffer_store_short
-define amdgpu_kernel void @store_i16(i16 addrspace(0)* %out, i16 %in) {
+define amdgpu_kernel void @store_i16(i16 addrspace(5)* %out, i16 %in) {
entry:
- store i16 %in, i16 addrspace(0)* %out
+ store i16 %in, i16 addrspace(5)* %out
ret void
}
@@ -102,9 +102,9 @@ entry:
; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,
; CM: MOVA_INT
; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
-define amdgpu_kernel void @store_i24(i24 addrspace(0)* %out, i24 %in) {
+define amdgpu_kernel void @store_i24(i24 addrspace(5)* %out, i24 %in) {
entry:
- store i24 %in, i24 addrspace(0)* %out
+ store i24 %in, i24 addrspace(5)* %out
ret void
}
@@ -120,9 +120,9 @@ entry:
; CM: MOVA_INT
; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
; CM-NOT: MOVA_INT
-define amdgpu_kernel void @store_i25(i25 addrspace(0)* %out, i25 %in) {
+define amdgpu_kernel void @store_i25(i25 addrspace(5)* %out, i25 %in) {
entry:
- store i25 %in, i25 addrspace(0)* %out
+ store i25 %in, i25 addrspace(5)* %out
ret void
}
@@ -141,10 +141,10 @@ entry:
; CM-NOT: MOVA_INT
; SI: buffer_store_short
-define amdgpu_kernel void @store_v2i8(<2 x i8> addrspace(0)* %out, <2 x i32> %in) {
+define amdgpu_kernel void @store_v2i8(<2 x i8> addrspace(5)* %out, <2 x i32> %in) {
entry:
%0 = trunc <2 x i32> %in to <2 x i8>
- store <2 x i8> %0, <2 x i8> addrspace(0)* %out
+ store <2 x i8> %0, <2 x i8> addrspace(5)* %out
ret void
}
@@ -172,10 +172,10 @@ entry:
; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
; SI: buffer_store_byte
-define amdgpu_kernel void @store_v2i8_unaligned(<2 x i8> addrspace(0)* %out, <2 x i32> %in) {
+define amdgpu_kernel void @store_v2i8_unaligned(<2 x i8> addrspace(5)* %out, <2 x i32> %in) {
entry:
%0 = trunc <2 x i32> %in to <2 x i8>
- store <2 x i8> %0, <2 x i8> addrspace(0)* %out, align 1
+ store <2 x i8> %0, <2 x i8> addrspace(5)* %out, align 1
ret void
}
@@ -191,10 +191,10 @@ entry:
; CM-NOT: MOVA_INT
; SI: buffer_store_dword
-define amdgpu_kernel void @store_v2i16(<2 x i16> addrspace(0)* %out, <2 x i32> %in) {
+define amdgpu_kernel void @store_v2i16(<2 x i16> addrspace(5)* %out, <2 x i32> %in) {
entry:
%0 = trunc <2 x i32> %in to <2 x i16>
- store <2 x i16> %0, <2 x i16> addrspace(0)* %out
+ store <2 x i16> %0, <2 x i16> addrspace(5)* %out
ret void
}
@@ -223,10 +223,10 @@ entry:
; SI: buffer_store_short
; SI: buffer_store_short
-define amdgpu_kernel void @store_v2i16_unaligned(<2 x i16> addrspace(0)* %out, <2 x i32> %in) {
+define amdgpu_kernel void @store_v2i16_unaligned(<2 x i16> addrspace(5)* %out, <2 x i32> %in) {
entry:
%0 = trunc <2 x i32> %in to <2 x i16>
- store <2 x i16> %0, <2 x i16> addrspace(0)* %out, align 2
+ store <2 x i16> %0, <2 x i16> addrspace(5)* %out, align 2
ret void
}
@@ -240,10 +240,10 @@ entry:
; CM-NOT: MOVA_INT
; SI: buffer_store_dword
-define amdgpu_kernel void @store_v4i8(<4 x i8> addrspace(0)* %out, <4 x i32> %in) {
+define amdgpu_kernel void @store_v4i8(<4 x i8> addrspace(5)* %out, <4 x i32> %in) {
entry:
%0 = trunc <4 x i32> %in to <4 x i8>
- store <4 x i8> %0, <4 x i8> addrspace(0)* %out
+ store <4 x i8> %0, <4 x i8> addrspace(5)* %out
ret void
}
@@ -299,10 +299,10 @@ entry:
; SI: buffer_store_byte
; SI: buffer_store_byte
; SI-NOT: buffer_store_dword
-define amdgpu_kernel void @store_v4i8_unaligned(<4 x i8> addrspace(0)* %out, <4 x i32> %in) {
+define amdgpu_kernel void @store_v4i8_unaligned(<4 x i8> addrspace(5)* %out, <4 x i32> %in) {
entry:
%0 = trunc <4 x i32> %in to <4 x i8>
- store <4 x i8> %0, <4 x i8> addrspace(0)* %out, align 1
+ store <4 x i8> %0, <4 x i8> addrspace(5)* %out, align 1
ret void
}
@@ -410,10 +410,10 @@ entry:
; SI: buffer_store_byte
; SI: buffer_store_byte
; SI-NOT: buffer_store_dword
-define amdgpu_kernel void @store_v8i8_unaligned(<8 x i8> addrspace(0)* %out, <8 x i32> %in) {
+define amdgpu_kernel void @store_v8i8_unaligned(<8 x i8> addrspace(5)* %out, <8 x i32> %in) {
entry:
%0 = trunc <8 x i32> %in to <8 x i8>
- store <8 x i8> %0, <8 x i8> addrspace(0)* %out, align 1
+ store <8 x i8> %0, <8 x i8> addrspace(5)* %out, align 1
ret void
}
@@ -443,10 +443,10 @@ entry:
; SI: buffer_store_short
; SI: buffer_store_short
; SI-NOT: buffer_store_dword
-define amdgpu_kernel void @store_v4i8_halfaligned(<4 x i8> addrspace(0)* %out, <4 x i32> %in) {
+define amdgpu_kernel void @store_v4i8_halfaligned(<4 x i8> addrspace(5)* %out, <4 x i32> %in) {
entry:
%0 = trunc <4 x i32> %in to <4 x i8>
- store <4 x i8> %0, <4 x i8> addrspace(0)* %out, align 2
+ store <4 x i8> %0, <4 x i8> addrspace(5)* %out, align 2
ret void
}
@@ -460,8 +460,8 @@ entry:
; SI: buffer_store_dword
-define amdgpu_kernel void @store_f32(float addrspace(0)* %out, float %in) {
- store float %in, float addrspace(0)* %out
+define amdgpu_kernel void @store_f32(float addrspace(5)* %out, float %in) {
+ store float %in, float addrspace(5)* %out
ret void
}
@@ -480,10 +480,10 @@ define amdgpu_kernel void @store_f32(float addrspace(0)* %out, float %in) {
; XSI: buffer_store_dwordx2
; SI: buffer_store_dword
; SI: buffer_store_dword
-define amdgpu_kernel void @store_v4i16(<4 x i16> addrspace(0)* %out, <4 x i32> %in) {
+define amdgpu_kernel void @store_v4i16(<4 x i16> addrspace(5)* %out, <4 x i32> %in) {
entry:
%0 = trunc <4 x i32> %in to <4 x i16>
- store <4 x i16> %0, <4 x i16> addrspace(0)* %out
+ store <4 x i16> %0, <4 x i16> addrspace(5)* %out
ret void
}
@@ -504,11 +504,11 @@ entry:
; SI: buffer_store_dword
; SI: buffer_store_dword
-define amdgpu_kernel void @store_v2f32(<2 x float> addrspace(0)* %out, float %a, float %b) {
+define amdgpu_kernel void @store_v2f32(<2 x float> addrspace(5)* %out, float %a, float %b) {
entry:
%0 = insertelement <2 x float> <float 0.0, float 0.0>, float %a, i32 0
%1 = insertelement <2 x float> %0, float %b, i32 1
- store <2 x float> %1, <2 x float> addrspace(0)* %out
+ store <2 x float> %1, <2 x float> addrspace(5)* %out
ret void
}
@@ -533,8 +533,8 @@ entry:
; SI: buffer_store_dword
; SI: buffer_store_dword
-define amdgpu_kernel void @store_v3i32(<3 x i32> addrspace(0)* %out, <3 x i32> %a) nounwind {
- store <3 x i32> %a, <3 x i32> addrspace(0)* %out, align 16
+define amdgpu_kernel void @store_v3i32(<3 x i32> addrspace(5)* %out, <3 x i32> %a) nounwind {
+ store <3 x i32> %a, <3 x i32> addrspace(5)* %out, align 16
ret void
}
@@ -563,9 +563,9 @@ define amdgpu_kernel void @store_v3i32(<3 x i32> addrspace(0)* %out, <3 x i32> %
; SI: buffer_store_dword
; SI: buffer_store_dword
; SI: buffer_store_dword
-define amdgpu_kernel void @store_v4i32(<4 x i32> addrspace(0)* %out, <4 x i32> %in) {
+define amdgpu_kernel void @store_v4i32(<4 x i32> addrspace(5)* %out, <4 x i32> %in) {
entry:
- store <4 x i32> %in, <4 x i32> addrspace(0)* %out
+ store <4 x i32> %in, <4 x i32> addrspace(5)* %out
ret void
}
@@ -594,9 +594,9 @@ entry:
; SI: buffer_store_dword
; SI: buffer_store_dword
; SI: buffer_store_dword
-define amdgpu_kernel void @store_v4i32_unaligned(<4 x i32> addrspace(0)* %out, <4 x i32> %in) {
+define amdgpu_kernel void @store_v4i32_unaligned(<4 x i32> addrspace(5)* %out, <4 x i32> %in) {
entry:
- store <4 x i32> %in, <4 x i32> addrspace(0)* %out, align 4
+ store <4 x i32> %in, <4 x i32> addrspace(5)* %out, align 4
ret void
}
@@ -626,9 +626,9 @@ entry:
; SI: buffer_store_dword
; SI: buffer_store_dword
; SI: buffer_store_dword
-define amdgpu_kernel void @store_v4f32(<4 x float> addrspace(0)* %out, <4 x float> addrspace(0)* %in) {
- %1 = load <4 x float>, <4 x float> addrspace(0) * %in
- store <4 x float> %1, <4 x float> addrspace(0)* %out
+define amdgpu_kernel void @store_v4f32(<4 x float> addrspace(5)* %out, <4 x float> addrspace(5)* %in) {
+ %1 = load <4 x float>, <4 x float> addrspace(5)* %in
+ store <4 x float> %1, <4 x float> addrspace(5)* %out
ret void
}
@@ -644,10 +644,10 @@ define amdgpu_kernel void @store_v4f32(<4 x float> addrspace(0)* %out, <4 x floa
; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
; SI: buffer_store_byte
-define amdgpu_kernel void @store_i64_i8(i8 addrspace(0)* %out, i64 %in) {
+define amdgpu_kernel void @store_i64_i8(i8 addrspace(5)* %out, i64 %in) {
entry:
%0 = trunc i64 %in to i8
- store i8 %0, i8 addrspace(0)* %out
+ store i8 %0, i8 addrspace(5)* %out
ret void
}
@@ -663,10 +663,10 @@ entry:
; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
; SI: buffer_store_short
-define amdgpu_kernel void @store_i64_i16(i16 addrspace(0)* %out, i64 %in) {
+define amdgpu_kernel void @store_i64_i16(i16 addrspace(5)* %out, i64 %in) {
entry:
%0 = trunc i64 %in to i16
- store i16 %0, i16 addrspace(0)* %out
+ store i16 %0, i16 addrspace(5)* %out
ret void
}
@@ -689,14 +689,14 @@ entry:
; XSI: buffer_store_dwordx2
; SI: buffer_store_dword
; SI: buffer_store_dword
-define amdgpu_kernel void @vecload2(i32 addrspace(0)* nocapture %out, i32 addrspace(2)* nocapture %mem) #0 {
+define amdgpu_kernel void @vecload2(i32 addrspace(5)* nocapture %out, i32 addrspace(2)* nocapture %mem) #0 {
entry:
%0 = load i32, i32 addrspace(2)* %mem, align 4
%arrayidx1.i = getelementptr inbounds i32, i32 addrspace(2)* %mem, i64 1
%1 = load i32, i32 addrspace(2)* %arrayidx1.i, align 4
- store i32 %0, i32 addrspace(0)* %out, align 4
- %arrayidx1 = getelementptr inbounds i32, i32 addrspace(0)* %out, i64 1
- store i32 %1, i32 addrspace(0)* %arrayidx1, align 4
+ store i32 %0, i32 addrspace(5)* %out, align 4
+ %arrayidx1 = getelementptr inbounds i32, i32 addrspace(5)* %out, i64 1
+ store i32 %1, i32 addrspace(5)* %arrayidx1, align 4
ret void
}
@@ -727,15 +727,15 @@ entry:
; SI: buffer_store_dword
; SI: buffer_store_dword
; SI: buffer_store_dword
-define amdgpu_kernel void @i128-const-store(i32 addrspace(0)* %out) {
+define amdgpu_kernel void @i128-const-store(i32 addrspace(5)* %out) {
entry:
- store i32 1, i32 addrspace(0)* %out, align 4
- %arrayidx2 = getelementptr inbounds i32, i32 addrspace(0)* %out, i64 1
- store i32 1, i32 addrspace(0)* %arrayidx2, align 4
- %arrayidx4 = getelementptr inbounds i32, i32 addrspace(0)* %out, i64 2
- store i32 2, i32 addrspace(0)* %arrayidx4, align 4
- %arrayidx6 = getelementptr inbounds i32, i32 addrspace(0)* %out, i64 3
- store i32 2, i32 addrspace(0)* %arrayidx6, align 4
+ store i32 1, i32 addrspace(5)* %out, align 4
+ %arrayidx2 = getelementptr inbounds i32, i32 addrspace(5)* %out, i64 1
+ store i32 1, i32 addrspace(5)* %arrayidx2, align 4
+ %arrayidx4 = getelementptr inbounds i32, i32 addrspace(5)* %out, i64 2
+ store i32 2, i32 addrspace(5)* %arrayidx4, align 4
+ %arrayidx6 = getelementptr inbounds i32, i32 addrspace(5)* %out, i64 3
+ store i32 2, i32 addrspace(5)* %arrayidx6, align 4
ret void
}
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