diff options
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/smrd.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/smrd.ll | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/smrd.ll b/llvm/test/CodeGen/AMDGPU/smrd.ll index 6bed5e9e7db..a67d471ee19 100644 --- a/llvm/test/CodeGen/AMDGPU/smrd.ll +++ b/llvm/test/CodeGen/AMDGPU/smrd.ll @@ -332,7 +332,7 @@ main_body: ; GCN-LABEL: {{^}}smrd_imm_merge_m0: ; -; SICIVI: s_buffer_load_dwordx2 +; GCN: s_buffer_load_dwordx2 ; SICIVI: s_mov_b32 m0 ; SICIVI_DAG: v_interp_p1_f32 ; SICIVI_DAG: v_interp_p1_f32 @@ -340,13 +340,15 @@ main_body: ; SICIVI_DAG: v_interp_p2_f32 ; SICIVI_DAG: v_interp_p2_f32 ; SICIVI_DAG: v_interp_p2_f32 -; SICIVI: s_mov_b32 m0 -; SICIVI: v_movrels_b32_e32 +; +; extractelement does not result in movrels anymore for vectors gitting 8 dwords +; SICIVI-NOT: s_mov_b32 m0 +; SICIVI-NOT: v_movrels_b32_e32 +; v_cndmask_b32_e32 +; v_cndmask_b32_e32 ; ; Merging is still thwarted on GFX9 due to s_set_gpr_idx ; -; GFX9: s_buffer_load_dword -; GFX9: s_buffer_load_dword define amdgpu_ps float @smrd_imm_merge_m0(<4 x i32> inreg %desc, i32 inreg %prim, float %u, float %v) #0 { main_body: %idx1.f = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 0) |
