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-rw-r--r--llvm/test/CodeGen/AMDGPU/setcc-fneg-constant.ll32
1 files changed, 16 insertions, 16 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/setcc-fneg-constant.ll b/llvm/test/CodeGen/AMDGPU/setcc-fneg-constant.ll
index d96b03f7330..8d455d84bf9 100644
--- a/llvm/test/CodeGen/AMDGPU/setcc-fneg-constant.ll
+++ b/llvm/test/CodeGen/AMDGPU/setcc-fneg-constant.ll
@@ -10,7 +10,7 @@
; GCN: v_mul_f32_e32 [[MUL:v[0-9]+]], [[B]], [[A]]
; GCN: v_cmp_eq_f32_e32 vcc, -4.0, [[MUL]]
; GCN: buffer_store_dword [[MUL]]
-define void @multi_use_fneg_src() #0 {
+define amdgpu_kernel void @multi_use_fneg_src() #0 {
%a = load volatile float, float addrspace(1)* undef
%b = load volatile float, float addrspace(1)* undef
%x = load volatile i32, i32 addrspace(1)* undef
@@ -33,7 +33,7 @@ define void @multi_use_fneg_src() #0 {
; GCN: v_mul_f32_e32 [[MUL:v[0-9]+]], [[B]], [[A]]
; GCN: v_cmp_eq_f32_e32 vcc, -4.0, [[A]]
; GCN: v_mul_f32_e64 [[USE1:v[0-9]+]], [[MUL]], -[[MUL]]
-define void @multi_foldable_use_fneg_src() #0 {
+define amdgpu_kernel void @multi_foldable_use_fneg_src() #0 {
%a = load volatile float, float addrspace(1)* undef
%b = load volatile float, float addrspace(1)* undef
%x = load volatile i32, i32 addrspace(1)* undef
@@ -59,7 +59,7 @@ define void @multi_foldable_use_fneg_src() #0 {
; GCN-NEXT: v_cmp_eq_f32_e32 vcc, 4.0, [[MUL]]
; GCN-NOT: xor
; GCN: buffer_store_dword [[MUL]]
-define void @multi_use_fneg() #0 {
+define amdgpu_kernel void @multi_use_fneg() #0 {
%a = load volatile float, float addrspace(1)* undef
%b = load volatile float, float addrspace(1)* undef
%x = load volatile i32, i32 addrspace(1)* undef
@@ -82,7 +82,7 @@ define void @multi_use_fneg() #0 {
; GCN: v_cmp_eq_f32_e32 vcc, -4.0, [[MUL0]]
; GCN: v_mul_f32_e64 [[MUL1:v[0-9]+]], -[[MUL0]], [[MUL0]]
; GCN: buffer_store_dword [[MUL1]]
-define void @multi_foldable_use_fneg() #0 {
+define amdgpu_kernel void @multi_foldable_use_fneg() #0 {
%a = load volatile float, float addrspace(1)* undef
%b = load volatile float, float addrspace(1)* undef
%x = load volatile i32, i32 addrspace(1)* undef
@@ -101,7 +101,7 @@ define void @multi_foldable_use_fneg() #0 {
; GCN-LABEL: {{^}}test_setcc_fneg_oeq_posk_f32:
; GCN: v_cmp_eq_f32_e32 vcc, -4.0, v{{[0-9]+}}
-define void @test_setcc_fneg_oeq_posk_f32() #0 {
+define amdgpu_kernel void @test_setcc_fneg_oeq_posk_f32() #0 {
%a = load volatile float, float addrspace(1)* undef
%x = load volatile i32, i32 addrspace(1)* undef
%y = load volatile i32, i32 addrspace(1)* undef
@@ -114,7 +114,7 @@ define void @test_setcc_fneg_oeq_posk_f32() #0 {
; GCN-LABEL: {{^}}test_setcc_fneg_ogt_posk_f32:
; GCN: v_cmp_gt_f32_e32 vcc, -4.0, v{{[0-9]+}}
-define void @test_setcc_fneg_ogt_posk_f32() #0 {
+define amdgpu_kernel void @test_setcc_fneg_ogt_posk_f32() #0 {
%a = load volatile float, float addrspace(1)* undef
%x = load volatile i32, i32 addrspace(1)* undef
%y = load volatile i32, i32 addrspace(1)* undef
@@ -127,7 +127,7 @@ define void @test_setcc_fneg_ogt_posk_f32() #0 {
; GCN-LABEL: {{^}}test_setcc_fneg_oge_posk_f32:
; GCN: v_cmp_ge_f32_e32 vcc, -4.0, v{{[0-9]+}}
-define void @test_setcc_fneg_oge_posk_f32() #0 {
+define amdgpu_kernel void @test_setcc_fneg_oge_posk_f32() #0 {
%a = load volatile float, float addrspace(1)* undef
%x = load volatile i32, i32 addrspace(1)* undef
%y = load volatile i32, i32 addrspace(1)* undef
@@ -140,7 +140,7 @@ define void @test_setcc_fneg_oge_posk_f32() #0 {
; GCN-LABEL: {{^}}test_setcc_fneg_olt_posk_f32:
; GCN: v_cmp_lt_f32_e32 vcc, -4.0, v{{[0-9]+}}
-define void @test_setcc_fneg_olt_posk_f32() #0 {
+define amdgpu_kernel void @test_setcc_fneg_olt_posk_f32() #0 {
%a = load volatile float, float addrspace(1)* undef
%x = load volatile i32, i32 addrspace(1)* undef
%y = load volatile i32, i32 addrspace(1)* undef
@@ -153,7 +153,7 @@ define void @test_setcc_fneg_olt_posk_f32() #0 {
; GCN-LABEL: {{^}}test_setcc_fneg_ole_posk_f32:
; GCN: v_cmp_le_f32_e32 vcc, -4.0, v{{[0-9]+}}
-define void @test_setcc_fneg_ole_posk_f32() #0 {
+define amdgpu_kernel void @test_setcc_fneg_ole_posk_f32() #0 {
%a = load volatile float, float addrspace(1)* undef
%x = load volatile i32, i32 addrspace(1)* undef
%y = load volatile i32, i32 addrspace(1)* undef
@@ -166,7 +166,7 @@ define void @test_setcc_fneg_ole_posk_f32() #0 {
; GCN-LABEL: {{^}}test_setcc_fneg_one_posk_f32:
; GCN: v_cmp_lg_f32_e32 vcc, -4.0, v{{[0-9]+}}
-define void @test_setcc_fneg_one_posk_f32() #0 {
+define amdgpu_kernel void @test_setcc_fneg_one_posk_f32() #0 {
%a = load volatile float, float addrspace(1)* undef
%x = load volatile i32, i32 addrspace(1)* undef
%y = load volatile i32, i32 addrspace(1)* undef
@@ -179,7 +179,7 @@ define void @test_setcc_fneg_one_posk_f32() #0 {
; GCN-LABEL: {{^}}test_setcc_fneg_ueq_posk_f32:
; GCN: v_cmp_nlg_f32_e32 vcc, -4.0, v{{[0-9]+}}
-define void @test_setcc_fneg_ueq_posk_f32() #0 {
+define amdgpu_kernel void @test_setcc_fneg_ueq_posk_f32() #0 {
%a = load volatile float, float addrspace(1)* undef
%x = load volatile i32, i32 addrspace(1)* undef
%y = load volatile i32, i32 addrspace(1)* undef
@@ -192,7 +192,7 @@ define void @test_setcc_fneg_ueq_posk_f32() #0 {
; GCN-LABEL: {{^}}test_setcc_fneg_ugt_posk_f32:
; GCN: v_cmp_nle_f32_e32 vcc, -4.0, v{{[0-9]+}}
-define void @test_setcc_fneg_ugt_posk_f32() #0 {
+define amdgpu_kernel void @test_setcc_fneg_ugt_posk_f32() #0 {
%a = load volatile float, float addrspace(1)* undef
%x = load volatile i32, i32 addrspace(1)* undef
%y = load volatile i32, i32 addrspace(1)* undef
@@ -205,7 +205,7 @@ define void @test_setcc_fneg_ugt_posk_f32() #0 {
; GCN-LABEL: {{^}}test_setcc_fneg_uge_posk_f32:
; GCN: v_cmp_nlt_f32_e32 vcc, -4.0, v{{[0-9]+}}
-define void @test_setcc_fneg_uge_posk_f32() #0 {
+define amdgpu_kernel void @test_setcc_fneg_uge_posk_f32() #0 {
%a = load volatile float, float addrspace(1)* undef
%x = load volatile i32, i32 addrspace(1)* undef
%y = load volatile i32, i32 addrspace(1)* undef
@@ -218,7 +218,7 @@ define void @test_setcc_fneg_uge_posk_f32() #0 {
; GCN-LABEL: {{^}}test_setcc_fneg_ult_posk_f32:
; GCN: v_cmp_nge_f32_e32 vcc, -4.0, v{{[0-9]+}}
-define void @test_setcc_fneg_ult_posk_f32() #0 {
+define amdgpu_kernel void @test_setcc_fneg_ult_posk_f32() #0 {
%a = load volatile float, float addrspace(1)* undef
%x = load volatile i32, i32 addrspace(1)* undef
%y = load volatile i32, i32 addrspace(1)* undef
@@ -231,7 +231,7 @@ define void @test_setcc_fneg_ult_posk_f32() #0 {
; GCN-LABEL: {{^}}test_setcc_fneg_ule_posk_f32:
; GCN: v_cmp_ngt_f32_e32 vcc, -4.0, v{{[0-9]+}}
-define void @test_setcc_fneg_ule_posk_f32() #0 {
+define amdgpu_kernel void @test_setcc_fneg_ule_posk_f32() #0 {
%a = load volatile float, float addrspace(1)* undef
%x = load volatile i32, i32 addrspace(1)* undef
%y = load volatile i32, i32 addrspace(1)* undef
@@ -244,7 +244,7 @@ define void @test_setcc_fneg_ule_posk_f32() #0 {
; GCN-LABEL: {{^}}test_setcc_fneg_une_posk_f32:
; GCN: v_cmp_neq_f32_e32 vcc, -4.0, v{{[0-9]+}}
-define void @test_setcc_fneg_une_posk_f32() #0 {
+define amdgpu_kernel void @test_setcc_fneg_une_posk_f32() #0 {
%a = load volatile float, float addrspace(1)* undef
%x = load volatile i32, i32 addrspace(1)* undef
%y = load volatile i32, i32 addrspace(1)* undef
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