diff options
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/load-global-i32.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/load-global-i32.ll | 282 |
1 files changed, 174 insertions, 108 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/load-global-i32.ll b/llvm/test/CodeGen/AMDGPU/load-global-i32.ll index 8e37122d551..27081b8379b 100644 --- a/llvm/test/CodeGen/AMDGPU/load-global-i32.ll +++ b/llvm/test/CodeGen/AMDGPU/load-global-i32.ll @@ -2,11 +2,12 @@ ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=EG -check-prefix=FUNC %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s ; FUNC-LABEL: {{^}}global_load_i32: ; GCN-NOHSA: buffer_load_dword v{{[0-9]+}} -; GCN-HSA: flat_load_dword +; GCN-HSA: {{flat|global}}_load_dword ; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0 define amdgpu_kernel void @global_load_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { @@ -18,7 +19,7 @@ entry: ; FUNC-LABEL: {{^}}global_load_v2i32: ; GCN-NOHSA: buffer_load_dwordx2 -; GCN-HSA: flat_load_dwordx2 +; GCN-HSA: {{flat|global}}_load_dwordx2 ; EG: VTX_READ_64 define amdgpu_kernel void @global_load_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) #0 { @@ -30,7 +31,7 @@ entry: ; FUNC-LABEL: {{^}}global_load_v3i32: ; GCN-NOHSA: buffer_load_dwordx4 -; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 ; EG: VTX_READ_128 define amdgpu_kernel void @global_load_v3i32(<3 x i32> addrspace(1)* %out, <3 x i32> addrspace(1)* %in) #0 { @@ -42,7 +43,7 @@ entry: ; FUNC-LABEL: {{^}}global_load_v4i32: ; GCN-NOHSA: buffer_load_dwordx4 -; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 ; EG: VTX_READ_128 define amdgpu_kernel void @global_load_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) #0 { @@ -55,8 +56,8 @@ entry: ; FUNC-LABEL: {{^}}global_load_v8i32: ; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4 -; GCN-HSA: flat_load_dwordx4 -; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 ; EG: VTX_READ_128 ; EG: VTX_READ_128 @@ -73,10 +74,10 @@ entry: ; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4 -; GCN-HSA: flat_load_dwordx4 -; GCN-HSA: flat_load_dwordx4 -; GCN-HSA: flat_load_dwordx4 -; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 ; EG: VTX_READ_128 ; EG: VTX_READ_128 @@ -91,11 +92,11 @@ entry: ; FUNC-LABEL: {{^}}global_zextload_i32_to_i64: ; GCN-NOHSA-DAG: buffer_load_dword v[[LO:[0-9]+]], -; GCN-HSA-DAG: flat_load_dword v[[LO:[0-9]+]], +; GCN-HSA-DAG: {{flat|global}}_load_dword v[[LO:[0-9]+]], ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} ; GCN-NOHSA: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]] -; GCN-HSA: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]] +; GCN-HSA: {{flat|global}}_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]] ; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY define amdgpu_kernel void @global_zextload_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { @@ -107,10 +108,10 @@ define amdgpu_kernel void @global_zextload_i32_to_i64(i64 addrspace(1)* %out, i3 ; FUNC-LABEL: {{^}}global_sextload_i32_to_i64: ; GCN-NOHSA: buffer_load_dword v[[LO:[0-9]+]] -; GCN-HSA: flat_load_dword v[[LO:[0-9]+]] +; GCN-HSA: {{flat|global}}_load_dword v[[LO:[0-9]+]] ; GCN: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]] ; GCN-NOHSA: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} -; GCN-HSA: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}} +; GCN-HSA: {{flat|global}}_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}} ; EG: MEM_RAT @@ -128,8 +129,8 @@ define amdgpu_kernel void @global_sextload_i32_to_i64(i64 addrspace(1)* %out, i3 ; GCN-NOHSA: buffer_load_dword ; GCN-NOHSA: buffer_store_dwordx2 -; GCN-HSA: flat_load_dword -; GCN-HSA: flat_store_dwordx2 +; GCN-HSA: {{flat|global}}_load_dword +; GCN-HSA: {{flat|global}}_store_dwordx2 define amdgpu_kernel void @global_zextload_v1i32_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i32> addrspace(1)* %in) #0 { %ld = load <1 x i32>, <1 x i32> addrspace(1)* %in %ext = zext <1 x i32> %ld to <1 x i64> @@ -139,10 +140,10 @@ define amdgpu_kernel void @global_zextload_v1i32_to_v1i64(<1 x i64> addrspace(1) ; FUNC-LABEL: {{^}}global_sextload_v1i32_to_v1i64: ; GCN-NOHSA: buffer_load_dword v[[LO:[0-9]+]] -; GCN-HSA: flat_load_dword v[[LO:[0-9]+]] +; GCN-HSA: {{flat|global}}_load_dword v[[LO:[0-9]+]] ; GCN: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]] ; GCN-NOHSA: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} -; GCN-HSA: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}} +; GCN-HSA: {{flat|global}}_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}} define amdgpu_kernel void @global_sextload_v1i32_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i32> addrspace(1)* %in) #0 { %ld = load <1 x i32>, <1 x i32> addrspace(1)* %in %ext = sext <1 x i32> %ld to <1 x i64> @@ -154,8 +155,8 @@ define amdgpu_kernel void @global_sextload_v1i32_to_v1i64(<1 x i64> addrspace(1) ; GCN-NOHSA: buffer_load_dwordx2 ; GCN-NOHSA: buffer_store_dwordx4 -; GCN-HSA: flat_load_dwordx2 -; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx2 +; GCN-HSA: {{flat|global}}_store_dwordx4 define amdgpu_kernel void @global_zextload_v2i32_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) #0 { %ld = load <2 x i32>, <2 x i32> addrspace(1)* %in %ext = zext <2 x i32> %ld to <2 x i64> @@ -165,13 +166,13 @@ define amdgpu_kernel void @global_zextload_v2i32_to_v2i64(<2 x i64> addrspace(1) ; FUNC-LABEL: {{^}}global_sextload_v2i32_to_v2i64: ; GCN-NOHSA: buffer_load_dwordx2 -; GCN-HSA: flat_load_dwordx2 +; GCN-HSA: {{flat|global}}_load_dwordx2 ; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32 ; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 define amdgpu_kernel void @global_sextload_v2i32_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) #0 { %ld = load <2 x i32>, <2 x i32> addrspace(1)* %in %ext = sext <2 x i32> %ld to <2 x i64> @@ -184,9 +185,9 @@ define amdgpu_kernel void @global_sextload_v2i32_to_v2i64(<2 x i64> addrspace(1) ; GCN-NOHSA: buffer_store_dwordx4 ; GCN-NOHSA: buffer_store_dwordx4 -; GCN-HSA: flat_load_dwordx4 -; GCN-HSA: flat_store_dwordx4 -; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 +; GCN-HSA: {{flat|global}}_store_dwordx4 +; GCN-HSA: {{flat|global}}_store_dwordx4 define amdgpu_kernel void @global_zextload_v4i32_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) #0 { %ld = load <4 x i32>, <4 x i32> addrspace(1)* %in %ext = zext <4 x i32> %ld to <4 x i64> @@ -196,7 +197,7 @@ define amdgpu_kernel void @global_zextload_v4i32_to_v4i64(<4 x i64> addrspace(1) ; FUNC-LABEL: {{^}}global_sextload_v4i32_to_v4i64: ; GCN-NOHSA: buffer_load_dwordx4 -; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 ; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32 @@ -206,8 +207,8 @@ define amdgpu_kernel void @global_zextload_v4i32_to_v4i64(<4 x i64> addrspace(1) ; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 define amdgpu_kernel void @global_sextload_v4i32_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) #0 { %ld = load <4 x i32>, <4 x i32> addrspace(1)* %in %ext = sext <4 x i32> %ld to <4 x i64> @@ -219,18 +220,18 @@ define amdgpu_kernel void @global_sextload_v4i32_to_v4i64(<4 x i64> addrspace(1) ; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4 -; GCN-HSA: flat_load_dwordx4 -; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 -; GCN-SA-DAG: flat_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 define amdgpu_kernel void @global_zextload_v8i32_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i32> addrspace(1)* %in) #0 { %ld = load <8 x i32>, <8 x i32> addrspace(1)* %in %ext = zext <8 x i32> %ld to <8 x i64> @@ -242,8 +243,8 @@ define amdgpu_kernel void @global_zextload_v8i32_to_v8i64(<8 x i64> addrspace(1) ; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4 -; GCN-HSA: flat_load_dwordx4 -; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 ; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32 @@ -259,10 +260,10 @@ define amdgpu_kernel void @global_zextload_v8i32_to_v8i64(<8 x i64> addrspace(1) ; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 define amdgpu_kernel void @global_sextload_v8i32_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i32> addrspace(1)* %in) #0 { %ld = load <8 x i32>, <8 x i32> addrspace(1)* %in %ext = sext <8 x i32> %ld to <8 x i64> @@ -276,10 +277,10 @@ define amdgpu_kernel void @global_sextload_v8i32_to_v8i64(<8 x i64> addrspace(1) ; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4 -; GCN-HSA: flat_load_dwordx4 -; GCN-HSA: flat_load_dwordx4 -; GCN-HSA: flat_load_dwordx4 -; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 ; GCN-DAG: v_ashrrev_i32 @@ -287,28 +288,28 @@ define amdgpu_kernel void @global_sextload_v8i32_to_v8i64(<8 x i64> addrspace(1) ; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32 ; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 ; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32 ; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 ; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32 ; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 ; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32 ; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 define amdgpu_kernel void @global_sextload_v16i32_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i32> addrspace(1)* %in) #0 { %ld = load <16 x i32>, <16 x i32> addrspace(1)* %in %ext = sext <16 x i32> %ld to <16 x i64> @@ -322,10 +323,10 @@ define amdgpu_kernel void @global_sextload_v16i32_to_v16i64(<16 x i64> addrspace ; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4 -; GCN-HSA: flat_load_dwordx4 -; GCN-HSA: flat_load_dwordx4 -; GCN-HSA: flat_load_dwordx4 -; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 ; GCN-NOHSA: buffer_store_dwordx4 ; GCN-NOHSA: buffer_store_dwordx4 @@ -336,14 +337,14 @@ define amdgpu_kernel void @global_sextload_v16i32_to_v16i64(<16 x i64> addrspace ; GCN-NOHSA: buffer_store_dwordx4 ; GCN-NOHSA: buffer_store_dwordx4 -; GCN-HSA: flat_store_dwordx4 -; GCN-HSA: flat_store_dwordx4 -; GCN-HSA: flat_store_dwordx4 -; GCN-HSA: flat_store_dwordx4 -; GCN-HSA: flat_store_dwordx4 -; GCN-HSA: flat_store_dwordx4 -; GCN-HSA: flat_store_dwordx4 -; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: {{flat|global}}_store_dwordx4 +; GCN-HSA: {{flat|global}}_store_dwordx4 +; GCN-HSA: {{flat|global}}_store_dwordx4 +; GCN-HSA: {{flat|global}}_store_dwordx4 +; GCN-HSA: {{flat|global}}_store_dwordx4 +; GCN-HSA: {{flat|global}}_store_dwordx4 +; GCN-HSA: {{flat|global}}_store_dwordx4 +; GCN-HSA: {{flat|global}}_store_dwordx4 define amdgpu_kernel void @global_zextload_v16i32_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i32> addrspace(1)* %in) #0 { %ld = load <16 x i32>, <16 x i32> addrspace(1)* %in %ext = zext <16 x i32> %ld to <16 x i64> @@ -362,14 +363,14 @@ define amdgpu_kernel void @global_zextload_v16i32_to_v16i64(<16 x i64> addrspace ; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA-DAG: buffer_load_dwordx4 -; GCN-HSA: flat_load_dwordx4 -; GCN-HSA: flat_load_dwordx4 -; GCN-HSA: flat_load_dwordx4 -; GCN-HSA: flat_load_dwordx4 -; GCN-HSA: flat_load_dwordx4 -; GCN-HSA: flat_load_dwordx4 -; GCN-HSA: flat_load_dwordx4 -; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 ; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32 @@ -424,25 +425,25 @@ define amdgpu_kernel void @global_zextload_v16i32_to_v16i64(<16 x i64> addrspace ; GCN-NOHSA: buffer_store_dwordx4 ; GCN-NOHSA: buffer_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 define amdgpu_kernel void @global_sextload_v32i32_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i32> addrspace(1)* %in) #0 { %ld = load <32 x i32>, <32 x i32> addrspace(1)* %in @@ -461,14 +462,14 @@ define amdgpu_kernel void @global_sextload_v32i32_to_v32i64(<32 x i64> addrspace ; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4 -; GCN-HSA: flat_load_dwordx4 -; GCN-HSA: flat_load_dwordx4 -; GCN-HSA: flat_load_dwordx4 -; GCN-HSA: flat_load_dwordx4 -; GCN-HSA: flat_load_dwordx4 -; GCN-HSA: flat_load_dwordx4 -; GCN-HSA: flat_load_dwordx4 -; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4 @@ -492,25 +493,25 @@ define amdgpu_kernel void @global_sextload_v32i32_to_v32i64(<32 x i64> addrspace ; GCN-NOHSA-DAG: buffer_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 -; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 define amdgpu_kernel void @global_zextload_v32i32_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i32> addrspace(1)* %in) #0 { %ld = load <32 x i32>, <32 x i32> addrspace(1)* %in %ext = zext <32 x i32> %ld to <32 x i64> @@ -518,4 +519,69 @@ define amdgpu_kernel void @global_zextload_v32i32_to_v32i64(<32 x i64> addrspace ret void } +; FUNC-LABEL: {{^}}global_load_v32i32: +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 + +; GCN-HSA: {{flat|global}}_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 +; GCN-HSA: {{flat|global}}_load_dwordx4 + + +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 + +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 + +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 + +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 + +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 + +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 + +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 + +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +; GCN-HSA-DAG: {{flat|global}}_store_dwordx4 +define amdgpu_kernel void @global_load_v32i32(<32 x i32> addrspace(1)* %out, <32 x i32> addrspace(1)* %in) #0 { + %ld = load <32 x i32>, <32 x i32> addrspace(1)* %in + store <32 x i32> %ld, <32 x i32> addrspace(1)* %out + ret void +} + attributes #0 = { nounwind } |
